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1 | /* |
2 | * This file contains miscellaneous low-level functions. | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) | |
6 | * and Paul Mackerras. | |
7 | * | |
3d1229d6 ME |
8 | * kexec bits: |
9 | * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> | |
10 | * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz | |
11 | * | |
9994a338 PM |
12 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | * | |
17 | */ | |
18 | ||
9994a338 PM |
19 | #include <linux/sys.h> |
20 | #include <asm/unistd.h> | |
21 | #include <asm/errno.h> | |
22 | #include <asm/reg.h> | |
23 | #include <asm/page.h> | |
24 | #include <asm/cache.h> | |
25 | #include <asm/cputable.h> | |
26 | #include <asm/mmu.h> | |
27 | #include <asm/ppc_asm.h> | |
28 | #include <asm/thread_info.h> | |
29 | #include <asm/asm-offsets.h> | |
3d1229d6 ME |
30 | #include <asm/processor.h> |
31 | #include <asm/kexec.h> | |
9994a338 PM |
32 | |
33 | .text | |
34 | ||
f2783c15 PM |
35 | /* |
36 | * This returns the high 64 bits of the product of two 64-bit numbers. | |
37 | */ | |
38 | _GLOBAL(mulhdu) | |
39 | cmpwi r6,0 | |
40 | cmpwi cr1,r3,0 | |
41 | mr r10,r4 | |
42 | mulhwu r4,r4,r5 | |
43 | beq 1f | |
44 | mulhwu r0,r10,r6 | |
45 | mullw r7,r10,r5 | |
46 | addc r7,r0,r7 | |
47 | addze r4,r4 | |
48 | 1: beqlr cr1 /* all done if high part of A is 0 */ | |
49 | mr r10,r3 | |
50 | mullw r9,r3,r5 | |
51 | mulhwu r3,r3,r5 | |
52 | beq 2f | |
53 | mullw r0,r10,r6 | |
54 | mulhwu r8,r10,r6 | |
55 | addc r7,r0,r7 | |
56 | adde r4,r4,r8 | |
57 | addze r3,r3 | |
58 | 2: addc r4,r4,r9 | |
59 | addze r3,r3 | |
60 | blr | |
61 | ||
9994a338 PM |
62 | /* |
63 | * sub_reloc_offset(x) returns x - reloc_offset(). | |
64 | */ | |
65 | _GLOBAL(sub_reloc_offset) | |
66 | mflr r0 | |
67 | bl 1f | |
68 | 1: mflr r5 | |
69 | lis r4,1b@ha | |
70 | addi r4,r4,1b@l | |
71 | subf r5,r4,r5 | |
72 | subf r3,r5,r3 | |
73 | mtlr r0 | |
74 | blr | |
75 | ||
76 | /* | |
77 | * reloc_got2 runs through the .got2 section adding an offset | |
78 | * to each entry. | |
79 | */ | |
80 | _GLOBAL(reloc_got2) | |
81 | mflr r11 | |
82 | lis r7,__got2_start@ha | |
83 | addi r7,r7,__got2_start@l | |
84 | lis r8,__got2_end@ha | |
85 | addi r8,r8,__got2_end@l | |
86 | subf r8,r7,r8 | |
87 | srwi. r8,r8,2 | |
88 | beqlr | |
89 | mtctr r8 | |
90 | bl 1f | |
91 | 1: mflr r0 | |
92 | lis r4,1b@ha | |
93 | addi r4,r4,1b@l | |
94 | subf r0,r4,r0 | |
95 | add r7,r0,r7 | |
96 | 2: lwz r0,0(r7) | |
97 | add r0,r0,r3 | |
98 | stw r0,0(r7) | |
99 | addi r7,r7,4 | |
100 | bdnz 2b | |
101 | mtlr r11 | |
102 | blr | |
103 | ||
104 | /* | |
105 | * identify_cpu, | |
106 | * called with r3 = data offset and r4 = CPU number | |
107 | * doesn't change r3 | |
108 | */ | |
109 | _GLOBAL(identify_cpu) | |
110 | addis r8,r3,cpu_specs@ha | |
111 | addi r8,r8,cpu_specs@l | |
112 | mfpvr r7 | |
113 | 1: | |
114 | lwz r5,CPU_SPEC_PVR_MASK(r8) | |
115 | and r5,r5,r7 | |
116 | lwz r6,CPU_SPEC_PVR_VALUE(r8) | |
117 | cmplw 0,r6,r5 | |
118 | beq 1f | |
119 | addi r8,r8,CPU_SPEC_ENTRY_SIZE | |
120 | b 1b | |
121 | 1: | |
122 | addis r6,r3,cur_cpu_spec@ha | |
123 | addi r6,r6,cur_cpu_spec@l | |
124 | sub r8,r8,r3 | |
125 | stw r8,0(r6) | |
126 | blr | |
127 | ||
128 | /* | |
129 | * do_cpu_ftr_fixups - goes through the list of CPU feature fixups | |
130 | * and writes nop's over sections of code that don't apply for this cpu. | |
131 | * r3 = data offset (not changed) | |
132 | */ | |
133 | _GLOBAL(do_cpu_ftr_fixups) | |
134 | /* Get CPU 0 features */ | |
135 | addis r6,r3,cur_cpu_spec@ha | |
136 | addi r6,r6,cur_cpu_spec@l | |
137 | lwz r4,0(r6) | |
138 | add r4,r4,r3 | |
139 | lwz r4,CPU_SPEC_FEATURES(r4) | |
140 | ||
141 | /* Get the fixup table */ | |
142 | addis r6,r3,__start___ftr_fixup@ha | |
143 | addi r6,r6,__start___ftr_fixup@l | |
144 | addis r7,r3,__stop___ftr_fixup@ha | |
145 | addi r7,r7,__stop___ftr_fixup@l | |
146 | ||
147 | /* Do the fixup */ | |
148 | 1: cmplw 0,r6,r7 | |
149 | bgelr | |
150 | addi r6,r6,16 | |
151 | lwz r8,-16(r6) /* mask */ | |
152 | and r8,r8,r4 | |
153 | lwz r9,-12(r6) /* value */ | |
154 | cmplw 0,r8,r9 | |
155 | beq 1b | |
156 | lwz r8,-8(r6) /* section begin */ | |
157 | lwz r9,-4(r6) /* section end */ | |
158 | subf. r9,r8,r9 | |
159 | beq 1b | |
160 | /* write nops over the section of code */ | |
161 | /* todo: if large section, add a branch at the start of it */ | |
162 | srwi r9,r9,2 | |
163 | mtctr r9 | |
164 | add r8,r8,r3 | |
165 | lis r0,0x60000000@h /* nop */ | |
166 | 3: stw r0,0(r8) | |
167 | andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l | |
168 | beq 2f | |
169 | dcbst 0,r8 /* suboptimal, but simpler */ | |
170 | sync | |
171 | icbi 0,r8 | |
172 | 2: addi r8,r8,4 | |
173 | bdnz 3b | |
174 | sync /* additional sync needed on g4 */ | |
175 | isync | |
176 | b 1b | |
177 | ||
178 | /* | |
179 | * call_setup_cpu - call the setup_cpu function for this cpu | |
180 | * r3 = data offset, r24 = cpu number | |
181 | * | |
182 | * Setup function is called with: | |
183 | * r3 = data offset | |
184 | * r4 = ptr to CPU spec (relocated) | |
185 | */ | |
186 | _GLOBAL(call_setup_cpu) | |
187 | addis r4,r3,cur_cpu_spec@ha | |
188 | addi r4,r4,cur_cpu_spec@l | |
189 | lwz r4,0(r4) | |
190 | add r4,r4,r3 | |
191 | lwz r5,CPU_SPEC_SETUP(r4) | |
b26f100d | 192 | cmpwi 0,r5,0 |
9994a338 PM |
193 | add r5,r5,r3 |
194 | beqlr | |
195 | mtctr r5 | |
196 | bctr | |
197 | ||
198 | #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) | |
199 | ||
200 | /* This gets called by via-pmu.c to switch the PLL selection | |
201 | * on 750fx CPU. This function should really be moved to some | |
202 | * other place (as most of the cpufreq code in via-pmu | |
203 | */ | |
204 | _GLOBAL(low_choose_750fx_pll) | |
205 | /* Clear MSR:EE */ | |
206 | mfmsr r7 | |
207 | rlwinm r0,r7,0,17,15 | |
208 | mtmsr r0 | |
209 | ||
210 | /* If switching to PLL1, disable HID0:BTIC */ | |
211 | cmplwi cr0,r3,0 | |
212 | beq 1f | |
213 | mfspr r5,SPRN_HID0 | |
214 | rlwinm r5,r5,0,27,25 | |
215 | sync | |
216 | mtspr SPRN_HID0,r5 | |
217 | isync | |
218 | sync | |
219 | ||
220 | 1: | |
221 | /* Calc new HID1 value */ | |
222 | mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ | |
223 | rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ | |
224 | rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ | |
225 | or r4,r4,r5 | |
226 | mtspr SPRN_HID1,r4 | |
227 | ||
228 | /* Store new HID1 image */ | |
229 | rlwinm r6,r1,0,0,18 | |
230 | lwz r6,TI_CPU(r6) | |
231 | slwi r6,r6,2 | |
232 | addis r6,r6,nap_save_hid1@ha | |
233 | stw r4,nap_save_hid1@l(r6) | |
234 | ||
235 | /* If switching to PLL0, enable HID0:BTIC */ | |
236 | cmplwi cr0,r3,0 | |
237 | bne 1f | |
238 | mfspr r5,SPRN_HID0 | |
239 | ori r5,r5,HID0_BTIC | |
240 | sync | |
241 | mtspr SPRN_HID0,r5 | |
242 | isync | |
243 | sync | |
244 | ||
245 | 1: | |
246 | /* Return */ | |
247 | mtmsr r7 | |
248 | blr | |
249 | ||
250 | _GLOBAL(low_choose_7447a_dfs) | |
251 | /* Clear MSR:EE */ | |
252 | mfmsr r7 | |
253 | rlwinm r0,r7,0,17,15 | |
254 | mtmsr r0 | |
255 | ||
256 | /* Calc new HID1 value */ | |
257 | mfspr r4,SPRN_HID1 | |
258 | insrwi r4,r3,1,9 /* insert parameter into bit 9 */ | |
259 | sync | |
260 | mtspr SPRN_HID1,r4 | |
261 | sync | |
262 | isync | |
263 | ||
264 | /* Return */ | |
265 | mtmsr r7 | |
266 | blr | |
267 | ||
268 | #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ | |
269 | ||
270 | /* | |
271 | * complement mask on the msr then "or" some values on. | |
272 | * _nmask_and_or_msr(nmask, value_to_or) | |
273 | */ | |
274 | _GLOBAL(_nmask_and_or_msr) | |
275 | mfmsr r0 /* Get current msr */ | |
276 | andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ | |
277 | or r0,r0,r4 /* Or on the bits in r4 (second parm) */ | |
278 | SYNC /* Some chip revs have problems here... */ | |
279 | mtmsr r0 /* Update machine state */ | |
280 | isync | |
281 | blr /* Done */ | |
282 | ||
283 | ||
284 | /* | |
285 | * Flush MMU TLB | |
286 | */ | |
287 | _GLOBAL(_tlbia) | |
288 | #if defined(CONFIG_40x) | |
289 | sync /* Flush to memory before changing mapping */ | |
290 | tlbia | |
291 | isync /* Flush shadow TLB */ | |
292 | #elif defined(CONFIG_44x) | |
293 | li r3,0 | |
294 | sync | |
295 | ||
296 | /* Load high watermark */ | |
297 | lis r4,tlb_44x_hwater@ha | |
298 | lwz r5,tlb_44x_hwater@l(r4) | |
299 | ||
300 | 1: tlbwe r3,r3,PPC44x_TLB_PAGEID | |
301 | addi r3,r3,1 | |
302 | cmpw 0,r3,r5 | |
303 | ble 1b | |
304 | ||
305 | isync | |
306 | #elif defined(CONFIG_FSL_BOOKE) | |
307 | /* Invalidate all entries in TLB0 */ | |
308 | li r3, 0x04 | |
309 | tlbivax 0,3 | |
310 | /* Invalidate all entries in TLB1 */ | |
311 | li r3, 0x0c | |
312 | tlbivax 0,3 | |
313 | /* Invalidate all entries in TLB2 */ | |
314 | li r3, 0x14 | |
315 | tlbivax 0,3 | |
316 | /* Invalidate all entries in TLB3 */ | |
317 | li r3, 0x1c | |
318 | tlbivax 0,3 | |
319 | msync | |
320 | #ifdef CONFIG_SMP | |
321 | tlbsync | |
322 | #endif /* CONFIG_SMP */ | |
323 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
324 | #if defined(CONFIG_SMP) | |
325 | rlwinm r8,r1,0,0,18 | |
326 | lwz r8,TI_CPU(r8) | |
327 | oris r8,r8,10 | |
328 | mfmsr r10 | |
329 | SYNC | |
330 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
331 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
332 | mtmsr r0 | |
333 | SYNC_601 | |
334 | isync | |
335 | lis r9,mmu_hash_lock@h | |
336 | ori r9,r9,mmu_hash_lock@l | |
337 | tophys(r9,r9) | |
338 | 10: lwarx r7,0,r9 | |
339 | cmpwi 0,r7,0 | |
340 | bne- 10b | |
341 | stwcx. r8,0,r9 | |
342 | bne- 10b | |
343 | sync | |
344 | tlbia | |
345 | sync | |
346 | TLBSYNC | |
347 | li r0,0 | |
348 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
349 | mtmsr r10 | |
350 | SYNC_601 | |
351 | isync | |
352 | #else /* CONFIG_SMP */ | |
353 | sync | |
354 | tlbia | |
355 | sync | |
356 | #endif /* CONFIG_SMP */ | |
357 | #endif /* ! defined(CONFIG_40x) */ | |
358 | blr | |
359 | ||
360 | /* | |
361 | * Flush MMU TLB for a particular address | |
362 | */ | |
363 | _GLOBAL(_tlbie) | |
364 | #if defined(CONFIG_40x) | |
365 | tlbsx. r3, 0, r3 | |
366 | bne 10f | |
367 | sync | |
368 | /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. | |
369 | * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate | |
370 | * the TLB entry. */ | |
371 | tlbwe r3, r3, TLB_TAG | |
372 | isync | |
373 | 10: | |
374 | #elif defined(CONFIG_44x) | |
375 | mfspr r4,SPRN_MMUCR | |
376 | mfspr r5,SPRN_PID /* Get PID */ | |
377 | rlwimi r4,r5,0,24,31 /* Set TID */ | |
378 | mtspr SPRN_MMUCR,r4 | |
379 | ||
380 | tlbsx. r3, 0, r3 | |
381 | bne 10f | |
382 | sync | |
383 | /* There are only 64 TLB entries, so r3 < 64, | |
384 | * which means bit 22, is clear. Since 22 is | |
385 | * the V bit in the TLB_PAGEID, loading this | |
386 | * value will invalidate the TLB entry. | |
387 | */ | |
388 | tlbwe r3, r3, PPC44x_TLB_PAGEID | |
389 | isync | |
390 | 10: | |
391 | #elif defined(CONFIG_FSL_BOOKE) | |
392 | rlwinm r4, r3, 0, 0, 19 | |
393 | ori r5, r4, 0x08 /* TLBSEL = 1 */ | |
394 | ori r6, r4, 0x10 /* TLBSEL = 2 */ | |
395 | ori r7, r4, 0x18 /* TLBSEL = 3 */ | |
396 | tlbivax 0, r4 | |
397 | tlbivax 0, r5 | |
398 | tlbivax 0, r6 | |
399 | tlbivax 0, r7 | |
400 | msync | |
401 | #if defined(CONFIG_SMP) | |
402 | tlbsync | |
403 | #endif /* CONFIG_SMP */ | |
404 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
405 | #if defined(CONFIG_SMP) | |
406 | rlwinm r8,r1,0,0,18 | |
407 | lwz r8,TI_CPU(r8) | |
408 | oris r8,r8,11 | |
409 | mfmsr r10 | |
410 | SYNC | |
411 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
412 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
413 | mtmsr r0 | |
414 | SYNC_601 | |
415 | isync | |
416 | lis r9,mmu_hash_lock@h | |
417 | ori r9,r9,mmu_hash_lock@l | |
418 | tophys(r9,r9) | |
419 | 10: lwarx r7,0,r9 | |
420 | cmpwi 0,r7,0 | |
421 | bne- 10b | |
422 | stwcx. r8,0,r9 | |
423 | bne- 10b | |
424 | eieio | |
425 | tlbie r3 | |
426 | sync | |
427 | TLBSYNC | |
428 | li r0,0 | |
429 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
430 | mtmsr r10 | |
431 | SYNC_601 | |
432 | isync | |
433 | #else /* CONFIG_SMP */ | |
434 | tlbie r3 | |
435 | sync | |
436 | #endif /* CONFIG_SMP */ | |
437 | #endif /* ! CONFIG_40x */ | |
438 | blr | |
439 | ||
440 | /* | |
441 | * Flush instruction cache. | |
442 | * This is a no-op on the 601. | |
443 | */ | |
444 | _GLOBAL(flush_instruction_cache) | |
445 | #if defined(CONFIG_8xx) | |
446 | isync | |
447 | lis r5, IDC_INVALL@h | |
448 | mtspr SPRN_IC_CST, r5 | |
449 | #elif defined(CONFIG_4xx) | |
450 | #ifdef CONFIG_403GCX | |
451 | li r3, 512 | |
452 | mtctr r3 | |
453 | lis r4, KERNELBASE@h | |
454 | 1: iccci 0, r4 | |
455 | addi r4, r4, 16 | |
456 | bdnz 1b | |
457 | #else | |
458 | lis r3, KERNELBASE@h | |
459 | iccci 0,r3 | |
460 | #endif | |
461 | #elif CONFIG_FSL_BOOKE | |
462 | BEGIN_FTR_SECTION | |
463 | mfspr r3,SPRN_L1CSR0 | |
464 | ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC | |
465 | /* msync; isync recommended here */ | |
466 | mtspr SPRN_L1CSR0,r3 | |
467 | isync | |
468 | blr | |
469 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |
470 | mfspr r3,SPRN_L1CSR1 | |
471 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR | |
472 | mtspr SPRN_L1CSR1,r3 | |
473 | #else | |
474 | mfspr r3,SPRN_PVR | |
475 | rlwinm r3,r3,16,16,31 | |
476 | cmpwi 0,r3,1 | |
477 | beqlr /* for 601, do nothing */ | |
478 | /* 603/604 processor - use invalidate-all bit in HID0 */ | |
479 | mfspr r3,SPRN_HID0 | |
480 | ori r3,r3,HID0_ICFI | |
481 | mtspr SPRN_HID0,r3 | |
482 | #endif /* CONFIG_8xx/4xx */ | |
483 | isync | |
484 | blr | |
485 | ||
486 | /* | |
487 | * Write any modified data cache blocks out to memory | |
488 | * and invalidate the corresponding instruction cache blocks. | |
489 | * This is a no-op on the 601. | |
490 | * | |
491 | * flush_icache_range(unsigned long start, unsigned long stop) | |
492 | */ | |
26ef5c09 | 493 | _GLOBAL(__flush_icache_range) |
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494 | BEGIN_FTR_SECTION |
495 | blr /* for 601, do nothing */ | |
496 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |
7dffb720 | 497 | li r5,L1_CACHE_BYTES-1 |
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498 | andc r3,r3,r5 |
499 | subf r4,r3,r4 | |
500 | add r4,r4,r5 | |
7dffb720 | 501 | srwi. r4,r4,L1_CACHE_SHIFT |
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502 | beqlr |
503 | mtctr r4 | |
504 | mr r6,r3 | |
505 | 1: dcbst 0,r3 | |
7dffb720 | 506 | addi r3,r3,L1_CACHE_BYTES |
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507 | bdnz 1b |
508 | sync /* wait for dcbst's to get to ram */ | |
509 | mtctr r4 | |
510 | 2: icbi 0,r6 | |
7dffb720 | 511 | addi r6,r6,L1_CACHE_BYTES |
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512 | bdnz 2b |
513 | sync /* additional sync needed on g4 */ | |
514 | isync | |
515 | blr | |
516 | /* | |
517 | * Write any modified data cache blocks out to memory. | |
518 | * Does not invalidate the corresponding cache lines (especially for | |
519 | * any corresponding instruction cache). | |
520 | * | |
521 | * clean_dcache_range(unsigned long start, unsigned long stop) | |
522 | */ | |
523 | _GLOBAL(clean_dcache_range) | |
7dffb720 | 524 | li r5,L1_CACHE_BYTES-1 |
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525 | andc r3,r3,r5 |
526 | subf r4,r3,r4 | |
527 | add r4,r4,r5 | |
7dffb720 | 528 | srwi. r4,r4,L1_CACHE_SHIFT |
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529 | beqlr |
530 | mtctr r4 | |
531 | ||
532 | 1: dcbst 0,r3 | |
7dffb720 | 533 | addi r3,r3,L1_CACHE_BYTES |
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534 | bdnz 1b |
535 | sync /* wait for dcbst's to get to ram */ | |
536 | blr | |
537 | ||
538 | /* | |
539 | * Write any modified data cache blocks out to memory and invalidate them. | |
540 | * Does not invalidate the corresponding instruction cache blocks. | |
541 | * | |
542 | * flush_dcache_range(unsigned long start, unsigned long stop) | |
543 | */ | |
544 | _GLOBAL(flush_dcache_range) | |
7dffb720 | 545 | li r5,L1_CACHE_BYTES-1 |
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546 | andc r3,r3,r5 |
547 | subf r4,r3,r4 | |
548 | add r4,r4,r5 | |
7dffb720 | 549 | srwi. r4,r4,L1_CACHE_SHIFT |
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550 | beqlr |
551 | mtctr r4 | |
552 | ||
553 | 1: dcbf 0,r3 | |
7dffb720 | 554 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
555 | bdnz 1b |
556 | sync /* wait for dcbst's to get to ram */ | |
557 | blr | |
558 | ||
559 | /* | |
560 | * Like above, but invalidate the D-cache. This is used by the 8xx | |
561 | * to invalidate the cache so the PPC core doesn't get stale data | |
562 | * from the CPM (no cache snooping here :-). | |
563 | * | |
564 | * invalidate_dcache_range(unsigned long start, unsigned long stop) | |
565 | */ | |
566 | _GLOBAL(invalidate_dcache_range) | |
7dffb720 | 567 | li r5,L1_CACHE_BYTES-1 |
9994a338 PM |
568 | andc r3,r3,r5 |
569 | subf r4,r3,r4 | |
570 | add r4,r4,r5 | |
7dffb720 | 571 | srwi. r4,r4,L1_CACHE_SHIFT |
9994a338 PM |
572 | beqlr |
573 | mtctr r4 | |
574 | ||
575 | 1: dcbi 0,r3 | |
7dffb720 | 576 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
577 | bdnz 1b |
578 | sync /* wait for dcbi's to get to ram */ | |
579 | blr | |
580 | ||
9994a338 PM |
581 | /* |
582 | * Flush a particular page from the data cache to RAM. | |
583 | * Note: this is necessary because the instruction cache does *not* | |
584 | * snoop from the data cache. | |
585 | * This is a no-op on the 601 which has a unified cache. | |
586 | * | |
587 | * void __flush_dcache_icache(void *page) | |
588 | */ | |
589 | _GLOBAL(__flush_dcache_icache) | |
590 | BEGIN_FTR_SECTION | |
591 | blr /* for 601, do nothing */ | |
592 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |
593 | rlwinm r3,r3,0,0,19 /* Get page base address */ | |
7dffb720 | 594 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
9994a338 PM |
595 | mtctr r4 |
596 | mr r6,r3 | |
597 | 0: dcbst 0,r3 /* Write line to ram */ | |
7dffb720 | 598 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
599 | bdnz 0b |
600 | sync | |
601 | mtctr r4 | |
602 | 1: icbi 0,r6 | |
7dffb720 | 603 | addi r6,r6,L1_CACHE_BYTES |
9994a338 PM |
604 | bdnz 1b |
605 | sync | |
606 | isync | |
607 | blr | |
608 | ||
609 | /* | |
610 | * Flush a particular page from the data cache to RAM, identified | |
611 | * by its physical address. We turn off the MMU so we can just use | |
612 | * the physical address (this may be a highmem page without a kernel | |
613 | * mapping). | |
614 | * | |
615 | * void __flush_dcache_icache_phys(unsigned long physaddr) | |
616 | */ | |
617 | _GLOBAL(__flush_dcache_icache_phys) | |
618 | BEGIN_FTR_SECTION | |
619 | blr /* for 601, do nothing */ | |
620 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | |
621 | mfmsr r10 | |
622 | rlwinm r0,r10,0,28,26 /* clear DR */ | |
623 | mtmsr r0 | |
624 | isync | |
625 | rlwinm r3,r3,0,0,19 /* Get page base address */ | |
7dffb720 | 626 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
9994a338 PM |
627 | mtctr r4 |
628 | mr r6,r3 | |
629 | 0: dcbst 0,r3 /* Write line to ram */ | |
7dffb720 | 630 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
631 | bdnz 0b |
632 | sync | |
633 | mtctr r4 | |
634 | 1: icbi 0,r6 | |
7dffb720 | 635 | addi r6,r6,L1_CACHE_BYTES |
9994a338 PM |
636 | bdnz 1b |
637 | sync | |
638 | mtmsr r10 /* restore DR */ | |
639 | isync | |
640 | blr | |
641 | ||
642 | /* | |
643 | * Clear pages using the dcbz instruction, which doesn't cause any | |
644 | * memory traffic (except to write out any cache lines which get | |
645 | * displaced). This only works on cacheable memory. | |
646 | * | |
647 | * void clear_pages(void *page, int order) ; | |
648 | */ | |
649 | _GLOBAL(clear_pages) | |
7dffb720 | 650 | li r0,4096/L1_CACHE_BYTES |
9994a338 PM |
651 | slw r0,r0,r4 |
652 | mtctr r0 | |
653 | #ifdef CONFIG_8xx | |
654 | li r4, 0 | |
655 | 1: stw r4, 0(r3) | |
656 | stw r4, 4(r3) | |
657 | stw r4, 8(r3) | |
658 | stw r4, 12(r3) | |
659 | #else | |
660 | 1: dcbz 0,r3 | |
661 | #endif | |
7dffb720 | 662 | addi r3,r3,L1_CACHE_BYTES |
9994a338 PM |
663 | bdnz 1b |
664 | blr | |
665 | ||
666 | /* | |
667 | * Copy a whole page. We use the dcbz instruction on the destination | |
668 | * to reduce memory traffic (it eliminates the unnecessary reads of | |
669 | * the destination into cache). This requires that the destination | |
670 | * is cacheable. | |
671 | */ | |
672 | #define COPY_16_BYTES \ | |
673 | lwz r6,4(r4); \ | |
674 | lwz r7,8(r4); \ | |
675 | lwz r8,12(r4); \ | |
676 | lwzu r9,16(r4); \ | |
677 | stw r6,4(r3); \ | |
678 | stw r7,8(r3); \ | |
679 | stw r8,12(r3); \ | |
680 | stwu r9,16(r3) | |
681 | ||
682 | _GLOBAL(copy_page) | |
683 | addi r3,r3,-4 | |
684 | addi r4,r4,-4 | |
685 | ||
686 | #ifdef CONFIG_8xx | |
687 | /* don't use prefetch on 8xx */ | |
7dffb720 | 688 | li r0,4096/L1_CACHE_BYTES |
9994a338 PM |
689 | mtctr r0 |
690 | 1: COPY_16_BYTES | |
691 | bdnz 1b | |
692 | blr | |
693 | ||
694 | #else /* not 8xx, we can prefetch */ | |
695 | li r5,4 | |
696 | ||
697 | #if MAX_COPY_PREFETCH > 1 | |
698 | li r0,MAX_COPY_PREFETCH | |
699 | li r11,4 | |
700 | mtctr r0 | |
701 | 11: dcbt r11,r4 | |
7dffb720 | 702 | addi r11,r11,L1_CACHE_BYTES |
9994a338 PM |
703 | bdnz 11b |
704 | #else /* MAX_COPY_PREFETCH == 1 */ | |
705 | dcbt r5,r4 | |
7dffb720 | 706 | li r11,L1_CACHE_BYTES+4 |
9994a338 | 707 | #endif /* MAX_COPY_PREFETCH */ |
7dffb720 | 708 | li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH |
9994a338 PM |
709 | crclr 4*cr0+eq |
710 | 2: | |
711 | mtctr r0 | |
712 | 1: | |
713 | dcbt r11,r4 | |
714 | dcbz r5,r3 | |
715 | COPY_16_BYTES | |
7dffb720 | 716 | #if L1_CACHE_BYTES >= 32 |
9994a338 | 717 | COPY_16_BYTES |
7dffb720 | 718 | #if L1_CACHE_BYTES >= 64 |
9994a338 PM |
719 | COPY_16_BYTES |
720 | COPY_16_BYTES | |
7dffb720 | 721 | #if L1_CACHE_BYTES >= 128 |
9994a338 PM |
722 | COPY_16_BYTES |
723 | COPY_16_BYTES | |
724 | COPY_16_BYTES | |
725 | COPY_16_BYTES | |
726 | #endif | |
727 | #endif | |
728 | #endif | |
729 | bdnz 1b | |
730 | beqlr | |
731 | crnot 4*cr0+eq,4*cr0+eq | |
732 | li r0,MAX_COPY_PREFETCH | |
733 | li r11,4 | |
734 | b 2b | |
735 | #endif /* CONFIG_8xx */ | |
736 | ||
737 | /* | |
738 | * void atomic_clear_mask(atomic_t mask, atomic_t *addr) | |
739 | * void atomic_set_mask(atomic_t mask, atomic_t *addr); | |
740 | */ | |
741 | _GLOBAL(atomic_clear_mask) | |
742 | 10: lwarx r5,0,r4 | |
743 | andc r5,r5,r3 | |
744 | PPC405_ERR77(0,r4) | |
745 | stwcx. r5,0,r4 | |
746 | bne- 10b | |
747 | blr | |
748 | _GLOBAL(atomic_set_mask) | |
749 | 10: lwarx r5,0,r4 | |
750 | or r5,r5,r3 | |
751 | PPC405_ERR77(0,r4) | |
752 | stwcx. r5,0,r4 | |
753 | bne- 10b | |
754 | blr | |
755 | ||
9994a338 PM |
756 | /* |
757 | * Extended precision shifts. | |
758 | * | |
759 | * Updated to be valid for shift counts from 0 to 63 inclusive. | |
760 | * -- Gabriel | |
761 | * | |
762 | * R3/R4 has 64 bit value | |
763 | * R5 has shift count | |
764 | * result in R3/R4 | |
765 | * | |
766 | * ashrdi3: arithmetic right shift (sign propagation) | |
767 | * lshrdi3: logical right shift | |
768 | * ashldi3: left shift | |
769 | */ | |
770 | _GLOBAL(__ashrdi3) | |
771 | subfic r6,r5,32 | |
772 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
773 | addi r7,r5,32 # could be xori, or addi with -32 | |
774 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
775 | rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 | |
776 | sraw r7,r3,r7 # t2 = MSW >> (count-32) | |
777 | or r4,r4,r6 # LSW |= t1 | |
778 | slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 | |
779 | sraw r3,r3,r5 # MSW = MSW >> count | |
780 | or r4,r4,r7 # LSW |= t2 | |
781 | blr | |
782 | ||
783 | _GLOBAL(__ashldi3) | |
784 | subfic r6,r5,32 | |
785 | slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count | |
786 | addi r7,r5,32 # could be xori, or addi with -32 | |
787 | srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) | |
788 | slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) | |
789 | or r3,r3,r6 # MSW |= t1 | |
790 | slw r4,r4,r5 # LSW = LSW << count | |
791 | or r3,r3,r7 # MSW |= t2 | |
792 | blr | |
793 | ||
794 | _GLOBAL(__lshrdi3) | |
795 | subfic r6,r5,32 | |
796 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
797 | addi r7,r5,32 # could be xori, or addi with -32 | |
798 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
799 | srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) | |
800 | or r4,r4,r6 # LSW |= t1 | |
801 | srw r3,r3,r5 # MSW = MSW >> count | |
802 | or r4,r4,r7 # LSW |= t2 | |
803 | blr | |
804 | ||
805 | _GLOBAL(abs) | |
806 | srawi r4,r3,31 | |
807 | xor r3,r3,r4 | |
808 | sub r3,r3,r4 | |
809 | blr | |
810 | ||
811 | _GLOBAL(_get_SP) | |
812 | mr r3,r1 /* Close enough */ | |
813 | blr | |
814 | ||
9994a338 PM |
815 | /* |
816 | * Create a kernel thread | |
817 | * kernel_thread(fn, arg, flags) | |
818 | */ | |
819 | _GLOBAL(kernel_thread) | |
820 | stwu r1,-16(r1) | |
821 | stw r30,8(r1) | |
822 | stw r31,12(r1) | |
823 | mr r30,r3 /* function */ | |
824 | mr r31,r4 /* argument */ | |
825 | ori r3,r5,CLONE_VM /* flags */ | |
826 | oris r3,r3,CLONE_UNTRACED>>16 | |
827 | li r4,0 /* new sp (unused) */ | |
828 | li r0,__NR_clone | |
829 | sc | |
830 | cmpwi 0,r3,0 /* parent or child? */ | |
831 | bne 1f /* return if parent */ | |
832 | li r0,0 /* make top-level stack frame */ | |
833 | stwu r0,-16(r1) | |
834 | mtlr r30 /* fn addr in lr */ | |
835 | mr r3,r31 /* load arg and call fn */ | |
836 | PPC440EP_ERR42 | |
837 | blrl | |
838 | li r0,__NR_exit /* exit if function returns */ | |
839 | li r3,0 | |
840 | sc | |
841 | 1: lwz r30,8(r1) | |
842 | lwz r31,12(r1) | |
843 | addi r1,r1,16 | |
844 | blr | |
845 | ||
846 | _GLOBAL(execve) | |
847 | li r0,__NR_execve | |
848 | sc | |
849 | bnslr | |
850 | neg r3,r3 | |
851 | blr | |
852 | ||
853 | /* | |
854 | * This routine is just here to keep GCC happy - sigh... | |
855 | */ | |
856 | _GLOBAL(__main) | |
857 | blr | |
3d1229d6 ME |
858 | |
859 | #ifdef CONFIG_KEXEC | |
860 | /* | |
861 | * Must be relocatable PIC code callable as a C function. | |
862 | */ | |
863 | .globl relocate_new_kernel | |
864 | relocate_new_kernel: | |
865 | /* r3 = page_list */ | |
866 | /* r4 = reboot_code_buffer */ | |
867 | /* r5 = start_address */ | |
868 | ||
869 | li r0, 0 | |
870 | ||
871 | /* | |
872 | * Set Machine Status Register to a known status, | |
873 | * switch the MMU off and jump to 1: in a single step. | |
874 | */ | |
875 | ||
876 | mr r8, r0 | |
877 | ori r8, r8, MSR_RI|MSR_ME | |
878 | mtspr SPRN_SRR1, r8 | |
879 | addi r8, r4, 1f - relocate_new_kernel | |
880 | mtspr SPRN_SRR0, r8 | |
881 | sync | |
882 | rfi | |
883 | ||
884 | 1: | |
885 | /* from this point address translation is turned off */ | |
886 | /* and interrupts are disabled */ | |
887 | ||
888 | /* set a new stack at the bottom of our page... */ | |
889 | /* (not really needed now) */ | |
890 | addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */ | |
891 | stw r0, 0(r1) | |
892 | ||
893 | /* Do the copies */ | |
894 | li r6, 0 /* checksum */ | |
895 | mr r0, r3 | |
896 | b 1f | |
897 | ||
898 | 0: /* top, read another word for the indirection page */ | |
899 | lwzu r0, 4(r3) | |
900 | ||
901 | 1: | |
902 | /* is it a destination page? (r8) */ | |
903 | rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ | |
904 | beq 2f | |
905 | ||
906 | rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
907 | b 0b | |
908 | ||
909 | 2: /* is it an indirection page? (r3) */ | |
910 | rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ | |
911 | beq 2f | |
912 | ||
913 | rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
914 | subi r3, r3, 4 | |
915 | b 0b | |
916 | ||
917 | 2: /* are we done? */ | |
918 | rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ | |
919 | beq 2f | |
920 | b 3f | |
921 | ||
922 | 2: /* is it a source page? (r9) */ | |
923 | rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ | |
924 | beq 0b | |
925 | ||
926 | rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
927 | ||
928 | li r7, PAGE_SIZE / 4 | |
929 | mtctr r7 | |
930 | subi r9, r9, 4 | |
931 | subi r8, r8, 4 | |
932 | 9: | |
933 | lwzu r0, 4(r9) /* do the copy */ | |
934 | xor r6, r6, r0 | |
935 | stwu r0, 4(r8) | |
936 | dcbst 0, r8 | |
937 | sync | |
938 | icbi 0, r8 | |
939 | bdnz 9b | |
940 | ||
941 | addi r9, r9, 4 | |
942 | addi r8, r8, 4 | |
943 | b 0b | |
944 | ||
945 | 3: | |
946 | ||
947 | /* To be certain of avoiding problems with self-modifying code | |
948 | * execute a serializing instruction here. | |
949 | */ | |
950 | isync | |
951 | sync | |
952 | ||
953 | /* jump to the entry point, usually the setup routine */ | |
954 | mtlr r5 | |
955 | blrl | |
956 | ||
957 | 1: b 1b | |
958 | ||
959 | relocate_new_kernel_end: | |
960 | ||
961 | .globl relocate_new_kernel_size | |
962 | relocate_new_kernel_size: | |
963 | .long relocate_new_kernel_end - relocate_new_kernel | |
964 | #endif |