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9994a338 | 1 | /* |
9994a338 PM |
2 | * This file contains miscellaneous low-level functions. |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) | |
6 | * and Paul Mackerras. | |
7 | * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com) | |
127efeb2 SR |
8 | * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) |
9 | * | |
9994a338 PM |
10 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | * | |
15 | */ | |
16 | ||
9994a338 PM |
17 | #include <linux/sys.h> |
18 | #include <asm/unistd.h> | |
19 | #include <asm/errno.h> | |
20 | #include <asm/processor.h> | |
21 | #include <asm/page.h> | |
22 | #include <asm/cache.h> | |
23 | #include <asm/ppc_asm.h> | |
24 | #include <asm/asm-offsets.h> | |
25 | #include <asm/cputable.h> | |
6cb7bfeb | 26 | #include <asm/thread_info.h> |
9994a338 PM |
27 | |
28 | .text | |
29 | ||
9994a338 PM |
30 | _GLOBAL(get_msr) |
31 | mfmsr r3 | |
32 | blr | |
33 | ||
9994a338 PM |
34 | _GLOBAL(get_srr0) |
35 | mfsrr0 r3 | |
36 | blr | |
37 | ||
38 | _GLOBAL(get_srr1) | |
39 | mfsrr1 r3 | |
40 | blr | |
9994a338 PM |
41 | |
42 | #ifdef CONFIG_IRQSTACKS | |
43 | _GLOBAL(call_do_softirq) | |
44 | mflr r0 | |
45 | std r0,16(r1) | |
46 | stdu r1,THREAD_SIZE-112(r3) | |
47 | mr r1,r3 | |
48 | bl .__do_softirq | |
49 | ld r1,0(r1) | |
50 | ld r0,16(r1) | |
51 | mtlr r0 | |
52 | blr | |
53 | ||
b9e5b4e6 BH |
54 | _GLOBAL(call_handle_irq) |
55 | ld r8,0(r7) | |
9994a338 PM |
56 | mflr r0 |
57 | std r0,16(r1) | |
b9e5b4e6 BH |
58 | mtctr r8 |
59 | stdu r1,THREAD_SIZE-112(r6) | |
60 | mr r1,r6 | |
61 | bctrl | |
9994a338 PM |
62 | ld r1,0(r1) |
63 | ld r0,16(r1) | |
64 | mtlr r0 | |
65 | blr | |
66 | #endif /* CONFIG_IRQSTACKS */ | |
67 | ||
9994a338 PM |
68 | .section ".toc","aw" |
69 | PPC64_CACHES: | |
70 | .tc ppc64_caches[TC],ppc64_caches | |
71 | .section ".text" | |
72 | ||
73 | /* | |
74 | * Write any modified data cache blocks out to memory | |
75 | * and invalidate the corresponding instruction cache blocks. | |
76 | * | |
77 | * flush_icache_range(unsigned long start, unsigned long stop) | |
78 | * | |
79 | * flush all bytes from start through stop-1 inclusive | |
80 | */ | |
81 | ||
82 | _KPROBE(__flush_icache_range) | |
83 | ||
84 | /* | |
85 | * Flush the data cache to memory | |
86 | * | |
87 | * Different systems have different cache line sizes | |
88 | * and in some cases i-cache and d-cache line sizes differ from | |
89 | * each other. | |
90 | */ | |
91 | ld r10,PPC64_CACHES@toc(r2) | |
92 | lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */ | |
93 | addi r5,r7,-1 | |
94 | andc r6,r3,r5 /* round low to line bdy */ | |
95 | subf r8,r6,r4 /* compute length */ | |
96 | add r8,r8,r5 /* ensure we get enough */ | |
97 | lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */ | |
98 | srw. r8,r8,r9 /* compute line count */ | |
99 | beqlr /* nothing to do? */ | |
100 | mtctr r8 | |
101 | 1: dcbst 0,r6 | |
102 | add r6,r6,r7 | |
103 | bdnz 1b | |
104 | sync | |
105 | ||
106 | /* Now invalidate the instruction cache */ | |
107 | ||
108 | lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */ | |
109 | addi r5,r7,-1 | |
110 | andc r6,r3,r5 /* round low to line bdy */ | |
111 | subf r8,r6,r4 /* compute length */ | |
112 | add r8,r8,r5 | |
113 | lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */ | |
114 | srw. r8,r8,r9 /* compute line count */ | |
115 | beqlr /* nothing to do? */ | |
116 | mtctr r8 | |
117 | 2: icbi 0,r6 | |
118 | add r6,r6,r7 | |
119 | bdnz 2b | |
120 | isync | |
121 | blr | |
122 | .previous .text | |
123 | /* | |
124 | * Like above, but only do the D-cache. | |
125 | * | |
126 | * flush_dcache_range(unsigned long start, unsigned long stop) | |
127 | * | |
128 | * flush all bytes from start to stop-1 inclusive | |
129 | */ | |
130 | _GLOBAL(flush_dcache_range) | |
131 | ||
132 | /* | |
133 | * Flush the data cache to memory | |
134 | * | |
135 | * Different systems have different cache line sizes | |
136 | */ | |
137 | ld r10,PPC64_CACHES@toc(r2) | |
138 | lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ | |
139 | addi r5,r7,-1 | |
140 | andc r6,r3,r5 /* round low to line bdy */ | |
141 | subf r8,r6,r4 /* compute length */ | |
142 | add r8,r8,r5 /* ensure we get enough */ | |
143 | lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ | |
144 | srw. r8,r8,r9 /* compute line count */ | |
145 | beqlr /* nothing to do? */ | |
146 | mtctr r8 | |
147 | 0: dcbst 0,r6 | |
148 | add r6,r6,r7 | |
149 | bdnz 0b | |
150 | sync | |
151 | blr | |
152 | ||
153 | /* | |
154 | * Like above, but works on non-mapped physical addresses. | |
155 | * Use only for non-LPAR setups ! It also assumes real mode | |
156 | * is cacheable. Used for flushing out the DART before using | |
157 | * it as uncacheable memory | |
158 | * | |
159 | * flush_dcache_phys_range(unsigned long start, unsigned long stop) | |
160 | * | |
161 | * flush all bytes from start to stop-1 inclusive | |
162 | */ | |
163 | _GLOBAL(flush_dcache_phys_range) | |
164 | ld r10,PPC64_CACHES@toc(r2) | |
165 | lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ | |
166 | addi r5,r7,-1 | |
167 | andc r6,r3,r5 /* round low to line bdy */ | |
168 | subf r8,r6,r4 /* compute length */ | |
169 | add r8,r8,r5 /* ensure we get enough */ | |
170 | lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ | |
171 | srw. r8,r8,r9 /* compute line count */ | |
172 | beqlr /* nothing to do? */ | |
173 | mfmsr r5 /* Disable MMU Data Relocation */ | |
174 | ori r0,r5,MSR_DR | |
175 | xori r0,r0,MSR_DR | |
176 | sync | |
177 | mtmsr r0 | |
178 | sync | |
179 | isync | |
180 | mtctr r8 | |
181 | 0: dcbst 0,r6 | |
182 | add r6,r6,r7 | |
183 | bdnz 0b | |
184 | sync | |
185 | isync | |
186 | mtmsr r5 /* Re-enable MMU Data Relocation */ | |
187 | sync | |
188 | isync | |
189 | blr | |
190 | ||
191 | _GLOBAL(flush_inval_dcache_range) | |
192 | ld r10,PPC64_CACHES@toc(r2) | |
193 | lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ | |
194 | addi r5,r7,-1 | |
195 | andc r6,r3,r5 /* round low to line bdy */ | |
196 | subf r8,r6,r4 /* compute length */ | |
197 | add r8,r8,r5 /* ensure we get enough */ | |
198 | lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */ | |
199 | srw. r8,r8,r9 /* compute line count */ | |
200 | beqlr /* nothing to do? */ | |
201 | sync | |
202 | isync | |
203 | mtctr r8 | |
204 | 0: dcbf 0,r6 | |
205 | add r6,r6,r7 | |
206 | bdnz 0b | |
207 | sync | |
208 | isync | |
209 | blr | |
210 | ||
211 | ||
212 | /* | |
213 | * Flush a particular page from the data cache to RAM. | |
214 | * Note: this is necessary because the instruction cache does *not* | |
215 | * snoop from the data cache. | |
216 | * | |
217 | * void __flush_dcache_icache(void *page) | |
218 | */ | |
219 | _GLOBAL(__flush_dcache_icache) | |
220 | /* | |
221 | * Flush the data cache to memory | |
222 | * | |
223 | * Different systems have different cache line sizes | |
224 | */ | |
225 | ||
226 | /* Flush the dcache */ | |
227 | ld r7,PPC64_CACHES@toc(r2) | |
228 | clrrdi r3,r3,PAGE_SHIFT /* Page align */ | |
229 | lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */ | |
230 | lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */ | |
231 | mr r6,r3 | |
232 | mtctr r4 | |
233 | 0: dcbst 0,r6 | |
234 | add r6,r6,r5 | |
235 | bdnz 0b | |
236 | sync | |
237 | ||
238 | /* Now invalidate the icache */ | |
239 | ||
240 | lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */ | |
241 | lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */ | |
242 | mtctr r4 | |
243 | 1: icbi 0,r3 | |
244 | add r3,r3,r5 | |
245 | bdnz 1b | |
246 | isync | |
247 | blr | |
9994a338 | 248 | |
9994a338 PM |
249 | /* |
250 | * identify_cpu and calls setup_cpu | |
251 | * In: r3 = base of the cpu_specs array | |
252 | * r4 = address of cur_cpu_spec | |
253 | * r5 = relocation offset | |
254 | */ | |
255 | _GLOBAL(identify_cpu) | |
256 | mfpvr r7 | |
257 | 1: | |
258 | lwz r8,CPU_SPEC_PVR_MASK(r3) | |
259 | and r8,r8,r7 | |
260 | lwz r9,CPU_SPEC_PVR_VALUE(r3) | |
261 | cmplw 0,r9,r8 | |
262 | beq 1f | |
263 | addi r3,r3,CPU_SPEC_ENTRY_SIZE | |
264 | b 1b | |
265 | 1: | |
266 | sub r0,r3,r5 | |
267 | std r0,0(r4) | |
268 | ld r4,CPU_SPEC_SETUP(r3) | |
b26f100d | 269 | cmpdi 0,r4,0 |
9994a338 | 270 | add r4,r4,r5 |
b26f100d | 271 | beqlr |
9994a338 PM |
272 | ld r4,0(r4) |
273 | add r4,r4,r5 | |
274 | mtctr r4 | |
275 | /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */ | |
276 | mr r4,r3 | |
277 | mr r3,r5 | |
278 | bctr | |
279 | ||
280 | /* | |
281 | * do_cpu_ftr_fixups - goes through the list of CPU feature fixups | |
282 | * and writes nop's over sections of code that don't apply for this cpu. | |
283 | * r3 = data offset (not changed) | |
284 | */ | |
285 | _GLOBAL(do_cpu_ftr_fixups) | |
286 | /* Get CPU 0 features */ | |
e58c3495 | 287 | LOAD_REG_IMMEDIATE(r6,cur_cpu_spec) |
9994a338 PM |
288 | sub r6,r6,r3 |
289 | ld r4,0(r6) | |
290 | sub r4,r4,r3 | |
291 | ld r4,CPU_SPEC_FEATURES(r4) | |
292 | /* Get the fixup table */ | |
e58c3495 | 293 | LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup) |
9994a338 | 294 | sub r6,r6,r3 |
e58c3495 | 295 | LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup) |
9994a338 PM |
296 | sub r7,r7,r3 |
297 | /* Do the fixup */ | |
298 | 1: cmpld r6,r7 | |
299 | bgelr | |
300 | addi r6,r6,32 | |
301 | ld r8,-32(r6) /* mask */ | |
302 | and r8,r8,r4 | |
303 | ld r9,-24(r6) /* value */ | |
304 | cmpld r8,r9 | |
305 | beq 1b | |
306 | ld r8,-16(r6) /* section begin */ | |
307 | ld r9,-8(r6) /* section end */ | |
308 | subf. r9,r8,r9 | |
309 | beq 1b | |
310 | /* write nops over the section of code */ | |
311 | /* todo: if large section, add a branch at the start of it */ | |
312 | srwi r9,r9,2 | |
313 | mtctr r9 | |
314 | sub r8,r8,r3 | |
315 | lis r0,0x60000000@h /* nop */ | |
316 | 3: stw r0,0(r8) | |
317 | andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l | |
318 | beq 2f | |
319 | dcbst 0,r8 /* suboptimal, but simpler */ | |
320 | sync | |
321 | icbi 0,r8 | |
322 | 2: addi r8,r8,4 | |
323 | bdnz 3b | |
324 | sync /* additional sync needed on g4 */ | |
325 | isync | |
326 | b 1b | |
327 | ||
328 | #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) | |
329 | /* | |
330 | * Do an IO access in real mode | |
331 | */ | |
332 | _GLOBAL(real_readb) | |
333 | mfmsr r7 | |
334 | ori r0,r7,MSR_DR | |
335 | xori r0,r0,MSR_DR | |
336 | sync | |
337 | mtmsrd r0 | |
338 | sync | |
339 | isync | |
340 | mfspr r6,SPRN_HID4 | |
341 | rldicl r5,r6,32,0 | |
342 | ori r5,r5,0x100 | |
343 | rldicl r5,r5,32,0 | |
344 | sync | |
345 | mtspr SPRN_HID4,r5 | |
346 | isync | |
347 | slbia | |
348 | isync | |
349 | lbz r3,0(r3) | |
350 | sync | |
351 | mtspr SPRN_HID4,r6 | |
352 | isync | |
353 | slbia | |
354 | isync | |
355 | mtmsrd r7 | |
356 | sync | |
357 | isync | |
358 | blr | |
359 | ||
360 | /* | |
361 | * Do an IO access in real mode | |
362 | */ | |
363 | _GLOBAL(real_writeb) | |
364 | mfmsr r7 | |
365 | ori r0,r7,MSR_DR | |
366 | xori r0,r0,MSR_DR | |
367 | sync | |
368 | mtmsrd r0 | |
369 | sync | |
370 | isync | |
371 | mfspr r6,SPRN_HID4 | |
372 | rldicl r5,r6,32,0 | |
373 | ori r5,r5,0x100 | |
374 | rldicl r5,r5,32,0 | |
375 | sync | |
376 | mtspr SPRN_HID4,r5 | |
377 | isync | |
378 | slbia | |
379 | isync | |
380 | stb r3,0(r4) | |
381 | sync | |
382 | mtspr SPRN_HID4,r6 | |
383 | isync | |
384 | slbia | |
385 | isync | |
386 | mtmsrd r7 | |
387 | sync | |
388 | isync | |
389 | blr | |
390 | #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ | |
391 | ||
127efeb2 | 392 | #ifdef CONFIG_CPU_FREQ_PMAC64 |
4350147a BH |
393 | /* |
394 | * SCOM access functions for 970 (FX only for now) | |
395 | * | |
396 | * unsigned long scom970_read(unsigned int address); | |
397 | * void scom970_write(unsigned int address, unsigned long value); | |
398 | * | |
399 | * The address passed in is the 24 bits register address. This code | |
400 | * is 970 specific and will not check the status bits, so you should | |
401 | * know what you are doing. | |
402 | */ | |
403 | _GLOBAL(scom970_read) | |
404 | /* interrupts off */ | |
405 | mfmsr r4 | |
406 | ori r0,r4,MSR_EE | |
407 | xori r0,r0,MSR_EE | |
408 | mtmsrd r0,1 | |
409 | ||
410 | /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits | |
411 | * (including parity). On current CPUs they must be 0'd, | |
412 | * and finally or in RW bit | |
413 | */ | |
414 | rlwinm r3,r3,8,0,15 | |
415 | ori r3,r3,0x8000 | |
416 | ||
417 | /* do the actual scom read */ | |
418 | sync | |
419 | mtspr SPRN_SCOMC,r3 | |
420 | isync | |
421 | mfspr r3,SPRN_SCOMD | |
422 | isync | |
423 | mfspr r0,SPRN_SCOMC | |
424 | isync | |
425 | ||
426 | /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah | |
427 | * that's the best we can do). Not implemented yet as we don't use | |
428 | * the scom on any of the bogus CPUs yet, but may have to be done | |
429 | * ultimately | |
430 | */ | |
431 | ||
432 | /* restore interrupts */ | |
433 | mtmsrd r4,1 | |
434 | blr | |
435 | ||
436 | ||
437 | _GLOBAL(scom970_write) | |
438 | /* interrupts off */ | |
439 | mfmsr r5 | |
440 | ori r0,r5,MSR_EE | |
441 | xori r0,r0,MSR_EE | |
442 | mtmsrd r0,1 | |
443 | ||
444 | /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits | |
445 | * (including parity). On current CPUs they must be 0'd. | |
446 | */ | |
447 | ||
448 | rlwinm r3,r3,8,0,15 | |
449 | ||
450 | sync | |
451 | mtspr SPRN_SCOMD,r4 /* write data */ | |
452 | isync | |
453 | mtspr SPRN_SCOMC,r3 /* write command */ | |
454 | isync | |
455 | mfspr 3,SPRN_SCOMC | |
456 | isync | |
457 | ||
458 | /* restore interrupts */ | |
459 | mtmsrd r5,1 | |
460 | blr | |
127efeb2 | 461 | #endif /* CONFIG_CPU_FREQ_PMAC64 */ |
4350147a BH |
462 | |
463 | ||
9994a338 PM |
464 | /* |
465 | * Create a kernel thread | |
466 | * kernel_thread(fn, arg, flags) | |
467 | */ | |
468 | _GLOBAL(kernel_thread) | |
469 | std r29,-24(r1) | |
470 | std r30,-16(r1) | |
471 | stdu r1,-STACK_FRAME_OVERHEAD(r1) | |
472 | mr r29,r3 | |
473 | mr r30,r4 | |
474 | ori r3,r5,CLONE_VM /* flags */ | |
475 | oris r3,r3,(CLONE_UNTRACED>>16) | |
476 | li r4,0 /* new sp (unused) */ | |
477 | li r0,__NR_clone | |
478 | sc | |
479 | cmpdi 0,r3,0 /* parent or child? */ | |
480 | bne 1f /* return if parent */ | |
481 | li r0,0 | |
482 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
483 | ld r2,8(r29) | |
484 | ld r29,0(r29) | |
485 | mtlr r29 /* fn addr in lr */ | |
486 | mr r3,r30 /* load arg and call fn */ | |
487 | blrl | |
488 | li r0,__NR_exit /* exit after child exits */ | |
489 | li r3,0 | |
490 | sc | |
491 | 1: addi r1,r1,STACK_FRAME_OVERHEAD | |
492 | ld r29,-24(r1) | |
493 | ld r30,-16(r1) | |
494 | blr | |
495 | ||
496 | /* | |
497 | * disable_kernel_fp() | |
498 | * Disable the FPU. | |
499 | */ | |
500 | _GLOBAL(disable_kernel_fp) | |
501 | mfmsr r3 | |
502 | rldicl r0,r3,(63-MSR_FP_LG),1 | |
503 | rldicl r3,r0,(MSR_FP_LG+1),0 | |
504 | mtmsrd r3 /* disable use of fpu now */ | |
505 | isync | |
506 | blr | |
507 | ||
508 | #ifdef CONFIG_ALTIVEC | |
509 | ||
510 | #if 0 /* this has no callers for now */ | |
511 | /* | |
512 | * disable_kernel_altivec() | |
513 | * Disable the VMX. | |
514 | */ | |
515 | _GLOBAL(disable_kernel_altivec) | |
516 | mfmsr r3 | |
517 | rldicl r0,r3,(63-MSR_VEC_LG),1 | |
518 | rldicl r3,r0,(MSR_VEC_LG+1),0 | |
519 | mtmsrd r3 /* disable use of VMX now */ | |
520 | isync | |
521 | blr | |
522 | #endif /* 0 */ | |
523 | ||
524 | /* | |
525 | * giveup_altivec(tsk) | |
526 | * Disable VMX for the task given as the argument, | |
527 | * and save the vector registers in its thread_struct. | |
528 | * Enables the VMX for use in the kernel on return. | |
529 | */ | |
530 | _GLOBAL(giveup_altivec) | |
531 | mfmsr r5 | |
532 | oris r5,r5,MSR_VEC@h | |
533 | mtmsrd r5 /* enable use of VMX now */ | |
534 | isync | |
535 | cmpdi 0,r3,0 | |
536 | beqlr- /* if no previous owner, done */ | |
537 | addi r3,r3,THREAD /* want THREAD of task */ | |
538 | ld r5,PT_REGS(r3) | |
539 | cmpdi 0,r5,0 | |
540 | SAVE_32VRS(0,r4,r3) | |
541 | mfvscr vr0 | |
542 | li r4,THREAD_VSCR | |
543 | stvx vr0,r4,r3 | |
544 | beq 1f | |
545 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
546 | lis r3,MSR_VEC@h | |
547 | andc r4,r4,r3 /* disable FP for previous task */ | |
548 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
549 | 1: | |
550 | #ifndef CONFIG_SMP | |
551 | li r5,0 | |
552 | ld r4,last_task_used_altivec@got(r2) | |
553 | std r5,0(r4) | |
554 | #endif /* CONFIG_SMP */ | |
555 | blr | |
556 | ||
557 | #endif /* CONFIG_ALTIVEC */ | |
558 | ||
9994a338 PM |
559 | _GLOBAL(execve) |
560 | li r0,__NR_execve | |
561 | sc | |
562 | bnslr | |
563 | neg r3,r3 | |
564 | blr | |
565 | ||
566 | /* kexec_wait(phys_cpu) | |
567 | * | |
568 | * wait for the flag to change, indicating this kernel is going away but | |
569 | * the slave code for the next one is at addresses 0 to 100. | |
570 | * | |
571 | * This is used by all slaves. | |
572 | * | |
573 | * Physical (hardware) cpu id should be in r3. | |
574 | */ | |
575 | _GLOBAL(kexec_wait) | |
576 | bl 1f | |
577 | 1: mflr r5 | |
578 | addi r5,r5,kexec_flag-1b | |
579 | ||
580 | 99: HMT_LOW | |
581 | #ifdef CONFIG_KEXEC /* use no memory without kexec */ | |
582 | lwz r4,0(r5) | |
583 | cmpwi 0,r4,0 | |
584 | bnea 0x60 | |
585 | #endif | |
586 | b 99b | |
587 | ||
588 | /* this can be in text because we won't change it until we are | |
589 | * running in real anyways | |
590 | */ | |
591 | kexec_flag: | |
592 | .long 0 | |
593 | ||
594 | ||
595 | #ifdef CONFIG_KEXEC | |
596 | ||
597 | /* kexec_smp_wait(void) | |
598 | * | |
599 | * call with interrupts off | |
600 | * note: this is a terminal routine, it does not save lr | |
601 | * | |
602 | * get phys id from paca | |
603 | * set paca id to -1 to say we got here | |
604 | * switch to real mode | |
605 | * join other cpus in kexec_wait(phys_id) | |
606 | */ | |
607 | _GLOBAL(kexec_smp_wait) | |
608 | lhz r3,PACAHWCPUID(r13) | |
609 | li r4,-1 | |
610 | sth r4,PACAHWCPUID(r13) /* let others know we left */ | |
611 | bl real_mode | |
612 | b .kexec_wait | |
613 | ||
614 | /* | |
615 | * switch to real mode (turn mmu off) | |
616 | * we use the early kernel trick that the hardware ignores bits | |
617 | * 0 and 1 (big endian) of the effective address in real mode | |
618 | * | |
619 | * don't overwrite r3 here, it is live for kexec_wait above. | |
620 | */ | |
621 | real_mode: /* assume normal blr return */ | |
622 | 1: li r9,MSR_RI | |
623 | li r10,MSR_DR|MSR_IR | |
624 | mflr r11 /* return address to SRR0 */ | |
625 | mfmsr r12 | |
626 | andc r9,r12,r9 | |
627 | andc r10,r12,r10 | |
628 | ||
629 | mtmsrd r9,1 | |
630 | mtspr SPRN_SRR1,r10 | |
631 | mtspr SPRN_SRR0,r11 | |
632 | rfid | |
633 | ||
634 | ||
635 | /* | |
636 | * kexec_sequence(newstack, start, image, control, clear_all()) | |
637 | * | |
638 | * does the grungy work with stack switching and real mode switches | |
639 | * also does simple calls to other code | |
640 | */ | |
641 | ||
642 | _GLOBAL(kexec_sequence) | |
643 | mflr r0 | |
644 | std r0,16(r1) | |
645 | ||
646 | /* switch stacks to newstack -- &kexec_stack.stack */ | |
647 | stdu r1,THREAD_SIZE-112(r3) | |
648 | mr r1,r3 | |
649 | ||
650 | li r0,0 | |
651 | std r0,16(r1) | |
652 | ||
653 | /* save regs for local vars on new stack. | |
654 | * yes, we won't go back, but ... | |
655 | */ | |
656 | std r31,-8(r1) | |
657 | std r30,-16(r1) | |
658 | std r29,-24(r1) | |
659 | std r28,-32(r1) | |
660 | std r27,-40(r1) | |
661 | std r26,-48(r1) | |
662 | std r25,-56(r1) | |
663 | ||
664 | stdu r1,-112-64(r1) | |
665 | ||
666 | /* save args into preserved regs */ | |
667 | mr r31,r3 /* newstack (both) */ | |
668 | mr r30,r4 /* start (real) */ | |
669 | mr r29,r5 /* image (virt) */ | |
670 | mr r28,r6 /* control, unused */ | |
671 | mr r27,r7 /* clear_all() fn desc */ | |
672 | mr r26,r8 /* spare */ | |
673 | lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */ | |
674 | ||
675 | /* disable interrupts, we are overwriting kernel data next */ | |
676 | mfmsr r3 | |
677 | rlwinm r3,r3,0,17,15 | |
678 | mtmsrd r3,1 | |
679 | ||
680 | /* copy dest pages, flush whole dest image */ | |
681 | mr r3,r29 | |
682 | bl .kexec_copy_flush /* (image) */ | |
683 | ||
684 | /* turn off mmu */ | |
685 | bl real_mode | |
686 | ||
687 | /* clear out hardware hash page table and tlb */ | |
688 | ld r5,0(r27) /* deref function descriptor */ | |
689 | mtctr r5 | |
690 | bctrl /* ppc_md.hash_clear_all(void); */ | |
691 | ||
692 | /* | |
693 | * kexec image calling is: | |
694 | * the first 0x100 bytes of the entry point are copied to 0 | |
695 | * | |
696 | * all slaves branch to slave = 0x60 (absolute) | |
697 | * slave(phys_cpu_id); | |
698 | * | |
699 | * master goes to start = entry point | |
700 | * start(phys_cpu_id, start, 0); | |
701 | * | |
702 | * | |
703 | * a wrapper is needed to call existing kernels, here is an approximate | |
704 | * description of one method: | |
705 | * | |
706 | * v2: (2.6.10) | |
707 | * start will be near the boot_block (maybe 0x100 bytes before it?) | |
708 | * it will have a 0x60, which will b to boot_block, where it will wait | |
709 | * and 0 will store phys into struct boot-block and load r3 from there, | |
710 | * copy kernel 0-0x100 and tell slaves to back down to 0x60 again | |
711 | * | |
712 | * v1: (2.6.9) | |
713 | * boot block will have all cpus scanning device tree to see if they | |
714 | * are the boot cpu ????? | |
715 | * other device tree differences (prop sizes, va vs pa, etc)... | |
716 | */ | |
717 | ||
718 | /* copy 0x100 bytes starting at start to 0 */ | |
719 | li r3,0 | |
720 | mr r4,r30 | |
721 | li r5,0x100 | |
722 | li r6,0 | |
723 | bl .copy_and_flush /* (dest, src, copy limit, start offset) */ | |
724 | 1: /* assume normal blr return */ | |
725 | ||
726 | /* release other cpus to the new kernel secondary start at 0x60 */ | |
727 | mflr r5 | |
728 | li r6,1 | |
729 | stw r6,kexec_flag-1b(5) | |
730 | mr r3,r25 # my phys cpu | |
731 | mr r4,r30 # start, aka phys mem offset | |
732 | mtlr 4 | |
733 | li r5,0 | |
734 | blr /* image->start(physid, image->start, 0); */ | |
735 | #endif /* CONFIG_KEXEC */ |