[POWERPC] Raise the upper limit of NR_CPUS and move the pacas into the BSS
[deliverable/linux.git] / arch / powerpc / kernel / paca.c
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1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
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10#include <linux/threads.h>
11#include <linux/module.h>
12
1da177e4 13#include <asm/lppaca.h>
1da177e4 14#include <asm/paca.h>
1da177e4
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15
16/* This symbol is provided by the linker - let it fill in the paca
17 * field correctly */
18extern unsigned long __toc_start;
19
3356bb9f 20/*
30ff2e87 21 * The structure which the hypervisor knows about - this structure
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22 * should not cross a page boundary. The vpa_init/register_vpa call
23 * is now known to fail if the lppaca structure crosses a page
30ff2e87
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24 * boundary. The lppaca is also used on legacy iSeries and POWER5
25 * pSeries boxes. The lppaca is 640 bytes long, and cannot readily
26 * change since the hypervisor knows its layout, so a 1kB alignment
27 * will suffice to ensure that it doesn't cross a page boundary.
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28 */
29struct lppaca lppaca[] = {
30 [0 ... (NR_CPUS-1)] = {
31 .desc = 0xd397d781, /* "LpPa" */
32 .size = sizeof(struct lppaca),
33 .dyn_proc_status = 2,
34 .decr_val = 0x00ff0000,
35 .fpregs_in_use = 1,
36 .end_of_quantum = 0xfffffffffffffffful,
37 .slb_count = 64,
38 .vmxregs_in_use = 0,
39 },
40};
41
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42/*
43 * 3 persistent SLBs are registered here. The buffer will be zero
44 * initially, hence will all be invaild until we actually write them.
45 */
46struct slb_shadow slb_shadow[] __cacheline_aligned = {
47 [0 ... (NR_CPUS-1)] = {
48 .persistent = SLB_NUM_BOLTED,
49 .buffer_length = sizeof(struct slb_shadow),
50 },
51};
52
8882a4da 53/* The Paca is an array with one entry per processor. Each contains an
1da177e4 54 * lppaca, which contains the information shared between the
1888e7b5 55 * hypervisor and Linux.
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56 * On systems with hardware multi-threading, there are two threads
57 * per processor. The Paca array must contain an entry for each thread.
58 * The VPD Areas will give a max logical processors = 2 * max physical
59 * processors. The processor VPD array needs one entry per physical
60 * processor (not thread).
61 */
90035fe3 62struct paca_struct paca[NR_CPUS];
1da177e4 63EXPORT_SYMBOL(paca);
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64
65void __init initialise_pacas(void)
66{
67 int cpu;
68
69 /* The TOC register (GPR2) points 32kB into the TOC, so that 64kB
70 * of the TOC can be addressed using a single machine instruction.
71 */
72 unsigned long kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL;
73
74 /* Can't use for_each_*_cpu, as they aren't functional yet */
75 for (cpu = 0; cpu < NR_CPUS; cpu++) {
76 struct paca_struct *new_paca = &paca[cpu];
77
78 new_paca->lppaca_ptr = &lppaca[cpu];
79 new_paca->lock_token = 0x8000;
80 new_paca->paca_index = cpu;
81 new_paca->kernel_toc = kernel_toc;
82 new_paca->hw_cpu_id = 0xffff;
83 new_paca->slb_shadow_ptr = &slb_shadow[cpu];
84 new_paca->__current = &init_task;
85
86 }
87}
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