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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
22ae782f | 24 | #include <linux/of_address.h> |
04bea68b | 25 | #include <linux/of_pci.h> |
5516b540 KG |
26 | #include <linux/mm.h> |
27 | #include <linux/list.h> | |
28 | #include <linux/syscalls.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 31 | #include <linux/slab.h> |
5516b540 KG |
32 | |
33 | #include <asm/processor.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/prom.h> | |
36 | #include <asm/pci-bridge.h> | |
37 | #include <asm/byteorder.h> | |
38 | #include <asm/machdep.h> | |
39 | #include <asm/ppc-pci.h> | |
40 | #include <asm/firmware.h> | |
8b8da358 | 41 | #include <asm/eeh.h> |
5516b540 | 42 | |
a4c9e328 | 43 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 44 | LIST_HEAD(hose_list); |
a4c9e328 KG |
45 | |
46 | /* XXX kill that some day ... */ | |
ebfc00f7 | 47 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 48 | |
25e81f92 BH |
49 | /* ISA Memory physical address */ |
50 | resource_size_t isa_mem_base; | |
51 | ||
1fd0f525 | 52 | /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ |
0e47ff1c | 53 | unsigned int pci_flags = 0; |
1fd0f525 | 54 | |
a4c9e328 | 55 | |
45223c54 | 56 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 57 | |
45223c54 | 58 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
59 | { |
60 | pci_dma_ops = dma_ops; | |
61 | } | |
62 | ||
45223c54 | 63 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
64 | { |
65 | return pci_dma_ops; | |
66 | } | |
67 | EXPORT_SYMBOL(get_pci_dma_ops); | |
68 | ||
e60516e3 | 69 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
70 | { |
71 | struct pci_controller *phb; | |
72 | ||
e60516e3 | 73 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
74 | if (phb == NULL) |
75 | return NULL; | |
e60516e3 SR |
76 | spin_lock(&hose_spinlock); |
77 | phb->global_number = global_phb_number++; | |
78 | list_add_tail(&phb->list_node, &hose_list); | |
79 | spin_unlock(&hose_spinlock); | |
44ef3390 | 80 | phb->dn = dev; |
a4c9e328 KG |
81 | phb->is_dynamic = mem_init_done; |
82 | #ifdef CONFIG_PPC64 | |
83 | if (dev) { | |
84 | int nid = of_node_to_nid(dev); | |
85 | ||
86 | if (nid < 0 || !node_online(nid)) | |
87 | nid = -1; | |
88 | ||
89 | PHB_SET_NODE(phb, nid); | |
90 | } | |
91 | #endif | |
92 | return phb; | |
93 | } | |
94 | ||
95 | void pcibios_free_controller(struct pci_controller *phb) | |
96 | { | |
97 | spin_lock(&hose_spinlock); | |
98 | list_del(&phb->list_node); | |
99 | spin_unlock(&hose_spinlock); | |
100 | ||
101 | if (phb->is_dynamic) | |
102 | kfree(phb); | |
103 | } | |
104 | ||
c3bd517d MM |
105 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
106 | { | |
107 | #ifdef CONFIG_PPC64 | |
108 | return hose->pci_io_size; | |
109 | #else | |
110 | return hose->io_resource.end - hose->io_resource.start + 1; | |
111 | #endif | |
112 | } | |
113 | ||
6dfbde20 BH |
114 | int pcibios_vaddr_is_ioport(void __iomem *address) |
115 | { | |
116 | int ret = 0; | |
117 | struct pci_controller *hose; | |
c3bd517d | 118 | resource_size_t size; |
6dfbde20 BH |
119 | |
120 | spin_lock(&hose_spinlock); | |
121 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 122 | size = pcibios_io_size(hose); |
6dfbde20 BH |
123 | if (address >= hose->io_base_virt && |
124 | address < (hose->io_base_virt + size)) { | |
125 | ret = 1; | |
126 | break; | |
127 | } | |
128 | } | |
129 | spin_unlock(&hose_spinlock); | |
130 | return ret; | |
131 | } | |
132 | ||
c3bd517d MM |
133 | unsigned long pci_address_to_pio(phys_addr_t address) |
134 | { | |
135 | struct pci_controller *hose; | |
136 | resource_size_t size; | |
137 | unsigned long ret = ~0; | |
138 | ||
139 | spin_lock(&hose_spinlock); | |
140 | list_for_each_entry(hose, &hose_list, list_node) { | |
141 | size = pcibios_io_size(hose); | |
142 | if (address >= hose->io_base_phys && | |
143 | address < (hose->io_base_phys + size)) { | |
144 | unsigned long base = | |
145 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
146 | ret = base + (address - hose->io_base_phys); | |
147 | break; | |
148 | } | |
149 | } | |
150 | spin_unlock(&hose_spinlock); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
155 | ||
5516b540 KG |
156 | /* |
157 | * Return the domain number for this bus. | |
158 | */ | |
159 | int pci_domain_nr(struct pci_bus *bus) | |
160 | { | |
6207e816 | 161 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 162 | |
6207e816 | 163 | return hose->global_number; |
5516b540 | 164 | } |
5516b540 | 165 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 166 | |
a4c9e328 KG |
167 | /* This routine is meant to be used early during boot, when the |
168 | * PCI bus numbers have not yet been assigned, and you need to | |
169 | * issue PCI config cycles to an OF device. | |
170 | * It could also be used to "fix" RTAS config cycles if you want | |
171 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
172 | * config cycles. | |
173 | */ | |
174 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
175 | { | |
a4c9e328 KG |
176 | while(node) { |
177 | struct pci_controller *hose, *tmp; | |
178 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 179 | if (hose->dn == node) |
a4c9e328 KG |
180 | return hose; |
181 | node = node->parent; | |
182 | } | |
183 | return NULL; | |
184 | } | |
185 | ||
58083dad KG |
186 | static ssize_t pci_show_devspec(struct device *dev, |
187 | struct device_attribute *attr, char *buf) | |
188 | { | |
189 | struct pci_dev *pdev; | |
190 | struct device_node *np; | |
191 | ||
192 | pdev = to_pci_dev (dev); | |
193 | np = pci_device_to_OF_node(pdev); | |
194 | if (np == NULL || np->full_name == NULL) | |
195 | return 0; | |
196 | return sprintf(buf, "%s", np->full_name); | |
197 | } | |
198 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
58083dad KG |
199 | |
200 | /* Add sysfs properties */ | |
4f3731da | 201 | int pcibios_add_platform_entries(struct pci_dev *pdev) |
58083dad | 202 | { |
4f3731da | 203 | return device_create_file(&pdev->dev, &dev_attr_devspec); |
58083dad KG |
204 | } |
205 | ||
a2b7390a | 206 | char __devinit *pcibios_setup(char *str) |
58083dad KG |
207 | { |
208 | return str; | |
209 | } | |
210 | ||
211 | /* | |
212 | * Reads the interrupt pin to determine if interrupt is use by card. | |
213 | * If the interrupt is used, then gets the interrupt line from the | |
214 | * openfirmware and sets it in the pci_dev and pci_config line. | |
215 | */ | |
216 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
217 | { | |
218 | struct of_irq oirq; | |
219 | unsigned int virq; | |
220 | ||
50c9bc2f BH |
221 | /* The current device-tree that iSeries generates from the HV |
222 | * PCI informations doesn't contain proper interrupt routing, | |
223 | * and all the fallback would do is print out crap, so we | |
224 | * don't attempt to resolve the interrupts here at all, some | |
225 | * iSeries specific fixup does it. | |
226 | * | |
227 | * In the long run, we will hopefully fix the generated device-tree | |
228 | * instead. | |
229 | */ | |
230 | #ifdef CONFIG_PPC_ISERIES | |
231 | if (firmware_has_feature(FW_FEATURE_ISERIES)) | |
232 | return -1; | |
233 | #endif | |
234 | ||
b0494bc8 | 235 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
236 | |
237 | #ifdef DEBUG | |
238 | memset(&oirq, 0xff, sizeof(oirq)); | |
239 | #endif | |
240 | /* Try to get a mapping from the device-tree */ | |
241 | if (of_irq_map_pci(pci_dev, &oirq)) { | |
242 | u8 line, pin; | |
243 | ||
244 | /* If that fails, lets fallback to what is in the config | |
245 | * space and map that through the default controller. We | |
246 | * also set the type to level low since that's what PCI | |
247 | * interrupts are. If your platform does differently, then | |
248 | * either provide a proper interrupt tree or don't use this | |
249 | * function. | |
250 | */ | |
251 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
252 | return -1; | |
253 | if (pin == 0) | |
254 | return -1; | |
255 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 256 | line == 0xff || line == 0) { |
58083dad KG |
257 | return -1; |
258 | } | |
b0494bc8 BH |
259 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
260 | line, pin); | |
58083dad KG |
261 | |
262 | virq = irq_create_mapping(NULL, line); | |
263 | if (virq != NO_IRQ) | |
ec775d0e | 264 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 265 | } else { |
b0494bc8 BH |
266 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
267 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
59b608c2 BH |
268 | oirq.controller ? oirq.controller->full_name : |
269 | "<default>"); | |
58083dad KG |
270 | |
271 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
272 | oirq.size); | |
273 | } | |
274 | if(virq == NO_IRQ) { | |
b0494bc8 | 275 | pr_debug(" Failed to map !\n"); |
58083dad KG |
276 | return -1; |
277 | } | |
278 | ||
b0494bc8 | 279 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
280 | |
281 | pci_dev->irq = virq; | |
282 | ||
283 | return 0; | |
284 | } | |
285 | EXPORT_SYMBOL(pci_read_irq_line); | |
286 | ||
287 | /* | |
288 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
289 | * modelled on the sparc64 implementation by Dave Miller. | |
290 | * -- paulus. | |
291 | */ | |
292 | ||
293 | /* | |
294 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
295 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
296 | * | |
297 | * Basically, the user finds the base address for his device which he wishes | |
298 | * to mmap. They read the 32-bit value from the config space base register, | |
299 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
300 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
301 | * | |
302 | * Returns negative error code on failure, zero on success. | |
303 | */ | |
304 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
305 | resource_size_t *offset, | |
306 | enum pci_mmap_state mmap_state) | |
307 | { | |
308 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
309 | unsigned long io_offset = 0; | |
310 | int i, res_bit; | |
311 | ||
312 | if (hose == 0) | |
313 | return NULL; /* should never happen */ | |
314 | ||
315 | /* If memory, add on the PCI bridge address offset */ | |
316 | if (mmap_state == pci_mmap_mem) { | |
317 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
318 | *offset += hose->pci_mem_offset; | |
319 | #endif | |
320 | res_bit = IORESOURCE_MEM; | |
321 | } else { | |
322 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
323 | *offset += io_offset; | |
324 | res_bit = IORESOURCE_IO; | |
325 | } | |
326 | ||
327 | /* | |
328 | * Check that the offset requested corresponds to one of the | |
329 | * resources of the device. | |
330 | */ | |
331 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
332 | struct resource *rp = &dev->resource[i]; | |
333 | int flags = rp->flags; | |
334 | ||
335 | /* treat ROM as memory (should be already) */ | |
336 | if (i == PCI_ROM_RESOURCE) | |
337 | flags |= IORESOURCE_MEM; | |
338 | ||
339 | /* Active and same type? */ | |
340 | if ((flags & res_bit) == 0) | |
341 | continue; | |
342 | ||
343 | /* In the range of this resource? */ | |
344 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
345 | continue; | |
346 | ||
347 | /* found it! construct the final physical address */ | |
348 | if (mmap_state == pci_mmap_io) | |
349 | *offset += hose->io_base_phys - io_offset; | |
350 | return rp; | |
351 | } | |
352 | ||
353 | return NULL; | |
354 | } | |
355 | ||
356 | /* | |
357 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
358 | * device mapping. | |
359 | */ | |
360 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
361 | pgprot_t protection, | |
362 | enum pci_mmap_state mmap_state, | |
363 | int write_combine) | |
364 | { | |
365 | unsigned long prot = pgprot_val(protection); | |
366 | ||
367 | /* Write combine is always 0 on non-memory space mappings. On | |
368 | * memory space, if the user didn't pass 1, we check for a | |
369 | * "prefetchable" resource. This is a bit hackish, but we use | |
370 | * this to workaround the inability of /sysfs to provide a write | |
371 | * combine bit | |
372 | */ | |
373 | if (mmap_state != pci_mmap_mem) | |
374 | write_combine = 0; | |
375 | else if (write_combine == 0) { | |
376 | if (rp->flags & IORESOURCE_PREFETCH) | |
377 | write_combine = 1; | |
378 | } | |
379 | ||
380 | /* XXX would be nice to have a way to ask for write-through */ | |
58083dad | 381 | if (write_combine) |
64b3d0e8 | 382 | return pgprot_noncached_wc(prot); |
58083dad | 383 | else |
64b3d0e8 | 384 | return pgprot_noncached(prot); |
58083dad KG |
385 | } |
386 | ||
387 | /* | |
388 | * This one is used by /dev/mem and fbdev who have no clue about the | |
389 | * PCI device, it tries to find the PCI device first and calls the | |
390 | * above routine | |
391 | */ | |
392 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
393 | unsigned long pfn, | |
394 | unsigned long size, | |
64b3d0e8 | 395 | pgprot_t prot) |
58083dad KG |
396 | { |
397 | struct pci_dev *pdev = NULL; | |
398 | struct resource *found = NULL; | |
7c12d906 | 399 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
400 | int i; |
401 | ||
402 | if (page_is_ram(pfn)) | |
64b3d0e8 | 403 | return prot; |
58083dad | 404 | |
64b3d0e8 | 405 | prot = pgprot_noncached(prot); |
58083dad KG |
406 | for_each_pci_dev(pdev) { |
407 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
408 | struct resource *rp = &pdev->resource[i]; | |
409 | int flags = rp->flags; | |
410 | ||
411 | /* Active and same type? */ | |
412 | if ((flags & IORESOURCE_MEM) == 0) | |
413 | continue; | |
414 | /* In the range of this resource? */ | |
415 | if (offset < (rp->start & PAGE_MASK) || | |
416 | offset > rp->end) | |
417 | continue; | |
418 | found = rp; | |
419 | break; | |
420 | } | |
421 | if (found) | |
422 | break; | |
423 | } | |
424 | if (found) { | |
425 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 426 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
427 | pci_dev_put(pdev); |
428 | } | |
429 | ||
b0494bc8 | 430 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 431 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 432 | |
64b3d0e8 | 433 | return prot; |
58083dad KG |
434 | } |
435 | ||
436 | ||
437 | /* | |
438 | * Perform the actual remap of the pages for a PCI device mapping, as | |
439 | * appropriate for this architecture. The region in the process to map | |
440 | * is described by vm_start and vm_end members of VMA, the base physical | |
441 | * address is found in vm_pgoff. | |
442 | * The pci device structure is provided so that architectures may make mapping | |
443 | * decisions on a per-device or per-bus basis. | |
444 | * | |
445 | * Returns a negative error code on failure, zero on success. | |
446 | */ | |
447 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
448 | enum pci_mmap_state mmap_state, int write_combine) | |
449 | { | |
7c12d906 BH |
450 | resource_size_t offset = |
451 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
452 | struct resource *rp; |
453 | int ret; | |
454 | ||
455 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
456 | if (rp == NULL) | |
457 | return -EINVAL; | |
458 | ||
459 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
460 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
461 | vma->vm_page_prot, | |
462 | mmap_state, write_combine); | |
463 | ||
464 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
465 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
466 | ||
467 | return ret; | |
468 | } | |
469 | ||
e9f82cb7 BH |
470 | /* This provides legacy IO read access on a bus */ |
471 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
472 | { | |
473 | unsigned long offset; | |
474 | struct pci_controller *hose = pci_bus_to_host(bus); | |
475 | struct resource *rp = &hose->io_resource; | |
476 | void __iomem *addr; | |
477 | ||
478 | /* Check if port can be supported by that bus. We only check | |
479 | * the ranges of the PHB though, not the bus itself as the rules | |
480 | * for forwarding legacy cycles down bridges are not our problem | |
481 | * here. So if the host bridge supports it, we do it. | |
482 | */ | |
483 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
484 | offset += port; | |
485 | ||
486 | if (!(rp->flags & IORESOURCE_IO)) | |
487 | return -ENXIO; | |
488 | if (offset < rp->start || (offset + size) > rp->end) | |
489 | return -ENXIO; | |
490 | addr = hose->io_base_virt + port; | |
491 | ||
492 | switch(size) { | |
493 | case 1: | |
494 | *((u8 *)val) = in_8(addr); | |
495 | return 1; | |
496 | case 2: | |
497 | if (port & 1) | |
498 | return -EINVAL; | |
499 | *((u16 *)val) = in_le16(addr); | |
500 | return 2; | |
501 | case 4: | |
502 | if (port & 3) | |
503 | return -EINVAL; | |
504 | *((u32 *)val) = in_le32(addr); | |
505 | return 4; | |
506 | } | |
507 | return -EINVAL; | |
508 | } | |
509 | ||
510 | /* This provides legacy IO write access on a bus */ | |
511 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
512 | { | |
513 | unsigned long offset; | |
514 | struct pci_controller *hose = pci_bus_to_host(bus); | |
515 | struct resource *rp = &hose->io_resource; | |
516 | void __iomem *addr; | |
517 | ||
518 | /* Check if port can be supported by that bus. We only check | |
519 | * the ranges of the PHB though, not the bus itself as the rules | |
520 | * for forwarding legacy cycles down bridges are not our problem | |
521 | * here. So if the host bridge supports it, we do it. | |
522 | */ | |
523 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
524 | offset += port; | |
525 | ||
526 | if (!(rp->flags & IORESOURCE_IO)) | |
527 | return -ENXIO; | |
528 | if (offset < rp->start || (offset + size) > rp->end) | |
529 | return -ENXIO; | |
530 | addr = hose->io_base_virt + port; | |
531 | ||
532 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
533 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
534 | * as a u32, which means that we have to correct the location of | |
535 | * the data read within those 32 bits for size 1 and 2 | |
536 | */ | |
537 | switch(size) { | |
538 | case 1: | |
539 | out_8(addr, val >> 24); | |
540 | return 1; | |
541 | case 2: | |
542 | if (port & 1) | |
543 | return -EINVAL; | |
544 | out_le16(addr, val >> 16); | |
545 | return 2; | |
546 | case 4: | |
547 | if (port & 3) | |
548 | return -EINVAL; | |
549 | out_le32(addr, val); | |
550 | return 4; | |
551 | } | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
555 | /* This provides legacy IO or memory mmap access on a bus */ | |
556 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
557 | struct vm_area_struct *vma, | |
558 | enum pci_mmap_state mmap_state) | |
559 | { | |
560 | struct pci_controller *hose = pci_bus_to_host(bus); | |
561 | resource_size_t offset = | |
562 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
563 | resource_size_t size = vma->vm_end - vma->vm_start; | |
564 | struct resource *rp; | |
565 | ||
566 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
567 | pci_domain_nr(bus), bus->number, | |
568 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
569 | (unsigned long long)offset, | |
570 | (unsigned long long)(offset + size - 1)); | |
571 | ||
572 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
573 | /* Hack alert ! |
574 | * | |
575 | * Because X is lame and can fail starting if it gets an error trying | |
576 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
577 | * access) we fake it here by giving it anonymous memory, effectively | |
578 | * behaving just like /dev/zero | |
579 | */ | |
580 | if ((offset + size) > hose->isa_mem_size) { | |
581 | printk(KERN_DEBUG | |
582 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
583 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
584 | if (vma->vm_flags & VM_SHARED) | |
585 | return shmem_zero_setup(vma); | |
586 | return 0; | |
587 | } | |
e9f82cb7 BH |
588 | offset += hose->isa_mem_phys; |
589 | } else { | |
590 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
591 | unsigned long roffset = offset + io_offset; | |
592 | rp = &hose->io_resource; | |
593 | if (!(rp->flags & IORESOURCE_IO)) | |
594 | return -ENXIO; | |
595 | if (roffset < rp->start || (roffset + size) > rp->end) | |
596 | return -ENXIO; | |
597 | offset += hose->io_base_phys; | |
598 | } | |
599 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
600 | ||
601 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 602 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
603 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
604 | vma->vm_end - vma->vm_start, | |
605 | vma->vm_page_prot); | |
606 | } | |
607 | ||
58083dad KG |
608 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
609 | const struct resource *rsrc, | |
610 | resource_size_t *start, resource_size_t *end) | |
611 | { | |
612 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
613 | resource_size_t offset = 0; | |
614 | ||
615 | if (hose == NULL) | |
616 | return; | |
617 | ||
618 | if (rsrc->flags & IORESOURCE_IO) | |
619 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
620 | ||
621 | /* We pass a fully fixed up address to userland for MMIO instead of | |
622 | * a BAR value because X is lame and expects to be able to use that | |
623 | * to pass to /dev/mem ! | |
624 | * | |
625 | * That means that we'll have potentially 64 bits values where some | |
626 | * userland apps only expect 32 (like X itself since it thinks only | |
627 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
628 | * 32 bits CHRPs :-( | |
629 | * | |
630 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
631 | * has been fixed (and the fix spread enough), we can re-enable the | |
632 | * 2 lines below and pass down a BAR value to userland. In that case | |
633 | * we'll also have to re-enable the matching code in | |
634 | * __pci_mmap_make_offset(). | |
635 | * | |
636 | * BenH. | |
637 | */ | |
638 | #if 0 | |
639 | else if (rsrc->flags & IORESOURCE_MEM) | |
640 | offset = hose->pci_mem_offset; | |
641 | #endif | |
642 | ||
643 | *start = rsrc->start - offset; | |
644 | *end = rsrc->end - offset; | |
645 | } | |
13dccb9e BH |
646 | |
647 | /** | |
648 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
649 | * @hose: newly allocated pci_controller to be setup | |
650 | * @dev: device node of the host bridge | |
651 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
652 | * | |
653 | * This function will parse the "ranges" property of a PCI host bridge device | |
654 | * node and setup the resource mapping of a pci controller based on its | |
655 | * content. | |
656 | * | |
657 | * Life would be boring if it wasn't for a few issues that we have to deal | |
658 | * with here: | |
659 | * | |
660 | * - We can only cope with one IO space range and up to 3 Memory space | |
661 | * ranges. However, some machines (thanks Apple !) tend to split their | |
662 | * space into lots of small contiguous ranges. So we have to coalesce. | |
663 | * | |
664 | * - We can only cope with all memory ranges having the same offset | |
665 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
666 | * are setup for a large 1:1 mapping along with a small "window" which | |
667 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
668 | * order to give access to the ISA memory hole. | |
669 | * The way out of here that I've chosen for now is to always set the | |
670 | * offset based on the first resource found, then override it if we | |
671 | * have a different offset and the previous was set by an ISA hole. | |
672 | * | |
673 | * - Some busses have IO space not starting at 0, which causes trouble with | |
674 | * the way we do our IO resource renumbering. The code somewhat deals with | |
675 | * it for 64 bits but I would expect problems on 32 bits. | |
676 | * | |
677 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
678 | * 32 bits so we need to use 64 bits values for the parsing | |
679 | */ | |
680 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
681 | struct device_node *dev, | |
682 | int primary) | |
683 | { | |
684 | const u32 *ranges; | |
685 | int rlen; | |
686 | int pna = of_n_addr_cells(dev); | |
687 | int np = pna + 5; | |
688 | int memno = 0, isa_hole = -1; | |
689 | u32 pci_space; | |
690 | unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; | |
691 | unsigned long long isa_mb = 0; | |
692 | struct resource *res; | |
693 | ||
694 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
695 | dev->full_name, primary ? "(primary)" : ""); | |
696 | ||
697 | /* Get ranges property */ | |
698 | ranges = of_get_property(dev, "ranges", &rlen); | |
699 | if (ranges == NULL) | |
700 | return; | |
701 | ||
702 | /* Parse it */ | |
703 | while ((rlen -= np * 4) >= 0) { | |
704 | /* Read next ranges element */ | |
705 | pci_space = ranges[0]; | |
706 | pci_addr = of_read_number(ranges + 1, 2); | |
707 | cpu_addr = of_translate_address(dev, ranges + 3); | |
708 | size = of_read_number(ranges + pna + 3, 2); | |
709 | ranges += np; | |
e9f82cb7 BH |
710 | |
711 | /* If we failed translation or got a zero-sized region | |
712 | * (some FW try to feed us with non sensical zero sized regions | |
713 | * such as power3 which look like some kind of attempt at exposing | |
714 | * the VGA memory hole) | |
715 | */ | |
13dccb9e BH |
716 | if (cpu_addr == OF_BAD_ADDR || size == 0) |
717 | continue; | |
718 | ||
719 | /* Now consume following elements while they are contiguous */ | |
720 | for (; rlen >= np * sizeof(u32); | |
721 | ranges += np, rlen -= np * 4) { | |
722 | if (ranges[0] != pci_space) | |
723 | break; | |
724 | pci_next = of_read_number(ranges + 1, 2); | |
725 | cpu_next = of_translate_address(dev, ranges + 3); | |
726 | if (pci_next != pci_addr + size || | |
727 | cpu_next != cpu_addr + size) | |
728 | break; | |
729 | size += of_read_number(ranges + pna + 3, 2); | |
730 | } | |
731 | ||
732 | /* Act based on address space type */ | |
733 | res = NULL; | |
734 | switch ((pci_space >> 24) & 0x3) { | |
735 | case 1: /* PCI IO space */ | |
736 | printk(KERN_INFO | |
737 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
738 | cpu_addr, cpu_addr + size - 1, pci_addr); | |
739 | ||
740 | /* We support only one IO range */ | |
741 | if (hose->pci_io_size) { | |
742 | printk(KERN_INFO | |
743 | " \\--> Skipped (too many) !\n"); | |
744 | continue; | |
745 | } | |
746 | #ifdef CONFIG_PPC32 | |
747 | /* On 32 bits, limit I/O space to 16MB */ | |
748 | if (size > 0x01000000) | |
749 | size = 0x01000000; | |
750 | ||
751 | /* 32 bits needs to map IOs here */ | |
752 | hose->io_base_virt = ioremap(cpu_addr, size); | |
753 | ||
754 | /* Expect trouble if pci_addr is not 0 */ | |
755 | if (primary) | |
756 | isa_io_base = | |
757 | (unsigned long)hose->io_base_virt; | |
758 | #endif /* CONFIG_PPC32 */ | |
759 | /* pci_io_size and io_base_phys always represent IO | |
760 | * space starting at 0 so we factor in pci_addr | |
761 | */ | |
762 | hose->pci_io_size = pci_addr + size; | |
763 | hose->io_base_phys = cpu_addr - pci_addr; | |
764 | ||
765 | /* Build resource */ | |
766 | res = &hose->io_resource; | |
767 | res->flags = IORESOURCE_IO; | |
768 | res->start = pci_addr; | |
769 | break; | |
770 | case 2: /* PCI Memory space */ | |
67260ac9 | 771 | case 3: /* PCI 64 bits Memory space */ |
13dccb9e BH |
772 | printk(KERN_INFO |
773 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
774 | cpu_addr, cpu_addr + size - 1, pci_addr, | |
775 | (pci_space & 0x40000000) ? "Prefetch" : ""); | |
776 | ||
777 | /* We support only 3 memory ranges */ | |
778 | if (memno >= 3) { | |
779 | printk(KERN_INFO | |
780 | " \\--> Skipped (too many) !\n"); | |
781 | continue; | |
782 | } | |
783 | /* Handles ISA memory hole space here */ | |
784 | if (pci_addr == 0) { | |
785 | isa_mb = cpu_addr; | |
786 | isa_hole = memno; | |
787 | if (primary || isa_mem_base == 0) | |
788 | isa_mem_base = cpu_addr; | |
e9f82cb7 BH |
789 | hose->isa_mem_phys = cpu_addr; |
790 | hose->isa_mem_size = size; | |
13dccb9e BH |
791 | } |
792 | ||
793 | /* We get the PCI/Mem offset from the first range or | |
794 | * the, current one if the offset came from an ISA | |
795 | * hole. If they don't match, bugger. | |
796 | */ | |
797 | if (memno == 0 || | |
798 | (isa_hole >= 0 && pci_addr != 0 && | |
799 | hose->pci_mem_offset == isa_mb)) | |
800 | hose->pci_mem_offset = cpu_addr - pci_addr; | |
801 | else if (pci_addr != 0 && | |
802 | hose->pci_mem_offset != cpu_addr - pci_addr) { | |
803 | printk(KERN_INFO | |
804 | " \\--> Skipped (offset mismatch) !\n"); | |
805 | continue; | |
806 | } | |
807 | ||
808 | /* Build resource */ | |
809 | res = &hose->mem_resources[memno++]; | |
810 | res->flags = IORESOURCE_MEM; | |
811 | if (pci_space & 0x40000000) | |
812 | res->flags |= IORESOURCE_PREFETCH; | |
813 | res->start = cpu_addr; | |
814 | break; | |
815 | } | |
816 | if (res != NULL) { | |
817 | res->name = dev->full_name; | |
818 | res->end = res->start + size - 1; | |
819 | res->parent = NULL; | |
820 | res->sibling = NULL; | |
821 | res->child = NULL; | |
822 | } | |
823 | } | |
824 | ||
8db13a0e BH |
825 | /* If there's an ISA hole and the pci_mem_offset is -not- matching |
826 | * the ISA hole offset, then we need to remove the ISA hole from | |
827 | * the resource list for that brige | |
828 | */ | |
829 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
830 | unsigned int next = isa_hole + 1; | |
831 | printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); | |
832 | if (next < memno) | |
833 | memmove(&hose->mem_resources[isa_hole], | |
834 | &hose->mem_resources[next], | |
835 | sizeof(struct resource) * (memno - next)); | |
836 | hose->mem_resources[--memno].flags = 0; | |
13dccb9e BH |
837 | } |
838 | } | |
fa462f2d BH |
839 | |
840 | /* Decide whether to display the domain number in /proc */ | |
841 | int pci_proc_domain(struct pci_bus *bus) | |
842 | { | |
843 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 844 | |
0e47ff1c | 845 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 846 | return 0; |
0e47ff1c | 847 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
848 | return hose->global_number != 0; |
849 | return 1; | |
fa462f2d BH |
850 | } |
851 | ||
fe2d338c BH |
852 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
853 | struct resource *res) | |
854 | { | |
855 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
856 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
857 | ||
858 | if (!hose) | |
859 | return; | |
860 | if (res->flags & IORESOURCE_IO) { | |
861 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
862 | mask = 0xffffffffu; | |
863 | } else if (res->flags & IORESOURCE_MEM) | |
864 | offset = hose->pci_mem_offset; | |
865 | ||
866 | region->start = (res->start - offset) & mask; | |
867 | region->end = (res->end - offset) & mask; | |
868 | } | |
869 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
870 | ||
871 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
872 | struct pci_bus_region *region) | |
873 | { | |
874 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
875 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
876 | ||
877 | if (!hose) | |
878 | return; | |
879 | if (res->flags & IORESOURCE_IO) { | |
880 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
881 | mask = 0xffffffffu; | |
882 | } else if (res->flags & IORESOURCE_MEM) | |
883 | offset = hose->pci_mem_offset; | |
884 | res->start = (region->start + offset) & mask; | |
885 | res->end = (region->end + offset) & mask; | |
886 | } | |
887 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
bf5e2ba2 BH |
888 | |
889 | /* Fixup a bus resource into a linux resource */ | |
890 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) | |
891 | { | |
892 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
893 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
894 | ||
895 | if (res->flags & IORESOURCE_IO) { | |
896 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
897 | mask = 0xffffffffu; | |
898 | } else if (res->flags & IORESOURCE_MEM) | |
899 | offset = hose->pci_mem_offset; | |
900 | ||
901 | res->start = (res->start + offset) & mask; | |
902 | res->end = (res->end + offset) & mask; | |
bf5e2ba2 BH |
903 | } |
904 | ||
905 | ||
906 | /* This header fixup will do the resource fixup for all devices as they are | |
907 | * probed, but not for bridge ranges | |
908 | */ | |
909 | static void __devinit pcibios_fixup_resources(struct pci_dev *dev) | |
910 | { | |
911 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
912 | int i; | |
913 | ||
914 | if (!hose) { | |
915 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
916 | pci_name(dev)); | |
917 | return; | |
918 | } | |
919 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
920 | struct resource *res = dev->resource + i; | |
921 | if (!res->flags) | |
922 | continue; | |
0e47ff1c | 923 | /* On platforms that have PCI_PROBE_ONLY set, we don't |
7f172890 BH |
924 | * consider 0 as an unassigned BAR value. It's technically |
925 | * a valid value, but linux doesn't like it... so when we can | |
926 | * re-assign things, we do so, but if we can't, we keep it | |
927 | * around and hope for the best... | |
928 | */ | |
0e47ff1c | 929 | if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) { |
bf5e2ba2 BH |
930 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", |
931 | pci_name(dev), i, | |
932 | (unsigned long long)res->start, | |
933 | (unsigned long long)res->end, | |
934 | (unsigned int)res->flags); | |
935 | res->end -= res->start; | |
936 | res->start = 0; | |
937 | res->flags |= IORESOURCE_UNSET; | |
938 | continue; | |
939 | } | |
940 | ||
941 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", | |
942 | pci_name(dev), i, | |
943 | (unsigned long long)res->start,\ | |
944 | (unsigned long long)res->end, | |
945 | (unsigned int)res->flags); | |
946 | ||
947 | fixup_resource(res, dev); | |
b5561511 BH |
948 | |
949 | pr_debug("PCI:%s %016llx-%016llx\n", | |
950 | pci_name(dev), | |
951 | (unsigned long long)res->start, | |
952 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
953 | } |
954 | ||
955 | /* Call machine specific resource fixup */ | |
956 | if (ppc_md.pcibios_fixup_resources) | |
957 | ppc_md.pcibios_fixup_resources(dev); | |
958 | } | |
959 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
960 | ||
b5561511 BH |
961 | /* This function tries to figure out if a bridge resource has been initialized |
962 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
963 | * things go more smoothly when it gets it right. It should covers cases such | |
964 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
965 | */ | |
966 | static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, | |
967 | struct resource *res) | |
bf5e2ba2 | 968 | { |
be8cbcd8 | 969 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 970 | struct pci_dev *dev = bus->self; |
b5561511 BH |
971 | resource_size_t offset; |
972 | u16 command; | |
973 | int i; | |
bf5e2ba2 | 974 | |
b5561511 | 975 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 976 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 977 | return 0; |
bf5e2ba2 | 978 | |
b5561511 BH |
979 | /* Job is a bit different between memory and IO */ |
980 | if (res->flags & IORESOURCE_MEM) { | |
981 | /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been | |
982 | * initialized by somebody | |
983 | */ | |
984 | if (res->start != hose->pci_mem_offset) | |
985 | return 0; | |
bf5e2ba2 | 986 | |
b5561511 BH |
987 | /* The BAR is 0, let's check if memory decoding is enabled on |
988 | * the bridge. If not, we consider it unassigned | |
989 | */ | |
990 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
991 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
992 | return 1; | |
be8cbcd8 | 993 | |
b5561511 BH |
994 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
995 | * resources covers that starting address (0 then it's good enough for | |
996 | * us for memory | |
997 | */ | |
998 | for (i = 0; i < 3; i++) { | |
999 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
1000 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | /* Well, it starts at 0 and we know it will collide so we may as | |
1005 | * well consider it as unassigned. That covers the Apple case. | |
1006 | */ | |
1007 | return 1; | |
1008 | } else { | |
1009 | /* If the BAR is non-0, then we consider it assigned */ | |
1010 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1011 | if (((res->start - offset) & 0xfffffffful) != 0) | |
1012 | return 0; | |
1013 | ||
1014 | /* Here, we are a bit different than memory as typically IO space | |
1015 | * starting at low addresses -is- valid. What we do instead if that | |
1016 | * we consider as unassigned anything that doesn't have IO enabled | |
1017 | * in the PCI command register, and that's it. | |
1018 | */ | |
1019 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1020 | if (command & PCI_COMMAND_IO) | |
1021 | return 0; | |
1022 | ||
1023 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
1024 | * it unassigned | |
1025 | */ | |
1026 | return 1; | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | /* Fixup resources of a PCI<->PCI bridge */ | |
1031 | static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) | |
1032 | { | |
1033 | struct resource *res; | |
1034 | int i; | |
1035 | ||
1036 | struct pci_dev *dev = bus->self; | |
1037 | ||
89a74ecc BH |
1038 | pci_bus_for_each_resource(bus, res, i) { |
1039 | if (!res || !res->flags) | |
b5561511 BH |
1040 | continue; |
1041 | if (i >= 3 && bus->self->transparent) | |
1042 | continue; | |
1043 | ||
1044 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
1045 | pci_name(dev), i, | |
1046 | (unsigned long long)res->start,\ | |
1047 | (unsigned long long)res->end, | |
1048 | (unsigned int)res->flags); | |
bf5e2ba2 | 1049 | |
b5561511 BH |
1050 | /* Perform fixup */ |
1051 | fixup_resource(res, dev); | |
1052 | ||
1053 | /* Try to detect uninitialized P2P bridge resources, | |
1054 | * and clear them out so they get re-assigned later | |
1055 | */ | |
1056 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
1057 | res->flags = 0; | |
1058 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
1059 | } else { | |
1060 | ||
1061 | pr_debug("PCI:%s %016llx-%016llx\n", | |
1062 | pci_name(dev), | |
1063 | (unsigned long long)res->start, | |
1064 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
1065 | } |
1066 | } | |
b5561511 BH |
1067 | } |
1068 | ||
8b8da358 BH |
1069 | void __devinit pcibios_setup_bus_self(struct pci_bus *bus) |
1070 | { | |
7eef440a | 1071 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
1072 | if (bus->self != NULL) |
1073 | pcibios_fixup_bridge(bus); | |
1074 | ||
1075 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 1076 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
1077 | */ |
1078 | if (ppc_md.pcibios_fixup_bus) | |
1079 | ppc_md.pcibios_fixup_bus(bus); | |
1080 | ||
1081 | /* Setup bus DMA mappings */ | |
1082 | if (ppc_md.pci_dma_bus_setup) | |
1083 | ppc_md.pci_dma_bus_setup(bus); | |
1084 | } | |
1085 | ||
7eef440a BH |
1086 | void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) |
1087 | { | |
1088 | struct pci_dev *dev; | |
1089 | ||
1090 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1091 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1092 | ||
1093 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1094 | /* Cardbus can call us to add new devices to a bus, so ignore |
1095 | * those who are already fully discovered | |
1096 | */ | |
1097 | if (dev->is_added) | |
1098 | continue; | |
1099 | ||
d706c1b0 | 1100 | /* Setup OF node pointer in the device */ |
d706c1b0 | 1101 | dev->dev.of_node = pci_device_to_OF_node(dev); |
7eef440a BH |
1102 | |
1103 | /* Fixup NUMA node as it may not be setup yet by the generic | |
1104 | * code and is needed by the DMA init | |
1105 | */ | |
1106 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
1107 | ||
1108 | /* Hook up default DMA ops */ | |
bc0df9ec | 1109 | set_dma_ops(&dev->dev, pci_dma_ops); |
738ef42e | 1110 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); |
7eef440a BH |
1111 | |
1112 | /* Additional platform DMA/iommu setup */ | |
1113 | if (ppc_md.pci_dma_dev_setup) | |
1114 | ppc_md.pci_dma_dev_setup(dev); | |
1115 | ||
1116 | /* Read default IRQs and fixup if necessary */ | |
1117 | pci_read_irq_line(dev); | |
1118 | if (ppc_md.pci_irq_fixup) | |
1119 | ppc_md.pci_irq_fixup(dev); | |
1120 | } | |
1121 | } | |
1122 | ||
bf5e2ba2 BH |
1123 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1124 | { | |
1125 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
7eef440a | 1126 | * bases. This is -not- called when generating the PCI tree from |
8b8da358 | 1127 | * the OF device-tree. |
bf5e2ba2 BH |
1128 | */ |
1129 | if (bus->self != NULL) | |
1130 | pci_read_bridge_bases(bus); | |
bf5e2ba2 | 1131 | |
8b8da358 BH |
1132 | /* Now fixup the bus bus */ |
1133 | pcibios_setup_bus_self(bus); | |
1134 | ||
1135 | /* Now fixup devices on that bus */ | |
1136 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1137 | } |
8b8da358 | 1138 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1139 | |
2d1c8618 BH |
1140 | void __devinit pci_fixup_cardbus(struct pci_bus *bus) |
1141 | { | |
1142 | /* Now fixup devices on that bus */ | |
1143 | pcibios_setup_bus_devices(bus); | |
1144 | } | |
1145 | ||
1146 | ||
3fd94c6b BH |
1147 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1148 | { | |
0e47ff1c | 1149 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1150 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1151 | return 1; | |
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* | |
1156 | * We need to avoid collisions with `mirrored' VGA ports | |
1157 | * and other strange ISA hardware, so we always want the | |
1158 | * addresses to be allocated in the 0x000-0x0ff region | |
1159 | * modulo 0x400. | |
1160 | * | |
1161 | * Why? Because some silly external IO cards only decode | |
1162 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1163 | * is reserved for motherboard devices that decode all 16 | |
1164 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1165 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1166 | * which might have be mirrored at 0x0100-0x03ff.. | |
1167 | */ | |
3b7a17fc | 1168 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1169 | resource_size_t size, resource_size_t align) |
1170 | { | |
1171 | struct pci_dev *dev = data; | |
b26b2d49 | 1172 | resource_size_t start = res->start; |
3fd94c6b BH |
1173 | |
1174 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1175 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1176 | return start; |
1177 | if (start & 0x300) | |
3fd94c6b | 1178 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1179 | } |
b26b2d49 DB |
1180 | |
1181 | return start; | |
3fd94c6b BH |
1182 | } |
1183 | EXPORT_SYMBOL(pcibios_align_resource); | |
1184 | ||
1185 | /* | |
1186 | * Reparent resource children of pr that conflict with res | |
1187 | * under res, and make res replace those children. | |
1188 | */ | |
0f6023d5 | 1189 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1190 | struct resource *res) |
1191 | { | |
1192 | struct resource *p, **pp; | |
1193 | struct resource **firstpp = NULL; | |
1194 | ||
1195 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1196 | if (p->end < res->start) | |
1197 | continue; | |
1198 | if (res->end < p->start) | |
1199 | break; | |
1200 | if (p->start < res->start || p->end > res->end) | |
1201 | return -1; /* not completely contained */ | |
1202 | if (firstpp == NULL) | |
1203 | firstpp = pp; | |
1204 | } | |
1205 | if (firstpp == NULL) | |
1206 | return -1; /* didn't find any conflicting entries? */ | |
1207 | res->parent = parent; | |
1208 | res->child = *firstpp; | |
1209 | res->sibling = *pp; | |
1210 | *firstpp = res; | |
1211 | *pp = NULL; | |
1212 | for (p = res->child; p != NULL; p = p->sibling) { | |
1213 | p->parent = res; | |
b0494bc8 BH |
1214 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
1215 | p->name, | |
1216 | (unsigned long long)p->start, | |
1217 | (unsigned long long)p->end, res->name); | |
3fd94c6b BH |
1218 | } |
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | /* | |
1223 | * Handle resources of PCI devices. If the world were perfect, we could | |
1224 | * just allocate all the resource regions and do nothing more. It isn't. | |
1225 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1226 | * require us to know lots of host bridge internals. So we attempt to | |
1227 | * keep as much of the original configuration as possible, but tweak it | |
1228 | * when it's found to be wrong. | |
1229 | * | |
1230 | * Known BIOS problems we have to work around: | |
1231 | * - I/O or memory regions not configured | |
1232 | * - regions configured, but not enabled in the command register | |
1233 | * - bogus I/O addresses above 64K used | |
1234 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1235 | * the fact the PCI specs explicitly allow address decoders to be | |
1236 | * shared between expansion ROMs and other resource regions, it's | |
1237 | * at least dangerous) | |
1238 | * | |
1239 | * Our solution: | |
1240 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1241 | * This gives us fixed barriers on where we can allocate. | |
1242 | * (2) Allocate resources for all enabled devices. If there is | |
1243 | * a collision, just mark the resource as unallocated. Also | |
1244 | * disable expansion ROMs during this step. | |
1245 | * (3) Try to allocate resources for disabled devices. If the | |
1246 | * resources were assigned correctly, everything goes well, | |
1247 | * if they weren't, they won't disturb allocation of other | |
1248 | * resources. | |
1249 | * (4) Assign new addresses to resources which were either | |
1250 | * not configured at all or misconfigured. If explicitly | |
1251 | * requested by the user, configure expansion ROM address | |
1252 | * as well. | |
1253 | */ | |
1254 | ||
e90a1318 | 1255 | void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1256 | { |
e90a1318 | 1257 | struct pci_bus *b; |
3fd94c6b BH |
1258 | int i; |
1259 | struct resource *res, *pr; | |
1260 | ||
b5ae5f91 BH |
1261 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1262 | pci_domain_nr(bus), bus->number); | |
1263 | ||
89a74ecc BH |
1264 | pci_bus_for_each_resource(bus, res, i) { |
1265 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 NF |
1266 | continue; |
1267 | if (bus->parent == NULL) | |
1268 | pr = (res->flags & IORESOURCE_IO) ? | |
1269 | &ioport_resource : &iomem_resource; | |
1270 | else { | |
1271 | /* Don't bother with non-root busses when | |
1272 | * re-assigning all resources. We clear the | |
1273 | * resource flags as if they were colliding | |
1274 | * and as such ensure proper re-allocation | |
1275 | * later. | |
1276 | */ | |
0e47ff1c | 1277 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) |
e90a1318 NF |
1278 | goto clear_resource; |
1279 | pr = pci_find_parent_resource(bus->self, res); | |
1280 | if (pr == res) { | |
1281 | /* this happens when the generic PCI | |
1282 | * code (wrongly) decides that this | |
1283 | * bridge is transparent -- paulus | |
3fd94c6b | 1284 | */ |
e90a1318 | 1285 | continue; |
3fd94c6b | 1286 | } |
e90a1318 | 1287 | } |
3fd94c6b | 1288 | |
b0494bc8 BH |
1289 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " |
1290 | "[0x%x], parent %p (%s)\n", | |
1291 | bus->self ? pci_name(bus->self) : "PHB", | |
1292 | bus->number, i, | |
1293 | (unsigned long long)res->start, | |
1294 | (unsigned long long)res->end, | |
1295 | (unsigned int)res->flags, | |
1296 | pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1297 | |
1298 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1299 | if (request_resource(pr, res) == 0) | |
1300 | continue; | |
1301 | /* | |
1302 | * Must be a conflict with an existing entry. | |
1303 | * Move that entry (or entries) under the | |
1304 | * bridge resource and try again. | |
1305 | */ | |
1306 | if (reparent_resources(pr, res) == 0) | |
1307 | continue; | |
3fd94c6b | 1308 | } |
e90a1318 NF |
1309 | printk(KERN_WARNING "PCI: Cannot allocate resource region " |
1310 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1311 | clear_resource: | |
837c4ef1 | 1312 | res->start = res->end = 0; |
e90a1318 | 1313 | res->flags = 0; |
3fd94c6b | 1314 | } |
e90a1318 NF |
1315 | |
1316 | list_for_each_entry(b, &bus->children, node) | |
1317 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1318 | } |
1319 | ||
533b1928 | 1320 | static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1321 | { |
1322 | struct resource *pr, *r = &dev->resource[idx]; | |
1323 | ||
b0494bc8 BH |
1324 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
1325 | pci_name(dev), idx, | |
1326 | (unsigned long long)r->start, | |
1327 | (unsigned long long)r->end, | |
1328 | (unsigned int)r->flags); | |
3fd94c6b BH |
1329 | |
1330 | pr = pci_find_parent_resource(dev, r); | |
1331 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1332 | request_resource(pr, r) < 0) { | |
1333 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1334 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1335 | if (pr) | |
b0494bc8 BH |
1336 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
1337 | pr, | |
1338 | (unsigned long long)pr->start, | |
1339 | (unsigned long long)pr->end, | |
1340 | (unsigned int)pr->flags); | |
3fd94c6b BH |
1341 | /* We'll assign a new address later */ |
1342 | r->flags |= IORESOURCE_UNSET; | |
1343 | r->end -= r->start; | |
1344 | r->start = 0; | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | static void __init pcibios_allocate_resources(int pass) | |
1349 | { | |
1350 | struct pci_dev *dev = NULL; | |
1351 | int idx, disabled; | |
1352 | u16 command; | |
1353 | struct resource *r; | |
1354 | ||
1355 | for_each_pci_dev(dev) { | |
1356 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1357 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1358 | r = &dev->resource[idx]; |
1359 | if (r->parent) /* Already allocated */ | |
1360 | continue; | |
1361 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1362 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1363 | /* We only allocate ROMs on pass 1 just in case they |
1364 | * have been screwed up by firmware | |
1365 | */ | |
1366 | if (idx == PCI_ROM_RESOURCE ) | |
1367 | disabled = 1; | |
3fd94c6b BH |
1368 | if (r->flags & IORESOURCE_IO) |
1369 | disabled = !(command & PCI_COMMAND_IO); | |
1370 | else | |
1371 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1372 | if (pass == disabled) |
1373 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1374 | } |
1375 | if (pass) | |
1376 | continue; | |
1377 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1378 | if (r->flags) { |
3fd94c6b BH |
1379 | /* Turn the ROM off, leave the resource region, |
1380 | * but keep it unregistered. | |
1381 | */ | |
1382 | u32 reg; | |
3fd94c6b | 1383 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1384 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1385 | pr_debug("PCI: Switching off ROM of %s\n", | |
1386 | pci_name(dev)); | |
1387 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1388 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1389 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1390 | } | |
3fd94c6b BH |
1391 | } |
1392 | } | |
1393 | } | |
1394 | ||
c1f34302 BH |
1395 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1396 | { | |
1397 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1398 | resource_size_t offset; | |
1399 | struct resource *res, *pres; | |
1400 | int i; | |
1401 | ||
1402 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1403 | ||
1404 | /* Check for IO */ | |
1405 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1406 | goto no_io; | |
1407 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1408 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1409 | BUG_ON(res == NULL); | |
1410 | res->name = "Legacy IO"; | |
1411 | res->flags = IORESOURCE_IO; | |
1412 | res->start = offset; | |
1413 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1414 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1415 | if (request_resource(&hose->io_resource, res)) { | |
1416 | printk(KERN_DEBUG | |
1417 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1418 | pci_domain_nr(bus), bus->number, res); | |
1419 | kfree(res); | |
1420 | } | |
1421 | ||
1422 | no_io: | |
1423 | /* Check for memory */ | |
1424 | offset = hose->pci_mem_offset; | |
1425 | pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); | |
1426 | for (i = 0; i < 3; i++) { | |
1427 | pres = &hose->mem_resources[i]; | |
1428 | if (!(pres->flags & IORESOURCE_MEM)) | |
1429 | continue; | |
1430 | pr_debug("hose mem res: %pR\n", pres); | |
1431 | if ((pres->start - offset) <= 0xa0000 && | |
1432 | (pres->end - offset) >= 0xbffff) | |
1433 | break; | |
1434 | } | |
1435 | if (i >= 3) | |
1436 | return; | |
1437 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1438 | BUG_ON(res == NULL); | |
1439 | res->name = "Legacy VGA memory"; | |
1440 | res->flags = IORESOURCE_MEM; | |
1441 | res->start = 0xa0000 + offset; | |
1442 | res->end = 0xbffff + offset; | |
1443 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1444 | if (request_resource(pres, res)) { | |
1445 | printk(KERN_DEBUG | |
1446 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1447 | pci_domain_nr(bus), bus->number, res); | |
1448 | kfree(res); | |
1449 | } | |
1450 | } | |
1451 | ||
3fd94c6b BH |
1452 | void __init pcibios_resource_survey(void) |
1453 | { | |
e90a1318 NF |
1454 | struct pci_bus *b; |
1455 | ||
3fd94c6b BH |
1456 | /* Allocate and assign resources. If we re-assign everything, then |
1457 | * we skip the allocate phase | |
1458 | */ | |
e90a1318 NF |
1459 | list_for_each_entry(b, &pci_root_buses, node) |
1460 | pcibios_allocate_bus_resources(b); | |
3fd94c6b | 1461 | |
0e47ff1c | 1462 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { |
3fd94c6b BH |
1463 | pcibios_allocate_resources(0); |
1464 | pcibios_allocate_resources(1); | |
1465 | } | |
1466 | ||
c1f34302 BH |
1467 | /* Before we start assigning unassigned resource, we try to reserve |
1468 | * the low IO area and the VGA memory area if they intersect the | |
1469 | * bus available resources to avoid allocating things on top of them | |
1470 | */ | |
0e47ff1c | 1471 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1472 | list_for_each_entry(b, &pci_root_buses, node) |
1473 | pcibios_reserve_legacy_regions(b); | |
1474 | } | |
1475 | ||
1476 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1477 | * we proceed to assigning things that were left unassigned | |
1478 | */ | |
0e47ff1c | 1479 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1480 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1481 | pci_assign_unassigned_resources(); |
1482 | } | |
1483 | ||
1484 | /* Call machine dependent fixup */ | |
1485 | if (ppc_md.pcibios_fixup) | |
1486 | ppc_md.pcibios_fixup(); | |
1487 | } | |
1488 | ||
1489 | #ifdef CONFIG_HOTPLUG | |
8b8da358 | 1490 | |
fd6852c8 | 1491 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1492 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1493 | * rest of the code later, for now, keep it as-is as our main |
1494 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1495 | */ |
baf75b0a | 1496 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1497 | { |
1498 | struct pci_dev *dev; | |
1499 | struct pci_bus *child_bus; | |
1500 | ||
1501 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1502 | int i; | |
1503 | ||
1504 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1505 | struct resource *r = &dev->resource[i]; | |
1506 | ||
1507 | if (r->parent || !r->start || !r->flags) | |
1508 | continue; | |
fd6852c8 BH |
1509 | |
1510 | pr_debug("PCI: Claiming %s: " | |
1511 | "Resource %d: %016llx..%016llx [%x]\n", | |
1512 | pci_name(dev), i, | |
1513 | (unsigned long long)r->start, | |
1514 | (unsigned long long)r->end, | |
1515 | (unsigned int)r->flags); | |
1516 | ||
3fd94c6b BH |
1517 | pci_claim_resource(dev, i); |
1518 | } | |
1519 | } | |
1520 | ||
1521 | list_for_each_entry(child_bus, &bus->children, node) | |
1522 | pcibios_claim_one_bus(child_bus); | |
1523 | } | |
fd6852c8 BH |
1524 | |
1525 | ||
1526 | /* pcibios_finish_adding_to_bus | |
1527 | * | |
1528 | * This is to be called by the hotplug code after devices have been | |
1529 | * added to a bus, this include calling it for a PHB that is just | |
1530 | * being added | |
1531 | */ | |
1532 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1533 | { | |
1534 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1535 | pci_domain_nr(bus), bus->number); | |
1536 | ||
1537 | /* Allocate bus and devices resources */ | |
1538 | pcibios_allocate_bus_resources(bus); | |
1539 | pcibios_claim_one_bus(bus); | |
1540 | ||
1541 | /* Add new devices to global lists. Register in proc, sysfs. */ | |
1542 | pci_bus_add_devices(bus); | |
1543 | ||
1544 | /* Fixup EEH */ | |
1545 | eeh_add_device_tree_late(bus); | |
1546 | } | |
1547 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1548 | ||
3fd94c6b | 1549 | #endif /* CONFIG_HOTPLUG */ |
549beb9b BH |
1550 | |
1551 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1552 | { | |
549beb9b BH |
1553 | if (ppc_md.pcibios_enable_device_hook) |
1554 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1555 | return -EINVAL; | |
1556 | ||
7cfb5f9a | 1557 | return pci_enable_resources(dev, mask); |
549beb9b | 1558 | } |
53280323 BH |
1559 | |
1560 | void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) | |
1561 | { | |
1562 | struct pci_bus *bus = hose->bus; | |
1563 | struct resource *res; | |
1564 | int i; | |
1565 | ||
1566 | /* Hookup PHB IO resource */ | |
1567 | bus->resource[0] = res = &hose->io_resource; | |
1568 | ||
1569 | if (!res->flags) { | |
1570 | printk(KERN_WARNING "PCI: I/O resource not set for host" | |
1571 | " bridge %s (domain %d)\n", | |
1572 | hose->dn->full_name, hose->global_number); | |
1573 | #ifdef CONFIG_PPC32 | |
1574 | /* Workaround for lack of IO resource only on 32-bit */ | |
1575 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1576 | res->end = res->start + IO_SPACE_LIMIT; | |
1577 | res->flags = IORESOURCE_IO; | |
1578 | #endif /* CONFIG_PPC32 */ | |
1579 | } | |
1580 | ||
1581 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1582 | (unsigned long long)res->start, | |
1583 | (unsigned long long)res->end, | |
1584 | (unsigned long)res->flags); | |
1585 | ||
1586 | /* Hookup PHB Memory resources */ | |
1587 | for (i = 0; i < 3; ++i) { | |
1588 | res = &hose->mem_resources[i]; | |
1589 | if (!res->flags) { | |
1590 | if (i > 0) | |
1591 | continue; | |
1592 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1593 | "host bridge %s (domain %d)\n", | |
1594 | hose->dn->full_name, hose->global_number); | |
1595 | #ifdef CONFIG_PPC32 | |
1596 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1597 | res->start = hose->pci_mem_offset; | |
1598 | res->end = (resource_size_t)-1LL; | |
1599 | res->flags = IORESOURCE_MEM; | |
1600 | #endif /* CONFIG_PPC32 */ | |
1601 | } | |
1602 | bus->resource[i+1] = res; | |
1603 | ||
1604 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, | |
1605 | (unsigned long long)res->start, | |
1606 | (unsigned long long)res->end, | |
1607 | (unsigned long)res->flags); | |
1608 | } | |
1609 | ||
1610 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1611 | (unsigned long long)hose->pci_mem_offset); | |
1612 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1613 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1614 | ||
1615 | } | |
89c2dd62 KG |
1616 | |
1617 | /* | |
1618 | * Null PCI config access functions, for the case when we can't | |
1619 | * find a hose. | |
1620 | */ | |
1621 | #define NULL_PCI_OP(rw, size, type) \ | |
1622 | static int \ | |
1623 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1624 | { \ | |
1625 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1626 | } | |
1627 | ||
1628 | static int | |
1629 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1630 | int len, u32 *val) | |
1631 | { | |
1632 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1633 | } | |
1634 | ||
1635 | static int | |
1636 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1637 | int len, u32 val) | |
1638 | { | |
1639 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1640 | } | |
1641 | ||
1642 | static struct pci_ops null_pci_ops = | |
1643 | { | |
1644 | .read = null_read_config, | |
1645 | .write = null_write_config, | |
1646 | }; | |
1647 | ||
1648 | /* | |
1649 | * These functions are used early on before PCI scanning is done | |
1650 | * and all of the pci_dev and pci_bus structures have been created. | |
1651 | */ | |
1652 | static struct pci_bus * | |
1653 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1654 | { | |
1655 | static struct pci_bus bus; | |
1656 | ||
1657 | if (hose == 0) { | |
1658 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | |
1659 | } | |
1660 | bus.number = busnr; | |
1661 | bus.sysdata = hose; | |
1662 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1663 | return &bus; | |
1664 | } | |
1665 | ||
1666 | #define EARLY_PCI_OP(rw, size, type) \ | |
1667 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1668 | int devfn, int offset, type value) \ | |
1669 | { \ | |
1670 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1671 | devfn, offset, value); \ | |
1672 | } | |
1673 | ||
1674 | EARLY_PCI_OP(read, byte, u8 *) | |
1675 | EARLY_PCI_OP(read, word, u16 *) | |
1676 | EARLY_PCI_OP(read, dword, u32 *) | |
1677 | EARLY_PCI_OP(write, byte, u8) | |
1678 | EARLY_PCI_OP(write, word, u16) | |
1679 | EARLY_PCI_OP(write, dword, u32) | |
1680 | ||
1681 | extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); | |
1682 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1683 | int cap) | |
1684 | { | |
1685 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1686 | } | |
0ed2c722 GL |
1687 | |
1688 | /** | |
1689 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1690 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1691 | */ |
b5d937de | 1692 | void __devinit pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 GL |
1693 | { |
1694 | struct pci_bus *bus; | |
1695 | struct device_node *node = hose->dn; | |
1696 | int mode; | |
1697 | ||
1698 | pr_debug("PCI: Scanning PHB %s\n", | |
1699 | node ? node->full_name : "<NO NAME>"); | |
1700 | ||
1701 | /* Create an empty bus for the toplevel */ | |
b5d937de | 1702 | bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose); |
0ed2c722 GL |
1703 | if (bus == NULL) { |
1704 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1705 | hose->global_number); | |
1706 | return; | |
1707 | } | |
b5d937de | 1708 | bus->dev.of_node = of_node_get(node); |
0ed2c722 GL |
1709 | bus->secondary = hose->first_busno; |
1710 | hose->bus = bus; | |
1711 | ||
1712 | /* Get some IO space for the new PHB */ | |
1713 | pcibios_setup_phb_io_space(hose); | |
1714 | ||
1715 | /* Wire up PHB bus resources */ | |
1716 | pcibios_setup_phb_resources(hose); | |
1717 | ||
1718 | /* Get probe mode and perform scan */ | |
1719 | mode = PCI_PROBE_NORMAL; | |
1720 | if (node && ppc_md.pci_probe_mode) | |
1721 | mode = ppc_md.pci_probe_mode(bus); | |
1722 | pr_debug(" probe mode: %d\n", mode); | |
1723 | if (mode == PCI_PROBE_DEVTREE) { | |
1724 | bus->subordinate = hose->last_busno; | |
1725 | of_scan_bus(node, bus); | |
1726 | } | |
1727 | ||
1728 | if (mode == PCI_PROBE_NORMAL) | |
1729 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
1730 | } |