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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
19 | #undef DEBUG | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/bootmem.h> | |
26 | #include <linux/mm.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/syscalls.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/vmalloc.h> | |
31 | ||
32 | #include <asm/processor.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/prom.h> | |
35 | #include <asm/pci-bridge.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <asm/machdep.h> | |
38 | #include <asm/ppc-pci.h> | |
39 | #include <asm/firmware.h> | |
8b8da358 | 40 | #include <asm/eeh.h> |
5516b540 | 41 | |
a4c9e328 KG |
42 | static DEFINE_SPINLOCK(hose_spinlock); |
43 | ||
44 | /* XXX kill that some day ... */ | |
ebfc00f7 | 45 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 46 | |
25e81f92 BH |
47 | /* ISA Memory physical address */ |
48 | resource_size_t isa_mem_base; | |
49 | ||
1fd0f525 BH |
50 | /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */ |
51 | unsigned int ppc_pci_flags = 0; | |
52 | ||
a4c9e328 | 53 | |
4fc665b8 BB |
54 | static struct dma_mapping_ops *pci_dma_ops; |
55 | ||
56 | void set_pci_dma_ops(struct dma_mapping_ops *dma_ops) | |
57 | { | |
58 | pci_dma_ops = dma_ops; | |
59 | } | |
60 | ||
61 | struct dma_mapping_ops *get_pci_dma_ops(void) | |
62 | { | |
63 | return pci_dma_ops; | |
64 | } | |
65 | EXPORT_SYMBOL(get_pci_dma_ops); | |
66 | ||
67 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
68 | { | |
69 | return dma_set_mask(&dev->dev, mask); | |
70 | } | |
71 | ||
72 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
73 | { | |
74 | int rc; | |
75 | ||
76 | rc = dma_set_mask(&dev->dev, mask); | |
77 | dev->dev.coherent_dma_mask = dev->dma_mask; | |
78 | ||
79 | return rc; | |
80 | } | |
81 | ||
e60516e3 | 82 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
83 | { |
84 | struct pci_controller *phb; | |
85 | ||
e60516e3 | 86 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
87 | if (phb == NULL) |
88 | return NULL; | |
e60516e3 SR |
89 | spin_lock(&hose_spinlock); |
90 | phb->global_number = global_phb_number++; | |
91 | list_add_tail(&phb->list_node, &hose_list); | |
92 | spin_unlock(&hose_spinlock); | |
44ef3390 | 93 | phb->dn = dev; |
a4c9e328 KG |
94 | phb->is_dynamic = mem_init_done; |
95 | #ifdef CONFIG_PPC64 | |
96 | if (dev) { | |
97 | int nid = of_node_to_nid(dev); | |
98 | ||
99 | if (nid < 0 || !node_online(nid)) | |
100 | nid = -1; | |
101 | ||
102 | PHB_SET_NODE(phb, nid); | |
103 | } | |
104 | #endif | |
105 | return phb; | |
106 | } | |
107 | ||
108 | void pcibios_free_controller(struct pci_controller *phb) | |
109 | { | |
110 | spin_lock(&hose_spinlock); | |
111 | list_del(&phb->list_node); | |
112 | spin_unlock(&hose_spinlock); | |
113 | ||
114 | if (phb->is_dynamic) | |
115 | kfree(phb); | |
116 | } | |
117 | ||
6dfbde20 BH |
118 | int pcibios_vaddr_is_ioport(void __iomem *address) |
119 | { | |
120 | int ret = 0; | |
121 | struct pci_controller *hose; | |
122 | unsigned long size; | |
123 | ||
124 | spin_lock(&hose_spinlock); | |
125 | list_for_each_entry(hose, &hose_list, list_node) { | |
126 | #ifdef CONFIG_PPC64 | |
127 | size = hose->pci_io_size; | |
128 | #else | |
129 | size = hose->io_resource.end - hose->io_resource.start + 1; | |
130 | #endif | |
131 | if (address >= hose->io_base_virt && | |
132 | address < (hose->io_base_virt + size)) { | |
133 | ret = 1; | |
134 | break; | |
135 | } | |
136 | } | |
137 | spin_unlock(&hose_spinlock); | |
138 | return ret; | |
139 | } | |
140 | ||
5516b540 KG |
141 | /* |
142 | * Return the domain number for this bus. | |
143 | */ | |
144 | int pci_domain_nr(struct pci_bus *bus) | |
145 | { | |
6207e816 | 146 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 147 | |
6207e816 | 148 | return hose->global_number; |
5516b540 | 149 | } |
5516b540 | 150 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad KG |
151 | |
152 | #ifdef CONFIG_PPC_OF | |
a4c9e328 KG |
153 | |
154 | /* This routine is meant to be used early during boot, when the | |
155 | * PCI bus numbers have not yet been assigned, and you need to | |
156 | * issue PCI config cycles to an OF device. | |
157 | * It could also be used to "fix" RTAS config cycles if you want | |
158 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
159 | * config cycles. | |
160 | */ | |
161 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
162 | { | |
163 | if (!have_of) | |
164 | return NULL; | |
165 | while(node) { | |
166 | struct pci_controller *hose, *tmp; | |
167 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 168 | if (hose->dn == node) |
a4c9e328 KG |
169 | return hose; |
170 | node = node->parent; | |
171 | } | |
172 | return NULL; | |
173 | } | |
174 | ||
58083dad KG |
175 | static ssize_t pci_show_devspec(struct device *dev, |
176 | struct device_attribute *attr, char *buf) | |
177 | { | |
178 | struct pci_dev *pdev; | |
179 | struct device_node *np; | |
180 | ||
181 | pdev = to_pci_dev (dev); | |
182 | np = pci_device_to_OF_node(pdev); | |
183 | if (np == NULL || np->full_name == NULL) | |
184 | return 0; | |
185 | return sprintf(buf, "%s", np->full_name); | |
186 | } | |
187 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
188 | #endif /* CONFIG_PPC_OF */ | |
189 | ||
190 | /* Add sysfs properties */ | |
4f3731da | 191 | int pcibios_add_platform_entries(struct pci_dev *pdev) |
58083dad KG |
192 | { |
193 | #ifdef CONFIG_PPC_OF | |
4f3731da TB |
194 | return device_create_file(&pdev->dev, &dev_attr_devspec); |
195 | #else | |
196 | return 0; | |
58083dad | 197 | #endif /* CONFIG_PPC_OF */ |
4f3731da | 198 | |
58083dad KG |
199 | } |
200 | ||
a2b7390a | 201 | char __devinit *pcibios_setup(char *str) |
58083dad KG |
202 | { |
203 | return str; | |
204 | } | |
205 | ||
206 | /* | |
207 | * Reads the interrupt pin to determine if interrupt is use by card. | |
208 | * If the interrupt is used, then gets the interrupt line from the | |
209 | * openfirmware and sets it in the pci_dev and pci_config line. | |
210 | */ | |
211 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
212 | { | |
213 | struct of_irq oirq; | |
214 | unsigned int virq; | |
215 | ||
50c9bc2f BH |
216 | /* The current device-tree that iSeries generates from the HV |
217 | * PCI informations doesn't contain proper interrupt routing, | |
218 | * and all the fallback would do is print out crap, so we | |
219 | * don't attempt to resolve the interrupts here at all, some | |
220 | * iSeries specific fixup does it. | |
221 | * | |
222 | * In the long run, we will hopefully fix the generated device-tree | |
223 | * instead. | |
224 | */ | |
225 | #ifdef CONFIG_PPC_ISERIES | |
226 | if (firmware_has_feature(FW_FEATURE_ISERIES)) | |
227 | return -1; | |
228 | #endif | |
229 | ||
b0494bc8 | 230 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
231 | |
232 | #ifdef DEBUG | |
233 | memset(&oirq, 0xff, sizeof(oirq)); | |
234 | #endif | |
235 | /* Try to get a mapping from the device-tree */ | |
236 | if (of_irq_map_pci(pci_dev, &oirq)) { | |
237 | u8 line, pin; | |
238 | ||
239 | /* If that fails, lets fallback to what is in the config | |
240 | * space and map that through the default controller. We | |
241 | * also set the type to level low since that's what PCI | |
242 | * interrupts are. If your platform does differently, then | |
243 | * either provide a proper interrupt tree or don't use this | |
244 | * function. | |
245 | */ | |
246 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
247 | return -1; | |
248 | if (pin == 0) | |
249 | return -1; | |
250 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 251 | line == 0xff || line == 0) { |
58083dad KG |
252 | return -1; |
253 | } | |
b0494bc8 BH |
254 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
255 | line, pin); | |
58083dad KG |
256 | |
257 | virq = irq_create_mapping(NULL, line); | |
258 | if (virq != NO_IRQ) | |
259 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | |
260 | } else { | |
b0494bc8 BH |
261 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
262 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
58083dad KG |
263 | oirq.controller->full_name); |
264 | ||
265 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
266 | oirq.size); | |
267 | } | |
268 | if(virq == NO_IRQ) { | |
b0494bc8 | 269 | pr_debug(" Failed to map !\n"); |
58083dad KG |
270 | return -1; |
271 | } | |
272 | ||
b0494bc8 | 273 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
274 | |
275 | pci_dev->irq = virq; | |
276 | ||
277 | return 0; | |
278 | } | |
279 | EXPORT_SYMBOL(pci_read_irq_line); | |
280 | ||
281 | /* | |
282 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
283 | * modelled on the sparc64 implementation by Dave Miller. | |
284 | * -- paulus. | |
285 | */ | |
286 | ||
287 | /* | |
288 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
289 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
290 | * | |
291 | * Basically, the user finds the base address for his device which he wishes | |
292 | * to mmap. They read the 32-bit value from the config space base register, | |
293 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
294 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
295 | * | |
296 | * Returns negative error code on failure, zero on success. | |
297 | */ | |
298 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
299 | resource_size_t *offset, | |
300 | enum pci_mmap_state mmap_state) | |
301 | { | |
302 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
303 | unsigned long io_offset = 0; | |
304 | int i, res_bit; | |
305 | ||
306 | if (hose == 0) | |
307 | return NULL; /* should never happen */ | |
308 | ||
309 | /* If memory, add on the PCI bridge address offset */ | |
310 | if (mmap_state == pci_mmap_mem) { | |
311 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
312 | *offset += hose->pci_mem_offset; | |
313 | #endif | |
314 | res_bit = IORESOURCE_MEM; | |
315 | } else { | |
316 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
317 | *offset += io_offset; | |
318 | res_bit = IORESOURCE_IO; | |
319 | } | |
320 | ||
321 | /* | |
322 | * Check that the offset requested corresponds to one of the | |
323 | * resources of the device. | |
324 | */ | |
325 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
326 | struct resource *rp = &dev->resource[i]; | |
327 | int flags = rp->flags; | |
328 | ||
329 | /* treat ROM as memory (should be already) */ | |
330 | if (i == PCI_ROM_RESOURCE) | |
331 | flags |= IORESOURCE_MEM; | |
332 | ||
333 | /* Active and same type? */ | |
334 | if ((flags & res_bit) == 0) | |
335 | continue; | |
336 | ||
337 | /* In the range of this resource? */ | |
338 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
339 | continue; | |
340 | ||
341 | /* found it! construct the final physical address */ | |
342 | if (mmap_state == pci_mmap_io) | |
343 | *offset += hose->io_base_phys - io_offset; | |
344 | return rp; | |
345 | } | |
346 | ||
347 | return NULL; | |
348 | } | |
349 | ||
350 | /* | |
351 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
352 | * device mapping. | |
353 | */ | |
354 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
355 | pgprot_t protection, | |
356 | enum pci_mmap_state mmap_state, | |
357 | int write_combine) | |
358 | { | |
359 | unsigned long prot = pgprot_val(protection); | |
360 | ||
361 | /* Write combine is always 0 on non-memory space mappings. On | |
362 | * memory space, if the user didn't pass 1, we check for a | |
363 | * "prefetchable" resource. This is a bit hackish, but we use | |
364 | * this to workaround the inability of /sysfs to provide a write | |
365 | * combine bit | |
366 | */ | |
367 | if (mmap_state != pci_mmap_mem) | |
368 | write_combine = 0; | |
369 | else if (write_combine == 0) { | |
370 | if (rp->flags & IORESOURCE_PREFETCH) | |
371 | write_combine = 1; | |
372 | } | |
373 | ||
374 | /* XXX would be nice to have a way to ask for write-through */ | |
375 | prot |= _PAGE_NO_CACHE; | |
376 | if (write_combine) | |
377 | prot &= ~_PAGE_GUARDED; | |
378 | else | |
379 | prot |= _PAGE_GUARDED; | |
380 | ||
381 | return __pgprot(prot); | |
382 | } | |
383 | ||
384 | /* | |
385 | * This one is used by /dev/mem and fbdev who have no clue about the | |
386 | * PCI device, it tries to find the PCI device first and calls the | |
387 | * above routine | |
388 | */ | |
389 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
390 | unsigned long pfn, | |
391 | unsigned long size, | |
392 | pgprot_t protection) | |
393 | { | |
394 | struct pci_dev *pdev = NULL; | |
395 | struct resource *found = NULL; | |
396 | unsigned long prot = pgprot_val(protection); | |
7c12d906 | 397 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
398 | int i; |
399 | ||
400 | if (page_is_ram(pfn)) | |
401 | return __pgprot(prot); | |
402 | ||
403 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
404 | ||
405 | for_each_pci_dev(pdev) { | |
406 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
407 | struct resource *rp = &pdev->resource[i]; | |
408 | int flags = rp->flags; | |
409 | ||
410 | /* Active and same type? */ | |
411 | if ((flags & IORESOURCE_MEM) == 0) | |
412 | continue; | |
413 | /* In the range of this resource? */ | |
414 | if (offset < (rp->start & PAGE_MASK) || | |
415 | offset > rp->end) | |
416 | continue; | |
417 | found = rp; | |
418 | break; | |
419 | } | |
420 | if (found) | |
421 | break; | |
422 | } | |
423 | if (found) { | |
424 | if (found->flags & IORESOURCE_PREFETCH) | |
425 | prot &= ~_PAGE_GUARDED; | |
426 | pci_dev_put(pdev); | |
427 | } | |
428 | ||
b0494bc8 BH |
429 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
430 | (unsigned long long)offset, prot); | |
58083dad KG |
431 | |
432 | return __pgprot(prot); | |
433 | } | |
434 | ||
435 | ||
436 | /* | |
437 | * Perform the actual remap of the pages for a PCI device mapping, as | |
438 | * appropriate for this architecture. The region in the process to map | |
439 | * is described by vm_start and vm_end members of VMA, the base physical | |
440 | * address is found in vm_pgoff. | |
441 | * The pci device structure is provided so that architectures may make mapping | |
442 | * decisions on a per-device or per-bus basis. | |
443 | * | |
444 | * Returns a negative error code on failure, zero on success. | |
445 | */ | |
446 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
447 | enum pci_mmap_state mmap_state, int write_combine) | |
448 | { | |
7c12d906 BH |
449 | resource_size_t offset = |
450 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
451 | struct resource *rp; |
452 | int ret; | |
453 | ||
454 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
455 | if (rp == NULL) | |
456 | return -EINVAL; | |
457 | ||
458 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
459 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
460 | vma->vm_page_prot, | |
461 | mmap_state, write_combine); | |
462 | ||
463 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
464 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
465 | ||
466 | return ret; | |
467 | } | |
468 | ||
e9f82cb7 BH |
469 | /* This provides legacy IO read access on a bus */ |
470 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
471 | { | |
472 | unsigned long offset; | |
473 | struct pci_controller *hose = pci_bus_to_host(bus); | |
474 | struct resource *rp = &hose->io_resource; | |
475 | void __iomem *addr; | |
476 | ||
477 | /* Check if port can be supported by that bus. We only check | |
478 | * the ranges of the PHB though, not the bus itself as the rules | |
479 | * for forwarding legacy cycles down bridges are not our problem | |
480 | * here. So if the host bridge supports it, we do it. | |
481 | */ | |
482 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
483 | offset += port; | |
484 | ||
485 | if (!(rp->flags & IORESOURCE_IO)) | |
486 | return -ENXIO; | |
487 | if (offset < rp->start || (offset + size) > rp->end) | |
488 | return -ENXIO; | |
489 | addr = hose->io_base_virt + port; | |
490 | ||
491 | switch(size) { | |
492 | case 1: | |
493 | *((u8 *)val) = in_8(addr); | |
494 | return 1; | |
495 | case 2: | |
496 | if (port & 1) | |
497 | return -EINVAL; | |
498 | *((u16 *)val) = in_le16(addr); | |
499 | return 2; | |
500 | case 4: | |
501 | if (port & 3) | |
502 | return -EINVAL; | |
503 | *((u32 *)val) = in_le32(addr); | |
504 | return 4; | |
505 | } | |
506 | return -EINVAL; | |
507 | } | |
508 | ||
509 | /* This provides legacy IO write access on a bus */ | |
510 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
511 | { | |
512 | unsigned long offset; | |
513 | struct pci_controller *hose = pci_bus_to_host(bus); | |
514 | struct resource *rp = &hose->io_resource; | |
515 | void __iomem *addr; | |
516 | ||
517 | /* Check if port can be supported by that bus. We only check | |
518 | * the ranges of the PHB though, not the bus itself as the rules | |
519 | * for forwarding legacy cycles down bridges are not our problem | |
520 | * here. So if the host bridge supports it, we do it. | |
521 | */ | |
522 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
523 | offset += port; | |
524 | ||
525 | if (!(rp->flags & IORESOURCE_IO)) | |
526 | return -ENXIO; | |
527 | if (offset < rp->start || (offset + size) > rp->end) | |
528 | return -ENXIO; | |
529 | addr = hose->io_base_virt + port; | |
530 | ||
531 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
532 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
533 | * as a u32, which means that we have to correct the location of | |
534 | * the data read within those 32 bits for size 1 and 2 | |
535 | */ | |
536 | switch(size) { | |
537 | case 1: | |
538 | out_8(addr, val >> 24); | |
539 | return 1; | |
540 | case 2: | |
541 | if (port & 1) | |
542 | return -EINVAL; | |
543 | out_le16(addr, val >> 16); | |
544 | return 2; | |
545 | case 4: | |
546 | if (port & 3) | |
547 | return -EINVAL; | |
548 | out_le32(addr, val); | |
549 | return 4; | |
550 | } | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | /* This provides legacy IO or memory mmap access on a bus */ | |
555 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
556 | struct vm_area_struct *vma, | |
557 | enum pci_mmap_state mmap_state) | |
558 | { | |
559 | struct pci_controller *hose = pci_bus_to_host(bus); | |
560 | resource_size_t offset = | |
561 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
562 | resource_size_t size = vma->vm_end - vma->vm_start; | |
563 | struct resource *rp; | |
564 | ||
565 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
566 | pci_domain_nr(bus), bus->number, | |
567 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
568 | (unsigned long long)offset, | |
569 | (unsigned long long)(offset + size - 1)); | |
570 | ||
571 | if (mmap_state == pci_mmap_mem) { | |
572 | if ((offset + size) > hose->isa_mem_size) | |
573 | return -ENXIO; | |
574 | offset += hose->isa_mem_phys; | |
575 | } else { | |
576 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
577 | unsigned long roffset = offset + io_offset; | |
578 | rp = &hose->io_resource; | |
579 | if (!(rp->flags & IORESOURCE_IO)) | |
580 | return -ENXIO; | |
581 | if (roffset < rp->start || (roffset + size) > rp->end) | |
582 | return -ENXIO; | |
583 | offset += hose->io_base_phys; | |
584 | } | |
585 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
586 | ||
587 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
201bdc86 DG |
588 | vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) |
589 | | _PAGE_NO_CACHE | _PAGE_GUARDED); | |
e9f82cb7 BH |
590 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
591 | vma->vm_end - vma->vm_start, | |
592 | vma->vm_page_prot); | |
593 | } | |
594 | ||
58083dad KG |
595 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
596 | const struct resource *rsrc, | |
597 | resource_size_t *start, resource_size_t *end) | |
598 | { | |
599 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
600 | resource_size_t offset = 0; | |
601 | ||
602 | if (hose == NULL) | |
603 | return; | |
604 | ||
605 | if (rsrc->flags & IORESOURCE_IO) | |
606 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
607 | ||
608 | /* We pass a fully fixed up address to userland for MMIO instead of | |
609 | * a BAR value because X is lame and expects to be able to use that | |
610 | * to pass to /dev/mem ! | |
611 | * | |
612 | * That means that we'll have potentially 64 bits values where some | |
613 | * userland apps only expect 32 (like X itself since it thinks only | |
614 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
615 | * 32 bits CHRPs :-( | |
616 | * | |
617 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
618 | * has been fixed (and the fix spread enough), we can re-enable the | |
619 | * 2 lines below and pass down a BAR value to userland. In that case | |
620 | * we'll also have to re-enable the matching code in | |
621 | * __pci_mmap_make_offset(). | |
622 | * | |
623 | * BenH. | |
624 | */ | |
625 | #if 0 | |
626 | else if (rsrc->flags & IORESOURCE_MEM) | |
627 | offset = hose->pci_mem_offset; | |
628 | #endif | |
629 | ||
630 | *start = rsrc->start - offset; | |
631 | *end = rsrc->end - offset; | |
632 | } | |
13dccb9e BH |
633 | |
634 | /** | |
635 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
636 | * @hose: newly allocated pci_controller to be setup | |
637 | * @dev: device node of the host bridge | |
638 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
639 | * | |
640 | * This function will parse the "ranges" property of a PCI host bridge device | |
641 | * node and setup the resource mapping of a pci controller based on its | |
642 | * content. | |
643 | * | |
644 | * Life would be boring if it wasn't for a few issues that we have to deal | |
645 | * with here: | |
646 | * | |
647 | * - We can only cope with one IO space range and up to 3 Memory space | |
648 | * ranges. However, some machines (thanks Apple !) tend to split their | |
649 | * space into lots of small contiguous ranges. So we have to coalesce. | |
650 | * | |
651 | * - We can only cope with all memory ranges having the same offset | |
652 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
653 | * are setup for a large 1:1 mapping along with a small "window" which | |
654 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
655 | * order to give access to the ISA memory hole. | |
656 | * The way out of here that I've chosen for now is to always set the | |
657 | * offset based on the first resource found, then override it if we | |
658 | * have a different offset and the previous was set by an ISA hole. | |
659 | * | |
660 | * - Some busses have IO space not starting at 0, which causes trouble with | |
661 | * the way we do our IO resource renumbering. The code somewhat deals with | |
662 | * it for 64 bits but I would expect problems on 32 bits. | |
663 | * | |
664 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
665 | * 32 bits so we need to use 64 bits values for the parsing | |
666 | */ | |
667 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
668 | struct device_node *dev, | |
669 | int primary) | |
670 | { | |
671 | const u32 *ranges; | |
672 | int rlen; | |
673 | int pna = of_n_addr_cells(dev); | |
674 | int np = pna + 5; | |
675 | int memno = 0, isa_hole = -1; | |
676 | u32 pci_space; | |
677 | unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; | |
678 | unsigned long long isa_mb = 0; | |
679 | struct resource *res; | |
680 | ||
681 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
682 | dev->full_name, primary ? "(primary)" : ""); | |
683 | ||
684 | /* Get ranges property */ | |
685 | ranges = of_get_property(dev, "ranges", &rlen); | |
686 | if (ranges == NULL) | |
687 | return; | |
688 | ||
689 | /* Parse it */ | |
690 | while ((rlen -= np * 4) >= 0) { | |
691 | /* Read next ranges element */ | |
692 | pci_space = ranges[0]; | |
693 | pci_addr = of_read_number(ranges + 1, 2); | |
694 | cpu_addr = of_translate_address(dev, ranges + 3); | |
695 | size = of_read_number(ranges + pna + 3, 2); | |
696 | ranges += np; | |
e9f82cb7 BH |
697 | |
698 | /* If we failed translation or got a zero-sized region | |
699 | * (some FW try to feed us with non sensical zero sized regions | |
700 | * such as power3 which look like some kind of attempt at exposing | |
701 | * the VGA memory hole) | |
702 | */ | |
13dccb9e BH |
703 | if (cpu_addr == OF_BAD_ADDR || size == 0) |
704 | continue; | |
705 | ||
706 | /* Now consume following elements while they are contiguous */ | |
707 | for (; rlen >= np * sizeof(u32); | |
708 | ranges += np, rlen -= np * 4) { | |
709 | if (ranges[0] != pci_space) | |
710 | break; | |
711 | pci_next = of_read_number(ranges + 1, 2); | |
712 | cpu_next = of_translate_address(dev, ranges + 3); | |
713 | if (pci_next != pci_addr + size || | |
714 | cpu_next != cpu_addr + size) | |
715 | break; | |
716 | size += of_read_number(ranges + pna + 3, 2); | |
717 | } | |
718 | ||
719 | /* Act based on address space type */ | |
720 | res = NULL; | |
721 | switch ((pci_space >> 24) & 0x3) { | |
722 | case 1: /* PCI IO space */ | |
723 | printk(KERN_INFO | |
724 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
725 | cpu_addr, cpu_addr + size - 1, pci_addr); | |
726 | ||
727 | /* We support only one IO range */ | |
728 | if (hose->pci_io_size) { | |
729 | printk(KERN_INFO | |
730 | " \\--> Skipped (too many) !\n"); | |
731 | continue; | |
732 | } | |
733 | #ifdef CONFIG_PPC32 | |
734 | /* On 32 bits, limit I/O space to 16MB */ | |
735 | if (size > 0x01000000) | |
736 | size = 0x01000000; | |
737 | ||
738 | /* 32 bits needs to map IOs here */ | |
739 | hose->io_base_virt = ioremap(cpu_addr, size); | |
740 | ||
741 | /* Expect trouble if pci_addr is not 0 */ | |
742 | if (primary) | |
743 | isa_io_base = | |
744 | (unsigned long)hose->io_base_virt; | |
745 | #endif /* CONFIG_PPC32 */ | |
746 | /* pci_io_size and io_base_phys always represent IO | |
747 | * space starting at 0 so we factor in pci_addr | |
748 | */ | |
749 | hose->pci_io_size = pci_addr + size; | |
750 | hose->io_base_phys = cpu_addr - pci_addr; | |
751 | ||
752 | /* Build resource */ | |
753 | res = &hose->io_resource; | |
754 | res->flags = IORESOURCE_IO; | |
755 | res->start = pci_addr; | |
756 | break; | |
757 | case 2: /* PCI Memory space */ | |
67260ac9 | 758 | case 3: /* PCI 64 bits Memory space */ |
13dccb9e BH |
759 | printk(KERN_INFO |
760 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
761 | cpu_addr, cpu_addr + size - 1, pci_addr, | |
762 | (pci_space & 0x40000000) ? "Prefetch" : ""); | |
763 | ||
764 | /* We support only 3 memory ranges */ | |
765 | if (memno >= 3) { | |
766 | printk(KERN_INFO | |
767 | " \\--> Skipped (too many) !\n"); | |
768 | continue; | |
769 | } | |
770 | /* Handles ISA memory hole space here */ | |
771 | if (pci_addr == 0) { | |
772 | isa_mb = cpu_addr; | |
773 | isa_hole = memno; | |
774 | if (primary || isa_mem_base == 0) | |
775 | isa_mem_base = cpu_addr; | |
e9f82cb7 BH |
776 | hose->isa_mem_phys = cpu_addr; |
777 | hose->isa_mem_size = size; | |
13dccb9e BH |
778 | } |
779 | ||
780 | /* We get the PCI/Mem offset from the first range or | |
781 | * the, current one if the offset came from an ISA | |
782 | * hole. If they don't match, bugger. | |
783 | */ | |
784 | if (memno == 0 || | |
785 | (isa_hole >= 0 && pci_addr != 0 && | |
786 | hose->pci_mem_offset == isa_mb)) | |
787 | hose->pci_mem_offset = cpu_addr - pci_addr; | |
788 | else if (pci_addr != 0 && | |
789 | hose->pci_mem_offset != cpu_addr - pci_addr) { | |
790 | printk(KERN_INFO | |
791 | " \\--> Skipped (offset mismatch) !\n"); | |
792 | continue; | |
793 | } | |
794 | ||
795 | /* Build resource */ | |
796 | res = &hose->mem_resources[memno++]; | |
797 | res->flags = IORESOURCE_MEM; | |
798 | if (pci_space & 0x40000000) | |
799 | res->flags |= IORESOURCE_PREFETCH; | |
800 | res->start = cpu_addr; | |
801 | break; | |
802 | } | |
803 | if (res != NULL) { | |
804 | res->name = dev->full_name; | |
805 | res->end = res->start + size - 1; | |
806 | res->parent = NULL; | |
807 | res->sibling = NULL; | |
808 | res->child = NULL; | |
809 | } | |
810 | } | |
811 | ||
8db13a0e BH |
812 | /* If there's an ISA hole and the pci_mem_offset is -not- matching |
813 | * the ISA hole offset, then we need to remove the ISA hole from | |
814 | * the resource list for that brige | |
815 | */ | |
816 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
817 | unsigned int next = isa_hole + 1; | |
818 | printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); | |
819 | if (next < memno) | |
820 | memmove(&hose->mem_resources[isa_hole], | |
821 | &hose->mem_resources[next], | |
822 | sizeof(struct resource) * (memno - next)); | |
823 | hose->mem_resources[--memno].flags = 0; | |
13dccb9e BH |
824 | } |
825 | } | |
fa462f2d BH |
826 | |
827 | /* Decide whether to display the domain number in /proc */ | |
828 | int pci_proc_domain(struct pci_bus *bus) | |
829 | { | |
830 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 831 | |
fa462f2d BH |
832 | if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) |
833 | return 0; | |
834 | if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) | |
835 | return hose->global_number != 0; | |
836 | return 1; | |
fa462f2d BH |
837 | } |
838 | ||
fe2d338c BH |
839 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
840 | struct resource *res) | |
841 | { | |
842 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
843 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
844 | ||
845 | if (!hose) | |
846 | return; | |
847 | if (res->flags & IORESOURCE_IO) { | |
848 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
849 | mask = 0xffffffffu; | |
850 | } else if (res->flags & IORESOURCE_MEM) | |
851 | offset = hose->pci_mem_offset; | |
852 | ||
853 | region->start = (res->start - offset) & mask; | |
854 | region->end = (res->end - offset) & mask; | |
855 | } | |
856 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
857 | ||
858 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
859 | struct pci_bus_region *region) | |
860 | { | |
861 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
862 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
863 | ||
864 | if (!hose) | |
865 | return; | |
866 | if (res->flags & IORESOURCE_IO) { | |
867 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
868 | mask = 0xffffffffu; | |
869 | } else if (res->flags & IORESOURCE_MEM) | |
870 | offset = hose->pci_mem_offset; | |
871 | res->start = (region->start + offset) & mask; | |
872 | res->end = (region->end + offset) & mask; | |
873 | } | |
874 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
bf5e2ba2 BH |
875 | |
876 | /* Fixup a bus resource into a linux resource */ | |
877 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) | |
878 | { | |
879 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
880 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
881 | ||
882 | if (res->flags & IORESOURCE_IO) { | |
883 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
884 | mask = 0xffffffffu; | |
885 | } else if (res->flags & IORESOURCE_MEM) | |
886 | offset = hose->pci_mem_offset; | |
887 | ||
888 | res->start = (res->start + offset) & mask; | |
889 | res->end = (res->end + offset) & mask; | |
bf5e2ba2 BH |
890 | } |
891 | ||
892 | ||
893 | /* This header fixup will do the resource fixup for all devices as they are | |
894 | * probed, but not for bridge ranges | |
895 | */ | |
896 | static void __devinit pcibios_fixup_resources(struct pci_dev *dev) | |
897 | { | |
898 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
899 | int i; | |
900 | ||
901 | if (!hose) { | |
902 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
903 | pci_name(dev)); | |
904 | return; | |
905 | } | |
906 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
907 | struct resource *res = dev->resource + i; | |
908 | if (!res->flags) | |
909 | continue; | |
7f172890 BH |
910 | /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't |
911 | * consider 0 as an unassigned BAR value. It's technically | |
912 | * a valid value, but linux doesn't like it... so when we can | |
913 | * re-assign things, we do so, but if we can't, we keep it | |
914 | * around and hope for the best... | |
915 | */ | |
916 | if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
bf5e2ba2 BH |
917 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", |
918 | pci_name(dev), i, | |
919 | (unsigned long long)res->start, | |
920 | (unsigned long long)res->end, | |
921 | (unsigned int)res->flags); | |
922 | res->end -= res->start; | |
923 | res->start = 0; | |
924 | res->flags |= IORESOURCE_UNSET; | |
925 | continue; | |
926 | } | |
927 | ||
928 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", | |
929 | pci_name(dev), i, | |
930 | (unsigned long long)res->start,\ | |
931 | (unsigned long long)res->end, | |
932 | (unsigned int)res->flags); | |
933 | ||
934 | fixup_resource(res, dev); | |
b5561511 BH |
935 | |
936 | pr_debug("PCI:%s %016llx-%016llx\n", | |
937 | pci_name(dev), | |
938 | (unsigned long long)res->start, | |
939 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
940 | } |
941 | ||
942 | /* Call machine specific resource fixup */ | |
943 | if (ppc_md.pcibios_fixup_resources) | |
944 | ppc_md.pcibios_fixup_resources(dev); | |
945 | } | |
946 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
947 | ||
b5561511 BH |
948 | /* This function tries to figure out if a bridge resource has been initialized |
949 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
950 | * things go more smoothly when it gets it right. It should covers cases such | |
951 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
952 | */ | |
953 | static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, | |
954 | struct resource *res) | |
bf5e2ba2 | 955 | { |
be8cbcd8 | 956 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 957 | struct pci_dev *dev = bus->self; |
b5561511 BH |
958 | resource_size_t offset; |
959 | u16 command; | |
960 | int i; | |
bf5e2ba2 | 961 | |
b5561511 BH |
962 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
963 | if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) | |
964 | return 0; | |
bf5e2ba2 | 965 | |
b5561511 BH |
966 | /* Job is a bit different between memory and IO */ |
967 | if (res->flags & IORESOURCE_MEM) { | |
968 | /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been | |
969 | * initialized by somebody | |
970 | */ | |
971 | if (res->start != hose->pci_mem_offset) | |
972 | return 0; | |
bf5e2ba2 | 973 | |
b5561511 BH |
974 | /* The BAR is 0, let's check if memory decoding is enabled on |
975 | * the bridge. If not, we consider it unassigned | |
976 | */ | |
977 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
978 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
979 | return 1; | |
be8cbcd8 | 980 | |
b5561511 BH |
981 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
982 | * resources covers that starting address (0 then it's good enough for | |
983 | * us for memory | |
984 | */ | |
985 | for (i = 0; i < 3; i++) { | |
986 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
987 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
988 | return 0; | |
989 | } | |
990 | ||
991 | /* Well, it starts at 0 and we know it will collide so we may as | |
992 | * well consider it as unassigned. That covers the Apple case. | |
993 | */ | |
994 | return 1; | |
995 | } else { | |
996 | /* If the BAR is non-0, then we consider it assigned */ | |
997 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
998 | if (((res->start - offset) & 0xfffffffful) != 0) | |
999 | return 0; | |
1000 | ||
1001 | /* Here, we are a bit different than memory as typically IO space | |
1002 | * starting at low addresses -is- valid. What we do instead if that | |
1003 | * we consider as unassigned anything that doesn't have IO enabled | |
1004 | * in the PCI command register, and that's it. | |
1005 | */ | |
1006 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1007 | if (command & PCI_COMMAND_IO) | |
1008 | return 0; | |
1009 | ||
1010 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
1011 | * it unassigned | |
1012 | */ | |
1013 | return 1; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | /* Fixup resources of a PCI<->PCI bridge */ | |
1018 | static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) | |
1019 | { | |
1020 | struct resource *res; | |
1021 | int i; | |
1022 | ||
1023 | struct pci_dev *dev = bus->self; | |
1024 | ||
1025 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { | |
1026 | if ((res = bus->resource[i]) == NULL) | |
1027 | continue; | |
1028 | if (!res->flags) | |
1029 | continue; | |
1030 | if (i >= 3 && bus->self->transparent) | |
1031 | continue; | |
1032 | ||
1033 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
1034 | pci_name(dev), i, | |
1035 | (unsigned long long)res->start,\ | |
1036 | (unsigned long long)res->end, | |
1037 | (unsigned int)res->flags); | |
bf5e2ba2 | 1038 | |
b5561511 BH |
1039 | /* Perform fixup */ |
1040 | fixup_resource(res, dev); | |
1041 | ||
1042 | /* Try to detect uninitialized P2P bridge resources, | |
1043 | * and clear them out so they get re-assigned later | |
1044 | */ | |
1045 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
1046 | res->flags = 0; | |
1047 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
1048 | } else { | |
1049 | ||
1050 | pr_debug("PCI:%s %016llx-%016llx\n", | |
1051 | pci_name(dev), | |
1052 | (unsigned long long)res->start, | |
1053 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
1054 | } |
1055 | } | |
b5561511 BH |
1056 | } |
1057 | ||
8b8da358 BH |
1058 | void __devinit pcibios_setup_bus_self(struct pci_bus *bus) |
1059 | { | |
7eef440a | 1060 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
1061 | if (bus->self != NULL) |
1062 | pcibios_fixup_bridge(bus); | |
1063 | ||
1064 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 1065 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
1066 | */ |
1067 | if (ppc_md.pcibios_fixup_bus) | |
1068 | ppc_md.pcibios_fixup_bus(bus); | |
1069 | ||
1070 | /* Setup bus DMA mappings */ | |
1071 | if (ppc_md.pci_dma_bus_setup) | |
1072 | ppc_md.pci_dma_bus_setup(bus); | |
1073 | } | |
1074 | ||
7eef440a BH |
1075 | void __devinit pcibios_setup_bus_devices(struct pci_bus *bus) |
1076 | { | |
1077 | struct pci_dev *dev; | |
1078 | ||
1079 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1080 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1081 | ||
1082 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1083 | struct dev_archdata *sd = &dev->dev.archdata; | |
1084 | ||
1085 | /* Setup OF node pointer in archdata */ | |
1086 | sd->of_node = pci_device_to_OF_node(dev); | |
1087 | ||
1088 | /* Fixup NUMA node as it may not be setup yet by the generic | |
1089 | * code and is needed by the DMA init | |
1090 | */ | |
1091 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
1092 | ||
1093 | /* Hook up default DMA ops */ | |
1094 | sd->dma_ops = pci_dma_ops; | |
1095 | sd->dma_data = (void *)PCI_DRAM_OFFSET; | |
1096 | ||
1097 | /* Additional platform DMA/iommu setup */ | |
1098 | if (ppc_md.pci_dma_dev_setup) | |
1099 | ppc_md.pci_dma_dev_setup(dev); | |
1100 | ||
1101 | /* Read default IRQs and fixup if necessary */ | |
1102 | pci_read_irq_line(dev); | |
1103 | if (ppc_md.pci_irq_fixup) | |
1104 | ppc_md.pci_irq_fixup(dev); | |
1105 | } | |
1106 | } | |
1107 | ||
bf5e2ba2 BH |
1108 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1109 | { | |
1110 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
7eef440a | 1111 | * bases. This is -not- called when generating the PCI tree from |
8b8da358 | 1112 | * the OF device-tree. |
bf5e2ba2 BH |
1113 | */ |
1114 | if (bus->self != NULL) | |
1115 | pci_read_bridge_bases(bus); | |
bf5e2ba2 | 1116 | |
8b8da358 BH |
1117 | /* Now fixup the bus bus */ |
1118 | pcibios_setup_bus_self(bus); | |
1119 | ||
1120 | /* Now fixup devices on that bus */ | |
1121 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1122 | } |
8b8da358 | 1123 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b BH |
1124 | |
1125 | static int skip_isa_ioresource_align(struct pci_dev *dev) | |
1126 | { | |
1127 | if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && | |
1128 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) | |
1129 | return 1; | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * We need to avoid collisions with `mirrored' VGA ports | |
1135 | * and other strange ISA hardware, so we always want the | |
1136 | * addresses to be allocated in the 0x000-0x0ff region | |
1137 | * modulo 0x400. | |
1138 | * | |
1139 | * Why? Because some silly external IO cards only decode | |
1140 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1141 | * is reserved for motherboard devices that decode all 16 | |
1142 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1143 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1144 | * which might have be mirrored at 0x0100-0x03ff.. | |
1145 | */ | |
1146 | void pcibios_align_resource(void *data, struct resource *res, | |
1147 | resource_size_t size, resource_size_t align) | |
1148 | { | |
1149 | struct pci_dev *dev = data; | |
1150 | ||
1151 | if (res->flags & IORESOURCE_IO) { | |
1152 | resource_size_t start = res->start; | |
1153 | ||
1154 | if (skip_isa_ioresource_align(dev)) | |
1155 | return; | |
1156 | if (start & 0x300) { | |
1157 | start = (start + 0x3ff) & ~0x3ff; | |
1158 | res->start = start; | |
1159 | } | |
1160 | } | |
1161 | } | |
1162 | EXPORT_SYMBOL(pcibios_align_resource); | |
1163 | ||
1164 | /* | |
1165 | * Reparent resource children of pr that conflict with res | |
1166 | * under res, and make res replace those children. | |
1167 | */ | |
1168 | static int __init reparent_resources(struct resource *parent, | |
1169 | struct resource *res) | |
1170 | { | |
1171 | struct resource *p, **pp; | |
1172 | struct resource **firstpp = NULL; | |
1173 | ||
1174 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1175 | if (p->end < res->start) | |
1176 | continue; | |
1177 | if (res->end < p->start) | |
1178 | break; | |
1179 | if (p->start < res->start || p->end > res->end) | |
1180 | return -1; /* not completely contained */ | |
1181 | if (firstpp == NULL) | |
1182 | firstpp = pp; | |
1183 | } | |
1184 | if (firstpp == NULL) | |
1185 | return -1; /* didn't find any conflicting entries? */ | |
1186 | res->parent = parent; | |
1187 | res->child = *firstpp; | |
1188 | res->sibling = *pp; | |
1189 | *firstpp = res; | |
1190 | *pp = NULL; | |
1191 | for (p = res->child; p != NULL; p = p->sibling) { | |
1192 | p->parent = res; | |
b0494bc8 BH |
1193 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
1194 | p->name, | |
1195 | (unsigned long long)p->start, | |
1196 | (unsigned long long)p->end, res->name); | |
3fd94c6b BH |
1197 | } |
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | /* | |
1202 | * Handle resources of PCI devices. If the world were perfect, we could | |
1203 | * just allocate all the resource regions and do nothing more. It isn't. | |
1204 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1205 | * require us to know lots of host bridge internals. So we attempt to | |
1206 | * keep as much of the original configuration as possible, but tweak it | |
1207 | * when it's found to be wrong. | |
1208 | * | |
1209 | * Known BIOS problems we have to work around: | |
1210 | * - I/O or memory regions not configured | |
1211 | * - regions configured, but not enabled in the command register | |
1212 | * - bogus I/O addresses above 64K used | |
1213 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1214 | * the fact the PCI specs explicitly allow address decoders to be | |
1215 | * shared between expansion ROMs and other resource regions, it's | |
1216 | * at least dangerous) | |
1217 | * | |
1218 | * Our solution: | |
1219 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1220 | * This gives us fixed barriers on where we can allocate. | |
1221 | * (2) Allocate resources for all enabled devices. If there is | |
1222 | * a collision, just mark the resource as unallocated. Also | |
1223 | * disable expansion ROMs during this step. | |
1224 | * (3) Try to allocate resources for disabled devices. If the | |
1225 | * resources were assigned correctly, everything goes well, | |
1226 | * if they weren't, they won't disturb allocation of other | |
1227 | * resources. | |
1228 | * (4) Assign new addresses to resources which were either | |
1229 | * not configured at all or misconfigured. If explicitly | |
1230 | * requested by the user, configure expansion ROM address | |
1231 | * as well. | |
1232 | */ | |
1233 | ||
e90a1318 | 1234 | void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1235 | { |
e90a1318 | 1236 | struct pci_bus *b; |
3fd94c6b BH |
1237 | int i; |
1238 | struct resource *res, *pr; | |
1239 | ||
b5ae5f91 BH |
1240 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1241 | pci_domain_nr(bus), bus->number); | |
1242 | ||
e90a1318 NF |
1243 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { |
1244 | if ((res = bus->resource[i]) == NULL || !res->flags | |
b5ae5f91 | 1245 | || res->start > res->end || res->parent) |
e90a1318 NF |
1246 | continue; |
1247 | if (bus->parent == NULL) | |
1248 | pr = (res->flags & IORESOURCE_IO) ? | |
1249 | &ioport_resource : &iomem_resource; | |
1250 | else { | |
1251 | /* Don't bother with non-root busses when | |
1252 | * re-assigning all resources. We clear the | |
1253 | * resource flags as if they were colliding | |
1254 | * and as such ensure proper re-allocation | |
1255 | * later. | |
1256 | */ | |
1257 | if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) | |
1258 | goto clear_resource; | |
1259 | pr = pci_find_parent_resource(bus->self, res); | |
1260 | if (pr == res) { | |
1261 | /* this happens when the generic PCI | |
1262 | * code (wrongly) decides that this | |
1263 | * bridge is transparent -- paulus | |
3fd94c6b | 1264 | */ |
e90a1318 | 1265 | continue; |
3fd94c6b | 1266 | } |
e90a1318 | 1267 | } |
3fd94c6b | 1268 | |
b0494bc8 BH |
1269 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " |
1270 | "[0x%x], parent %p (%s)\n", | |
1271 | bus->self ? pci_name(bus->self) : "PHB", | |
1272 | bus->number, i, | |
1273 | (unsigned long long)res->start, | |
1274 | (unsigned long long)res->end, | |
1275 | (unsigned int)res->flags, | |
1276 | pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1277 | |
1278 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1279 | if (request_resource(pr, res) == 0) | |
1280 | continue; | |
1281 | /* | |
1282 | * Must be a conflict with an existing entry. | |
1283 | * Move that entry (or entries) under the | |
1284 | * bridge resource and try again. | |
1285 | */ | |
1286 | if (reparent_resources(pr, res) == 0) | |
1287 | continue; | |
3fd94c6b | 1288 | } |
e90a1318 NF |
1289 | printk(KERN_WARNING "PCI: Cannot allocate resource region " |
1290 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1291 | clear_resource: | |
1292 | res->flags = 0; | |
3fd94c6b | 1293 | } |
e90a1318 NF |
1294 | |
1295 | list_for_each_entry(b, &bus->children, node) | |
1296 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1297 | } |
1298 | ||
533b1928 | 1299 | static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1300 | { |
1301 | struct resource *pr, *r = &dev->resource[idx]; | |
1302 | ||
b0494bc8 BH |
1303 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
1304 | pci_name(dev), idx, | |
1305 | (unsigned long long)r->start, | |
1306 | (unsigned long long)r->end, | |
1307 | (unsigned int)r->flags); | |
3fd94c6b BH |
1308 | |
1309 | pr = pci_find_parent_resource(dev, r); | |
1310 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1311 | request_resource(pr, r) < 0) { | |
1312 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1313 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1314 | if (pr) | |
b0494bc8 BH |
1315 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
1316 | pr, | |
1317 | (unsigned long long)pr->start, | |
1318 | (unsigned long long)pr->end, | |
1319 | (unsigned int)pr->flags); | |
3fd94c6b BH |
1320 | /* We'll assign a new address later */ |
1321 | r->flags |= IORESOURCE_UNSET; | |
1322 | r->end -= r->start; | |
1323 | r->start = 0; | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | static void __init pcibios_allocate_resources(int pass) | |
1328 | { | |
1329 | struct pci_dev *dev = NULL; | |
1330 | int idx, disabled; | |
1331 | u16 command; | |
1332 | struct resource *r; | |
1333 | ||
1334 | for_each_pci_dev(dev) { | |
1335 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1336 | for (idx = 0; idx < 6; idx++) { | |
1337 | r = &dev->resource[idx]; | |
1338 | if (r->parent) /* Already allocated */ | |
1339 | continue; | |
1340 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1341 | continue; /* Not assigned at all */ | |
1342 | if (r->flags & IORESOURCE_IO) | |
1343 | disabled = !(command & PCI_COMMAND_IO); | |
1344 | else | |
1345 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1346 | if (pass == disabled) |
1347 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1348 | } |
1349 | if (pass) | |
1350 | continue; | |
1351 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
1352 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
1353 | /* Turn the ROM off, leave the resource region, | |
1354 | * but keep it unregistered. | |
1355 | */ | |
1356 | u32 reg; | |
b0494bc8 BH |
1357 | pr_debug("PCI: Switching off ROM of %s\n", |
1358 | pci_name(dev)); | |
3fd94c6b BH |
1359 | r->flags &= ~IORESOURCE_ROM_ENABLE; |
1360 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
1361 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1362 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1363 | } | |
1364 | } | |
1365 | } | |
1366 | ||
1367 | void __init pcibios_resource_survey(void) | |
1368 | { | |
e90a1318 NF |
1369 | struct pci_bus *b; |
1370 | ||
3fd94c6b BH |
1371 | /* Allocate and assign resources. If we re-assign everything, then |
1372 | * we skip the allocate phase | |
1373 | */ | |
e90a1318 NF |
1374 | list_for_each_entry(b, &pci_root_buses, node) |
1375 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1376 | |
1377 | if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { | |
1378 | pcibios_allocate_resources(0); | |
1379 | pcibios_allocate_resources(1); | |
1380 | } | |
1381 | ||
1382 | if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
b0494bc8 | 1383 | pr_debug("PCI: Assigning unassigned resouces...\n"); |
3fd94c6b BH |
1384 | pci_assign_unassigned_resources(); |
1385 | } | |
1386 | ||
1387 | /* Call machine dependent fixup */ | |
1388 | if (ppc_md.pcibios_fixup) | |
1389 | ppc_md.pcibios_fixup(); | |
1390 | } | |
1391 | ||
1392 | #ifdef CONFIG_HOTPLUG | |
8b8da358 | 1393 | |
fd6852c8 | 1394 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1395 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1396 | * rest of the code later, for now, keep it as-is as our main |
1397 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b BH |
1398 | */ |
1399 | void __devinit pcibios_claim_one_bus(struct pci_bus *bus) | |
1400 | { | |
1401 | struct pci_dev *dev; | |
1402 | struct pci_bus *child_bus; | |
1403 | ||
1404 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1405 | int i; | |
1406 | ||
1407 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1408 | struct resource *r = &dev->resource[i]; | |
1409 | ||
1410 | if (r->parent || !r->start || !r->flags) | |
1411 | continue; | |
fd6852c8 BH |
1412 | |
1413 | pr_debug("PCI: Claiming %s: " | |
1414 | "Resource %d: %016llx..%016llx [%x]\n", | |
1415 | pci_name(dev), i, | |
1416 | (unsigned long long)r->start, | |
1417 | (unsigned long long)r->end, | |
1418 | (unsigned int)r->flags); | |
1419 | ||
3fd94c6b BH |
1420 | pci_claim_resource(dev, i); |
1421 | } | |
1422 | } | |
1423 | ||
1424 | list_for_each_entry(child_bus, &bus->children, node) | |
1425 | pcibios_claim_one_bus(child_bus); | |
1426 | } | |
1427 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
fd6852c8 BH |
1428 | |
1429 | ||
1430 | /* pcibios_finish_adding_to_bus | |
1431 | * | |
1432 | * This is to be called by the hotplug code after devices have been | |
1433 | * added to a bus, this include calling it for a PHB that is just | |
1434 | * being added | |
1435 | */ | |
1436 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1437 | { | |
1438 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1439 | pci_domain_nr(bus), bus->number); | |
1440 | ||
1441 | /* Allocate bus and devices resources */ | |
1442 | pcibios_allocate_bus_resources(bus); | |
1443 | pcibios_claim_one_bus(bus); | |
1444 | ||
1445 | /* Add new devices to global lists. Register in proc, sysfs. */ | |
1446 | pci_bus_add_devices(bus); | |
1447 | ||
1448 | /* Fixup EEH */ | |
1449 | eeh_add_device_tree_late(bus); | |
1450 | } | |
1451 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1452 | ||
3fd94c6b | 1453 | #endif /* CONFIG_HOTPLUG */ |
549beb9b BH |
1454 | |
1455 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1456 | { | |
549beb9b BH |
1457 | if (ppc_md.pcibios_enable_device_hook) |
1458 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1459 | return -EINVAL; | |
1460 | ||
7cfb5f9a | 1461 | return pci_enable_resources(dev, mask); |
549beb9b | 1462 | } |
53280323 BH |
1463 | |
1464 | void __devinit pcibios_setup_phb_resources(struct pci_controller *hose) | |
1465 | { | |
1466 | struct pci_bus *bus = hose->bus; | |
1467 | struct resource *res; | |
1468 | int i; | |
1469 | ||
1470 | /* Hookup PHB IO resource */ | |
1471 | bus->resource[0] = res = &hose->io_resource; | |
1472 | ||
1473 | if (!res->flags) { | |
1474 | printk(KERN_WARNING "PCI: I/O resource not set for host" | |
1475 | " bridge %s (domain %d)\n", | |
1476 | hose->dn->full_name, hose->global_number); | |
1477 | #ifdef CONFIG_PPC32 | |
1478 | /* Workaround for lack of IO resource only on 32-bit */ | |
1479 | res->start = (unsigned long)hose->io_base_virt - isa_io_base; | |
1480 | res->end = res->start + IO_SPACE_LIMIT; | |
1481 | res->flags = IORESOURCE_IO; | |
1482 | #endif /* CONFIG_PPC32 */ | |
1483 | } | |
1484 | ||
1485 | pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", | |
1486 | (unsigned long long)res->start, | |
1487 | (unsigned long long)res->end, | |
1488 | (unsigned long)res->flags); | |
1489 | ||
1490 | /* Hookup PHB Memory resources */ | |
1491 | for (i = 0; i < 3; ++i) { | |
1492 | res = &hose->mem_resources[i]; | |
1493 | if (!res->flags) { | |
1494 | if (i > 0) | |
1495 | continue; | |
1496 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1497 | "host bridge %s (domain %d)\n", | |
1498 | hose->dn->full_name, hose->global_number); | |
1499 | #ifdef CONFIG_PPC32 | |
1500 | /* Workaround for lack of MEM resource only on 32-bit */ | |
1501 | res->start = hose->pci_mem_offset; | |
1502 | res->end = (resource_size_t)-1LL; | |
1503 | res->flags = IORESOURCE_MEM; | |
1504 | #endif /* CONFIG_PPC32 */ | |
1505 | } | |
1506 | bus->resource[i+1] = res; | |
1507 | ||
1508 | pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, | |
1509 | (unsigned long long)res->start, | |
1510 | (unsigned long long)res->end, | |
1511 | (unsigned long)res->flags); | |
1512 | } | |
1513 | ||
1514 | pr_debug("PCI: PHB MEM offset = %016llx\n", | |
1515 | (unsigned long long)hose->pci_mem_offset); | |
1516 | pr_debug("PCI: PHB IO offset = %08lx\n", | |
1517 | (unsigned long)hose->io_base_virt - _IO_BASE); | |
1518 | ||
1519 | } | |
1520 |