Commit | Line | Data |
---|---|---|
e05b3b4a PM |
1 | /* |
2 | * Common pmac/prep/chrp pci routines. -- Cort | |
3 | */ | |
4 | ||
e05b3b4a PM |
5 | #include <linux/kernel.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/string.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/capability.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/bootmem.h> | |
6e99e458 | 14 | #include <linux/irq.h> |
f90bb153 | 15 | #include <linux/list.h> |
e05b3b4a PM |
16 | |
17 | #include <asm/processor.h> | |
18 | #include <asm/io.h> | |
19 | #include <asm/prom.h> | |
20 | #include <asm/sections.h> | |
21 | #include <asm/pci-bridge.h> | |
22 | #include <asm/byteorder.h> | |
e05b3b4a PM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/machdep.h> | |
25 | ||
26 | #undef DEBUG | |
27 | ||
28 | #ifdef DEBUG | |
29 | #define DBG(x...) printk(x) | |
30 | #else | |
31 | #define DBG(x...) | |
32 | #endif | |
33 | ||
34 | unsigned long isa_io_base = 0; | |
e05b3b4a PM |
35 | unsigned long pci_dram_offset = 0; |
36 | int pcibios_assign_bus_offset = 1; | |
37 | ||
38 | void pcibios_make_OF_bus_map(void); | |
39 | ||
e05b3b4a PM |
40 | static void pcibios_fixup_resources(struct pci_dev* dev); |
41 | static void fixup_broken_pcnet32(struct pci_dev* dev); | |
42 | static int reparent_resources(struct resource *parent, struct resource *res); | |
43 | static void fixup_cpc710_pci64(struct pci_dev* dev); | |
44 | #ifdef CONFIG_PPC_OF | |
45 | static u8* pci_to_OF_bus_map; | |
46 | #endif | |
47 | ||
48 | /* By default, we don't re-assign bus numbers. We do this only on | |
49 | * some pmacs | |
50 | */ | |
51 | int pci_assign_all_buses; | |
52 | ||
a4c9e328 | 53 | LIST_HEAD(hose_list); |
e05b3b4a PM |
54 | |
55 | static int pci_bus_count; | |
56 | ||
2052d6d2 KG |
57 | static void |
58 | fixup_hide_host_resource_fsl(struct pci_dev* dev) | |
59 | { | |
60 | int i, class = dev->class >> 8; | |
61 | ||
62 | if ((class == PCI_CLASS_PROCESSOR_POWERPC) && | |
63 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
64 | (dev->bus->parent == NULL)) { | |
65 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
66 | dev->resource[i].start = 0; | |
67 | dev->resource[i].end = 0; | |
68 | dev->resource[i].flags = 0; | |
69 | } | |
70 | } | |
71 | } | |
72 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
73 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
74 | ||
e05b3b4a PM |
75 | static void |
76 | fixup_broken_pcnet32(struct pci_dev* dev) | |
77 | { | |
78 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
79 | dev->vendor = PCI_VENDOR_ID_AMD; | |
80 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
81 | } | |
82 | } | |
83 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
84 | ||
85 | static void | |
86 | fixup_cpc710_pci64(struct pci_dev* dev) | |
87 | { | |
88 | /* Hide the PCI64 BARs from the kernel as their content doesn't | |
89 | * fit well in the resource management | |
90 | */ | |
91 | dev->resource[0].start = dev->resource[0].end = 0; | |
92 | dev->resource[0].flags = 0; | |
93 | dev->resource[1].start = dev->resource[1].end = 0; | |
94 | dev->resource[1].flags = 0; | |
95 | } | |
96 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64); | |
97 | ||
98 | static void | |
99 | pcibios_fixup_resources(struct pci_dev *dev) | |
100 | { | |
101 | struct pci_controller* hose = (struct pci_controller *)dev->sysdata; | |
102 | int i; | |
05d3957e | 103 | resource_size_t offset, mask; |
e05b3b4a PM |
104 | |
105 | if (!hose) { | |
106 | printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); | |
107 | return; | |
108 | } | |
109 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
110 | struct resource *res = dev->resource + i; | |
111 | if (!res->flags) | |
112 | continue; | |
113 | if (res->end == 0xffffffff) { | |
685143ac | 114 | DBG("PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", |
872455e2 | 115 | pci_name(dev), i, (u64)res->start, (u64)res->end); |
e05b3b4a PM |
116 | res->end -= res->start; |
117 | res->start = 0; | |
118 | res->flags |= IORESOURCE_UNSET; | |
119 | continue; | |
120 | } | |
121 | offset = 0; | |
05d3957e | 122 | mask = (resource_size_t)-1; |
e05b3b4a PM |
123 | if (res->flags & IORESOURCE_MEM) { |
124 | offset = hose->pci_mem_offset; | |
125 | } else if (res->flags & IORESOURCE_IO) { | |
126 | offset = (unsigned long) hose->io_base_virt | |
127 | - isa_io_base; | |
05d3957e | 128 | mask = 0xffffffffu; |
e05b3b4a PM |
129 | } |
130 | if (offset != 0) { | |
05d3957e BH |
131 | res->start = (res->start + offset) & mask; |
132 | res->end = (res->end + offset) & mask; | |
0ec6b5c1 | 133 | DBG("PCI: Fixup res %d (0x%lx) of dev %s: %llx -> %llx\n", |
872455e2 SS |
134 | i, res->flags, pci_name(dev), |
135 | (u64)res->start - offset, (u64)res->start); | |
e05b3b4a PM |
136 | } |
137 | } | |
138 | ||
139 | /* Call machine specific resource fixup */ | |
140 | if (ppc_md.pcibios_fixup_resources) | |
141 | ppc_md.pcibios_fixup_resources(dev); | |
142 | } | |
143 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
144 | ||
145 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
146 | struct resource *res) | |
147 | { | |
05d3957e | 148 | resource_size_t offset = 0, mask = (resource_size_t)-1; |
e05b3b4a PM |
149 | struct pci_controller *hose = dev->sysdata; |
150 | ||
05d3957e | 151 | if (hose && res->flags & IORESOURCE_IO) { |
e05b3b4a | 152 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
05d3957e BH |
153 | mask = 0xffffffffu; |
154 | } else if (hose && res->flags & IORESOURCE_MEM) | |
e05b3b4a | 155 | offset = hose->pci_mem_offset; |
05d3957e BH |
156 | region->start = (res->start - offset) & mask; |
157 | region->end = (res->end - offset) & mask; | |
e05b3b4a PM |
158 | } |
159 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
160 | ||
161 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
162 | struct pci_bus_region *region) | |
163 | { | |
05d3957e | 164 | resource_size_t offset = 0, mask = (resource_size_t)-1; |
e05b3b4a PM |
165 | struct pci_controller *hose = dev->sysdata; |
166 | ||
05d3957e | 167 | if (hose && res->flags & IORESOURCE_IO) { |
e05b3b4a | 168 | offset = (unsigned long)hose->io_base_virt - isa_io_base; |
05d3957e BH |
169 | mask = 0xffffffffu; |
170 | } else if (hose && res->flags & IORESOURCE_MEM) | |
e05b3b4a | 171 | offset = hose->pci_mem_offset; |
05d3957e BH |
172 | res->start = (region->start + offset) & mask; |
173 | res->end = (region->end + offset) & mask; | |
e05b3b4a PM |
174 | } |
175 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
176 | ||
177 | /* | |
178 | * We need to avoid collisions with `mirrored' VGA ports | |
179 | * and other strange ISA hardware, so we always want the | |
180 | * addresses to be allocated in the 0x000-0x0ff region | |
181 | * modulo 0x400. | |
182 | * | |
183 | * Why? Because some silly external IO cards only decode | |
184 | * the low 10 bits of the IO address. The 0x00-0xff region | |
185 | * is reserved for motherboard devices that decode all 16 | |
186 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
187 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
188 | * which might have be mirrored at 0x0100-0x03ff.. | |
189 | */ | |
e31dd6e4 GKH |
190 | void pcibios_align_resource(void *data, struct resource *res, |
191 | resource_size_t size, resource_size_t align) | |
e05b3b4a PM |
192 | { |
193 | struct pci_dev *dev = data; | |
194 | ||
195 | if (res->flags & IORESOURCE_IO) { | |
e31dd6e4 | 196 | resource_size_t start = res->start; |
e05b3b4a | 197 | |
e05b3b4a PM |
198 | if (start & 0x300) { |
199 | start = (start + 0x3ff) & ~0x3ff; | |
200 | res->start = start; | |
201 | } | |
202 | } | |
203 | } | |
204 | EXPORT_SYMBOL(pcibios_align_resource); | |
205 | ||
206 | /* | |
207 | * Handle resources of PCI devices. If the world were perfect, we could | |
208 | * just allocate all the resource regions and do nothing more. It isn't. | |
209 | * On the other hand, we cannot just re-allocate all devices, as it would | |
210 | * require us to know lots of host bridge internals. So we attempt to | |
211 | * keep as much of the original configuration as possible, but tweak it | |
212 | * when it's found to be wrong. | |
213 | * | |
214 | * Known BIOS problems we have to work around: | |
215 | * - I/O or memory regions not configured | |
216 | * - regions configured, but not enabled in the command register | |
217 | * - bogus I/O addresses above 64K used | |
218 | * - expansion ROMs left enabled (this may sound harmless, but given | |
219 | * the fact the PCI specs explicitly allow address decoders to be | |
220 | * shared between expansion ROMs and other resource regions, it's | |
221 | * at least dangerous) | |
222 | * | |
223 | * Our solution: | |
224 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
225 | * This gives us fixed barriers on where we can allocate. | |
226 | * (2) Allocate resources for all enabled devices. If there is | |
227 | * a collision, just mark the resource as unallocated. Also | |
228 | * disable expansion ROMs during this step. | |
229 | * (3) Try to allocate resources for disabled devices. If the | |
230 | * resources were assigned correctly, everything goes well, | |
231 | * if they weren't, they won't disturb allocation of other | |
232 | * resources. | |
233 | * (4) Assign new addresses to resources which were either | |
234 | * not configured at all or misconfigured. If explicitly | |
235 | * requested by the user, configure expansion ROM address | |
236 | * as well. | |
237 | */ | |
238 | ||
239 | static void __init | |
240 | pcibios_allocate_bus_resources(struct list_head *bus_list) | |
241 | { | |
242 | struct pci_bus *bus; | |
243 | int i; | |
244 | struct resource *res, *pr; | |
245 | ||
246 | /* Depth-First Search on bus tree */ | |
247 | list_for_each_entry(bus, bus_list, node) { | |
248 | for (i = 0; i < 4; ++i) { | |
249 | if ((res = bus->resource[i]) == NULL || !res->flags | |
250 | || res->start > res->end) | |
251 | continue; | |
252 | if (bus->parent == NULL) | |
253 | pr = (res->flags & IORESOURCE_IO)? | |
254 | &ioport_resource: &iomem_resource; | |
255 | else { | |
256 | pr = pci_find_parent_resource(bus->self, res); | |
257 | if (pr == res) { | |
258 | /* this happens when the generic PCI | |
259 | * code (wrongly) decides that this | |
260 | * bridge is transparent -- paulus | |
261 | */ | |
262 | continue; | |
263 | } | |
264 | } | |
265 | ||
0ec6b5c1 BH |
266 | DBG("PCI: dev %s (bus 0x%02x) bridge rsrc %d: %016llx..%016llx " |
267 | "(f:0x%08lx), parent %p\n", | |
268 | bus->self ? pci_name(bus->self) : "PHB", bus->number, i, | |
872455e2 | 269 | (u64)res->start, (u64)res->end, res->flags, pr); |
0ec6b5c1 BH |
270 | |
271 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
e05b3b4a PM |
272 | if (request_resource(pr, res) == 0) |
273 | continue; | |
274 | /* | |
275 | * Must be a conflict with an existing entry. | |
276 | * Move that entry (or entries) under the | |
277 | * bridge resource and try again. | |
278 | */ | |
279 | if (reparent_resources(pr, res) == 0) | |
280 | continue; | |
281 | } | |
0ec6b5c1 BH |
282 | printk(KERN_WARNING |
283 | "PCI: Cannot allocate resource region " | |
284 | "%d of PCI bridge %d, will remap\n", | |
285 | i, bus->number); | |
286 | res->flags |= IORESOURCE_UNSET; | |
e05b3b4a PM |
287 | } |
288 | pcibios_allocate_bus_resources(&bus->children); | |
289 | } | |
290 | } | |
291 | ||
292 | /* | |
293 | * Reparent resource children of pr that conflict with res | |
294 | * under res, and make res replace those children. | |
295 | */ | |
296 | static int __init | |
297 | reparent_resources(struct resource *parent, struct resource *res) | |
298 | { | |
299 | struct resource *p, **pp; | |
300 | struct resource **firstpp = NULL; | |
301 | ||
302 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
303 | if (p->end < res->start) | |
304 | continue; | |
305 | if (res->end < p->start) | |
306 | break; | |
307 | if (p->start < res->start || p->end > res->end) | |
308 | return -1; /* not completely contained */ | |
309 | if (firstpp == NULL) | |
310 | firstpp = pp; | |
311 | } | |
312 | if (firstpp == NULL) | |
313 | return -1; /* didn't find any conflicting entries? */ | |
314 | res->parent = parent; | |
315 | res->child = *firstpp; | |
316 | res->sibling = *pp; | |
317 | *firstpp = res; | |
318 | *pp = NULL; | |
319 | for (p = res->child; p != NULL; p = p->sibling) { | |
320 | p->parent = res; | |
685143ac | 321 | DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", |
872455e2 | 322 | p->name, (u64)p->start, (u64)p->end, res->name); |
e05b3b4a PM |
323 | } |
324 | return 0; | |
325 | } | |
326 | ||
f64fddbe KG |
327 | void __init |
328 | update_bridge_resource(struct pci_dev *dev, struct resource *res) | |
e05b3b4a | 329 | { |
e05b3b4a PM |
330 | u8 io_base_lo, io_limit_lo; |
331 | u16 mem_base, mem_limit; | |
332 | u16 cmd; | |
05d3957e | 333 | resource_size_t start, end, off; |
e05b3b4a PM |
334 | struct pci_controller *hose = dev->sysdata; |
335 | ||
336 | if (!hose) { | |
337 | printk("update_bridge_base: no hose?\n"); | |
338 | return; | |
339 | } | |
340 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
341 | pci_write_config_word(dev, PCI_COMMAND, | |
342 | cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)); | |
343 | if (res->flags & IORESOURCE_IO) { | |
344 | off = (unsigned long) hose->io_base_virt - isa_io_base; | |
345 | start = res->start - off; | |
346 | end = res->end - off; | |
347 | io_base_lo = (start >> 8) & PCI_IO_RANGE_MASK; | |
348 | io_limit_lo = (end >> 8) & PCI_IO_RANGE_MASK; | |
60b2a46c | 349 | if (end > 0xffff) |
e05b3b4a | 350 | io_base_lo |= PCI_IO_RANGE_TYPE_32; |
60b2a46c | 351 | else |
e05b3b4a | 352 | io_base_lo |= PCI_IO_RANGE_TYPE_16; |
60b2a46c RV |
353 | pci_write_config_word(dev, PCI_IO_BASE_UPPER16, |
354 | start >> 16); | |
355 | pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, | |
356 | end >> 16); | |
e05b3b4a PM |
357 | pci_write_config_byte(dev, PCI_IO_BASE, io_base_lo); |
358 | pci_write_config_byte(dev, PCI_IO_LIMIT, io_limit_lo); | |
359 | ||
360 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | |
361 | == IORESOURCE_MEM) { | |
362 | off = hose->pci_mem_offset; | |
363 | mem_base = ((res->start - off) >> 16) & PCI_MEMORY_RANGE_MASK; | |
364 | mem_limit = ((res->end - off) >> 16) & PCI_MEMORY_RANGE_MASK; | |
365 | pci_write_config_word(dev, PCI_MEMORY_BASE, mem_base); | |
366 | pci_write_config_word(dev, PCI_MEMORY_LIMIT, mem_limit); | |
367 | ||
368 | } else if ((res->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)) | |
369 | == (IORESOURCE_MEM | IORESOURCE_PREFETCH)) { | |
370 | off = hose->pci_mem_offset; | |
371 | mem_base = ((res->start - off) >> 16) & PCI_PREF_RANGE_MASK; | |
372 | mem_limit = ((res->end - off) >> 16) & PCI_PREF_RANGE_MASK; | |
373 | pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, mem_base); | |
374 | pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); | |
375 | ||
376 | } else { | |
f64fddbe KG |
377 | DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n", |
378 | pci_name(dev), res->flags); | |
e05b3b4a PM |
379 | } |
380 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
381 | } | |
382 | ||
383 | static inline void alloc_resource(struct pci_dev *dev, int idx) | |
384 | { | |
385 | struct resource *pr, *r = &dev->resource[idx]; | |
386 | ||
0ec6b5c1 | 387 | DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx (f=%lx)\n", |
872455e2 | 388 | pci_name(dev), idx, (u64)r->start, (u64)r->end, r->flags); |
e05b3b4a | 389 | pr = pci_find_parent_resource(dev, r); |
0ec6b5c1 BH |
390 | if (!pr || (pr->flags & IORESOURCE_UNSET) || request_resource(pr, r) < 0) { |
391 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
392 | " of device %s, will remap\n", idx, pci_name(dev)); | |
e05b3b4a | 393 | if (pr) |
685143ac | 394 | DBG("PCI: parent is %p: %016llx-%016llx (f=%lx)\n", |
872455e2 | 395 | pr, (u64)pr->start, (u64)pr->end, pr->flags); |
e05b3b4a PM |
396 | /* We'll assign a new address later */ |
397 | r->flags |= IORESOURCE_UNSET; | |
398 | r->end -= r->start; | |
399 | r->start = 0; | |
400 | } | |
401 | } | |
402 | ||
403 | static void __init | |
404 | pcibios_allocate_resources(int pass) | |
405 | { | |
406 | struct pci_dev *dev = NULL; | |
407 | int idx, disabled; | |
408 | u16 command; | |
409 | struct resource *r; | |
410 | ||
411 | for_each_pci_dev(dev) { | |
412 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
413 | for (idx = 0; idx < 6; idx++) { | |
414 | r = &dev->resource[idx]; | |
415 | if (r->parent) /* Already allocated */ | |
416 | continue; | |
417 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
418 | continue; /* Not assigned at all */ | |
419 | if (r->flags & IORESOURCE_IO) | |
420 | disabled = !(command & PCI_COMMAND_IO); | |
421 | else | |
422 | disabled = !(command & PCI_COMMAND_MEMORY); | |
423 | if (pass == disabled) | |
424 | alloc_resource(dev, idx); | |
425 | } | |
426 | if (pass) | |
427 | continue; | |
428 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
429 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
430 | /* Turn the ROM off, leave the resource region, but keep it unregistered. */ | |
431 | u32 reg; | |
432 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); | |
433 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
434 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
435 | pci_write_config_dword(dev, dev->rom_base_reg, | |
436 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
437 | } | |
438 | } | |
439 | } | |
440 | ||
e05b3b4a PM |
441 | #ifdef CONFIG_PPC_OF |
442 | /* | |
443 | * Functions below are used on OpenFirmware machines. | |
444 | */ | |
445 | static void | |
446 | make_one_node_map(struct device_node* node, u8 pci_bus) | |
447 | { | |
a7f67bdf | 448 | const int *bus_range; |
e05b3b4a PM |
449 | int len; |
450 | ||
451 | if (pci_bus >= pci_bus_count) | |
452 | return; | |
e2eb6392 | 453 | bus_range = of_get_property(node, "bus-range", &len); |
e05b3b4a PM |
454 | if (bus_range == NULL || len < 2 * sizeof(int)) { |
455 | printk(KERN_WARNING "Can't get bus-range for %s, " | |
456 | "assuming it starts at 0\n", node->full_name); | |
457 | pci_to_OF_bus_map[pci_bus] = 0; | |
458 | } else | |
459 | pci_to_OF_bus_map[pci_bus] = bus_range[0]; | |
460 | ||
461 | for (node=node->child; node != 0;node = node->sibling) { | |
462 | struct pci_dev* dev; | |
a7f67bdf | 463 | const unsigned int *class_code, *reg; |
e05b3b4a | 464 | |
e2eb6392 | 465 | class_code = of_get_property(node, "class-code", NULL); |
e05b3b4a PM |
466 | if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
467 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) | |
468 | continue; | |
e2eb6392 | 469 | reg = of_get_property(node, "reg", NULL); |
e05b3b4a PM |
470 | if (!reg) |
471 | continue; | |
ab462768 AC |
472 | dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff)); |
473 | if (!dev || !dev->subordinate) { | |
474 | pci_dev_put(dev); | |
e05b3b4a | 475 | continue; |
ab462768 | 476 | } |
e05b3b4a | 477 | make_one_node_map(node, dev->subordinate->number); |
ab462768 | 478 | pci_dev_put(dev); |
e05b3b4a PM |
479 | } |
480 | } | |
481 | ||
482 | void | |
483 | pcibios_make_OF_bus_map(void) | |
484 | { | |
485 | int i; | |
a4c9e328 | 486 | struct pci_controller *hose, *tmp; |
a7f67bdf | 487 | struct property *map_prop; |
8c8dc322 | 488 | struct device_node *dn; |
e05b3b4a | 489 | |
5cbded58 | 490 | pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL); |
e05b3b4a PM |
491 | if (!pci_to_OF_bus_map) { |
492 | printk(KERN_ERR "Can't allocate OF bus map !\n"); | |
493 | return; | |
494 | } | |
495 | ||
496 | /* We fill the bus map with invalid values, that helps | |
497 | * debugging. | |
498 | */ | |
499 | for (i=0; i<pci_bus_count; i++) | |
500 | pci_to_OF_bus_map[i] = 0xff; | |
501 | ||
502 | /* For each hose, we begin searching bridges */ | |
a4c9e328 | 503 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
44ef3390 SR |
504 | struct device_node* node = hose->dn; |
505 | ||
e05b3b4a PM |
506 | if (!node) |
507 | continue; | |
508 | make_one_node_map(node, hose->first_busno); | |
509 | } | |
8c8dc322 SR |
510 | dn = of_find_node_by_path("/"); |
511 | map_prop = of_find_property(dn, "pci-OF-bus-map", NULL); | |
a7f67bdf JK |
512 | if (map_prop) { |
513 | BUG_ON(pci_bus_count > map_prop->length); | |
514 | memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count); | |
515 | } | |
8c8dc322 | 516 | of_node_put(dn); |
e05b3b4a PM |
517 | #ifdef DEBUG |
518 | printk("PCI->OF bus map:\n"); | |
519 | for (i=0; i<pci_bus_count; i++) { | |
520 | if (pci_to_OF_bus_map[i] == 0xff) | |
521 | continue; | |
522 | printk("%d -> %d\n", i, pci_to_OF_bus_map[i]); | |
523 | } | |
524 | #endif | |
525 | } | |
526 | ||
527 | typedef int (*pci_OF_scan_iterator)(struct device_node* node, void* data); | |
528 | ||
529 | static struct device_node* | |
530 | scan_OF_pci_childs(struct device_node* node, pci_OF_scan_iterator filter, void* data) | |
531 | { | |
532 | struct device_node* sub_node; | |
533 | ||
534 | for (; node != 0;node = node->sibling) { | |
a7f67bdf | 535 | const unsigned int *class_code; |
e05b3b4a PM |
536 | |
537 | if (filter(node, data)) | |
538 | return node; | |
539 | ||
540 | /* For PCI<->PCI bridges or CardBus bridges, we go down | |
541 | * Note: some OFs create a parent node "multifunc-device" as | |
542 | * a fake root for all functions of a multi-function device, | |
543 | * we go down them as well. | |
544 | */ | |
e2eb6392 | 545 | class_code = of_get_property(node, "class-code", NULL); |
e05b3b4a PM |
546 | if ((!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
547 | (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) && | |
548 | strcmp(node->name, "multifunc-device")) | |
549 | continue; | |
550 | sub_node = scan_OF_pci_childs(node->child, filter, data); | |
551 | if (sub_node) | |
552 | return sub_node; | |
553 | } | |
554 | return NULL; | |
555 | } | |
556 | ||
dae4828d BH |
557 | static struct device_node *scan_OF_for_pci_dev(struct device_node *parent, |
558 | unsigned int devfn) | |
e05b3b4a | 559 | { |
dae4828d BH |
560 | struct device_node *np = NULL; |
561 | const u32 *reg; | |
562 | unsigned int psize; | |
563 | ||
564 | while ((np = of_get_next_child(parent, np)) != NULL) { | |
e2eb6392 | 565 | reg = of_get_property(np, "reg", &psize); |
dae4828d BH |
566 | if (reg == NULL || psize < 4) |
567 | continue; | |
568 | if (((reg[0] >> 8) & 0xff) == devfn) | |
569 | return np; | |
570 | } | |
571 | return NULL; | |
e05b3b4a PM |
572 | } |
573 | ||
dae4828d BH |
574 | |
575 | static struct device_node *scan_OF_for_pci_bus(struct pci_bus *bus) | |
e05b3b4a | 576 | { |
dae4828d BH |
577 | struct device_node *parent, *np; |
578 | ||
579 | /* Are we a root bus ? */ | |
580 | if (bus->self == NULL || bus->parent == NULL) { | |
0b1d40c4 | 581 | struct pci_controller *hose = pci_bus_to_host(bus); |
dae4828d BH |
582 | if (hose == NULL) |
583 | return NULL; | |
44ef3390 | 584 | return of_node_get(hose->dn); |
dae4828d BH |
585 | } |
586 | ||
587 | /* not a root bus, we need to get our parent */ | |
588 | parent = scan_OF_for_pci_bus(bus->parent); | |
589 | if (parent == NULL) | |
590 | return NULL; | |
591 | ||
592 | /* now iterate for children for a match */ | |
593 | np = scan_OF_for_pci_dev(parent, bus->self->devfn); | |
594 | of_node_put(parent); | |
595 | ||
dae4828d | 596 | return np; |
e05b3b4a PM |
597 | } |
598 | ||
599 | /* | |
600 | * Scans the OF tree for a device node matching a PCI device | |
601 | */ | |
602 | struct device_node * | |
603 | pci_busdev_to_OF_node(struct pci_bus *bus, int devfn) | |
604 | { | |
dae4828d | 605 | struct device_node *parent, *np; |
e05b3b4a PM |
606 | |
607 | if (!have_of) | |
608 | return NULL; | |
e05b3b4a | 609 | |
dae4828d BH |
610 | DBG("pci_busdev_to_OF_node(%d,0x%x)\n", bus->number, devfn); |
611 | parent = scan_OF_for_pci_bus(bus); | |
612 | if (parent == NULL) | |
e05b3b4a | 613 | return NULL; |
dae4828d BH |
614 | DBG(" parent is %s\n", parent ? parent->full_name : "<NULL>"); |
615 | np = scan_OF_for_pci_dev(parent, devfn); | |
616 | of_node_put(parent); | |
617 | DBG(" result is %s\n", np ? np->full_name : "<NULL>"); | |
618 | ||
619 | /* XXX most callers don't release the returned node | |
620 | * mostly because ppc64 doesn't increase the refcount, | |
621 | * we need to fix that. | |
e05b3b4a | 622 | */ |
dae4828d | 623 | return np; |
e05b3b4a PM |
624 | } |
625 | EXPORT_SYMBOL(pci_busdev_to_OF_node); | |
626 | ||
627 | struct device_node* | |
628 | pci_device_to_OF_node(struct pci_dev *dev) | |
629 | { | |
630 | return pci_busdev_to_OF_node(dev->bus, dev->devfn); | |
631 | } | |
632 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
633 | ||
e05b3b4a PM |
634 | static int |
635 | find_OF_pci_device_filter(struct device_node* node, void* data) | |
636 | { | |
637 | return ((void *)node == data); | |
638 | } | |
639 | ||
640 | /* | |
641 | * Returns the PCI device matching a given OF node | |
642 | */ | |
643 | int | |
644 | pci_device_from_OF_node(struct device_node* node, u8* bus, u8* devfn) | |
645 | { | |
a7f67bdf | 646 | const unsigned int *reg; |
e05b3b4a PM |
647 | struct pci_controller* hose; |
648 | struct pci_dev* dev = NULL; | |
649 | ||
650 | if (!have_of) | |
651 | return -ENODEV; | |
652 | /* Make sure it's really a PCI device */ | |
653 | hose = pci_find_hose_for_OF_device(node); | |
44ef3390 | 654 | if (!hose || !hose->dn) |
e05b3b4a | 655 | return -ENODEV; |
44ef3390 | 656 | if (!scan_OF_pci_childs(hose->dn->child, |
e05b3b4a PM |
657 | find_OF_pci_device_filter, (void *)node)) |
658 | return -ENODEV; | |
e2eb6392 | 659 | reg = of_get_property(node, "reg", NULL); |
e05b3b4a PM |
660 | if (!reg) |
661 | return -ENODEV; | |
662 | *bus = (reg[0] >> 16) & 0xff; | |
663 | *devfn = ((reg[0] >> 8) & 0xff); | |
664 | ||
665 | /* Ok, here we need some tweak. If we have already renumbered | |
666 | * all busses, we can't rely on the OF bus number any more. | |
667 | * the pci_to_OF_bus_map is not enough as several PCI busses | |
668 | * may match the same OF bus number. | |
669 | */ | |
670 | if (!pci_to_OF_bus_map) | |
671 | return 0; | |
672 | ||
673 | for_each_pci_dev(dev) | |
674 | if (pci_to_OF_bus_map[dev->bus->number] == *bus && | |
675 | dev->devfn == *devfn) { | |
676 | *bus = dev->bus->number; | |
677 | pci_dev_put(dev); | |
678 | return 0; | |
679 | } | |
680 | ||
681 | return -ENODEV; | |
682 | } | |
683 | EXPORT_SYMBOL(pci_device_from_OF_node); | |
684 | ||
e05b3b4a PM |
685 | /* We create the "pci-OF-bus-map" property now so it appears in the |
686 | * /proc device tree | |
687 | */ | |
688 | void __init | |
689 | pci_create_OF_bus_map(void) | |
690 | { | |
691 | struct property* of_prop; | |
8c8dc322 SR |
692 | struct device_node *dn; |
693 | ||
e05b3b4a | 694 | of_prop = (struct property*) alloc_bootmem(sizeof(struct property) + 256); |
8c8dc322 SR |
695 | if (!of_prop) |
696 | return; | |
697 | dn = of_find_node_by_path("/"); | |
698 | if (dn) { | |
e05b3b4a PM |
699 | memset(of_prop, -1, sizeof(struct property) + 256); |
700 | of_prop->name = "pci-OF-bus-map"; | |
701 | of_prop->length = 256; | |
1a38147e | 702 | of_prop->value = &of_prop[1]; |
8c8dc322 SR |
703 | prom_add_property(dn, of_prop); |
704 | of_node_put(dn); | |
e05b3b4a PM |
705 | } |
706 | } | |
707 | ||
e05b3b4a PM |
708 | #else /* CONFIG_PPC_OF */ |
709 | void pcibios_make_OF_bus_map(void) | |
710 | { | |
711 | } | |
712 | #endif /* CONFIG_PPC_OF */ | |
713 | ||
e05b3b4a PM |
714 | static int __init |
715 | pcibios_init(void) | |
716 | { | |
a4c9e328 | 717 | struct pci_controller *hose, *tmp; |
e05b3b4a | 718 | struct pci_bus *bus; |
a4c9e328 | 719 | int next_busno = 0; |
e05b3b4a PM |
720 | |
721 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); | |
722 | ||
723 | /* Scan all of the recorded PCI controllers. */ | |
a4c9e328 | 724 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
e05b3b4a PM |
725 | if (pci_assign_all_buses) |
726 | hose->first_busno = next_busno; | |
727 | hose->last_busno = 0xff; | |
803d4573 BH |
728 | bus = pci_scan_bus_parented(hose->parent, hose->first_busno, |
729 | hose->ops, hose); | |
730 | if (bus) | |
731 | pci_bus_add_devices(bus); | |
e05b3b4a PM |
732 | hose->last_busno = bus->subordinate; |
733 | if (pci_assign_all_buses || next_busno <= hose->last_busno) | |
734 | next_busno = hose->last_busno + pcibios_assign_bus_offset; | |
735 | } | |
736 | pci_bus_count = next_busno; | |
737 | ||
738 | /* OpenFirmware based machines need a map of OF bus | |
739 | * numbers vs. kernel bus numbers since we may have to | |
740 | * remap them. | |
741 | */ | |
742 | if (pci_assign_all_buses && have_of) | |
743 | pcibios_make_OF_bus_map(); | |
744 | ||
e05b3b4a PM |
745 | /* Call machine dependent fixup */ |
746 | if (ppc_md.pcibios_fixup) | |
747 | ppc_md.pcibios_fixup(); | |
748 | ||
749 | /* Allocate and assign resources */ | |
750 | pcibios_allocate_bus_resources(&pci_root_buses); | |
751 | pcibios_allocate_resources(0); | |
752 | pcibios_allocate_resources(1); | |
b9baa20b | 753 | |
0ec6b5c1 BH |
754 | DBG("PCI: Assigning unassigned resouces...\n"); |
755 | pci_assign_unassigned_resources(); | |
e05b3b4a PM |
756 | |
757 | /* Call machine dependent post-init code */ | |
758 | if (ppc_md.pcibios_after_init) | |
759 | ppc_md.pcibios_after_init(); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | subsys_initcall(pcibios_init); | |
765 | ||
282045b4 | 766 | void pcibios_fixup_bus(struct pci_bus *bus) |
e05b3b4a PM |
767 | { |
768 | struct pci_controller *hose = (struct pci_controller *) bus->sysdata; | |
769 | unsigned long io_offset; | |
770 | struct resource *res; | |
f90bb153 | 771 | struct pci_dev *dev; |
e05b3b4a PM |
772 | int i; |
773 | ||
774 | io_offset = (unsigned long)hose->io_base_virt - isa_io_base; | |
775 | if (bus->parent == NULL) { | |
776 | /* This is a host bridge - fill in its resources */ | |
777 | hose->bus = bus; | |
778 | ||
779 | bus->resource[0] = res = &hose->io_resource; | |
780 | if (!res->flags) { | |
781 | if (io_offset) | |
782 | printk(KERN_ERR "I/O resource not set for host" | |
5516b540 | 783 | " bridge %d\n", hose->global_number); |
e05b3b4a PM |
784 | res->start = 0; |
785 | res->end = IO_SPACE_LIMIT; | |
786 | res->flags = IORESOURCE_IO; | |
787 | } | |
05d3957e BH |
788 | res->start = (res->start + io_offset) & 0xffffffffu; |
789 | res->end = (res->end + io_offset) & 0xffffffffu; | |
e05b3b4a PM |
790 | |
791 | for (i = 0; i < 3; ++i) { | |
792 | res = &hose->mem_resources[i]; | |
793 | if (!res->flags) { | |
794 | if (i > 0) | |
795 | continue; | |
796 | printk(KERN_ERR "Memory resource not set for " | |
5516b540 | 797 | "host bridge %d\n", hose->global_number); |
e05b3b4a PM |
798 | res->start = hose->pci_mem_offset; |
799 | res->end = ~0U; | |
800 | res->flags = IORESOURCE_MEM; | |
801 | } | |
802 | bus->resource[i+1] = res; | |
803 | } | |
804 | } else { | |
805 | /* This is a subordinate bridge */ | |
806 | pci_read_bridge_bases(bus); | |
807 | ||
808 | for (i = 0; i < 4; ++i) { | |
809 | if ((res = bus->resource[i]) == NULL) | |
810 | continue; | |
6d8ff10c | 811 | if (!res->flags || bus->self->transparent) |
e05b3b4a PM |
812 | continue; |
813 | if (io_offset && (res->flags & IORESOURCE_IO)) { | |
05d3957e BH |
814 | res->start = (res->start + io_offset) & |
815 | 0xffffffffu; | |
816 | res->end = (res->end + io_offset) & | |
817 | 0xffffffffu; | |
e05b3b4a PM |
818 | } else if (hose->pci_mem_offset |
819 | && (res->flags & IORESOURCE_MEM)) { | |
820 | res->start += hose->pci_mem_offset; | |
821 | res->end += hose->pci_mem_offset; | |
822 | } | |
823 | } | |
824 | } | |
825 | ||
f90bb153 | 826 | /* Platform specific bus fixups */ |
e05b3b4a PM |
827 | if (ppc_md.pcibios_fixup_bus) |
828 | ppc_md.pcibios_fixup_bus(bus); | |
f90bb153 BH |
829 | |
830 | /* Read default IRQs and fixup if necessary */ | |
831 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
832 | pci_read_irq_line(dev); | |
833 | if (ppc_md.pci_irq_fixup) | |
834 | ppc_md.pci_irq_fixup(dev); | |
835 | } | |
e05b3b4a PM |
836 | } |
837 | ||
e05b3b4a PM |
838 | /* the next one is stolen from the alpha port... */ |
839 | void __init | |
840 | pcibios_update_irq(struct pci_dev *dev, int irq) | |
841 | { | |
842 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
843 | /* XXX FIXME - update OF device tree node interrupt property */ | |
844 | } | |
845 | ||
846 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
847 | { | |
848 | u16 cmd, old_cmd; | |
849 | int idx; | |
850 | struct resource *r; | |
851 | ||
852 | if (ppc_md.pcibios_enable_device_hook) | |
853 | if (ppc_md.pcibios_enable_device_hook(dev, 0)) | |
854 | return -EINVAL; | |
855 | ||
856 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
857 | old_cmd = cmd; | |
858 | for (idx=0; idx<6; idx++) { | |
859 | r = &dev->resource[idx]; | |
860 | if (r->flags & IORESOURCE_UNSET) { | |
861 | printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev)); | |
862 | return -EINVAL; | |
863 | } | |
864 | if (r->flags & IORESOURCE_IO) | |
865 | cmd |= PCI_COMMAND_IO; | |
866 | if (r->flags & IORESOURCE_MEM) | |
867 | cmd |= PCI_COMMAND_MEMORY; | |
868 | } | |
869 | if (cmd != old_cmd) { | |
870 | printk("PCI: Enabling device %s (%04x -> %04x)\n", | |
871 | pci_name(dev), old_cmd, cmd); | |
872 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
873 | } | |
874 | return 0; | |
875 | } | |
876 | ||
0b1d40c4 | 877 | static struct pci_controller* |
e05b3b4a PM |
878 | pci_bus_to_hose(int bus) |
879 | { | |
a4c9e328 | 880 | struct pci_controller *hose, *tmp; |
e05b3b4a | 881 | |
a4c9e328 | 882 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
e05b3b4a PM |
883 | if (bus >= hose->first_busno && bus <= hose->last_busno) |
884 | return hose; | |
885 | return NULL; | |
886 | } | |
887 | ||
e05b3b4a PM |
888 | /* Provide information on locations of various I/O regions in physical |
889 | * memory. Do this on a per-card basis so that we choose the right | |
890 | * root bridge. | |
891 | * Note that the returned IO or memory base is a physical address | |
892 | */ | |
893 | ||
894 | long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) | |
895 | { | |
896 | struct pci_controller* hose; | |
897 | long result = -EOPNOTSUPP; | |
898 | ||
899 | /* Argh ! Please forgive me for that hack, but that's the | |
900 | * simplest way to get existing XFree to not lockup on some | |
901 | * G5 machines... So when something asks for bus 0 io base | |
902 | * (bus 0 is HT root), we return the AGP one instead. | |
903 | */ | |
904 | #ifdef CONFIG_PPC_PMAC | |
e8222502 | 905 | if (machine_is(powermac) && machine_is_compatible("MacRISC4")) |
e05b3b4a PM |
906 | if (bus == 0) |
907 | bus = 0xf0; | |
908 | #endif /* CONFIG_PPC_PMAC */ | |
909 | ||
910 | hose = pci_bus_to_hose(bus); | |
911 | if (!hose) | |
912 | return -ENODEV; | |
913 | ||
914 | switch (which) { | |
915 | case IOBASE_BRIDGE_NUMBER: | |
916 | return (long)hose->first_busno; | |
917 | case IOBASE_MEMORY: | |
918 | return (long)hose->pci_mem_offset; | |
919 | case IOBASE_IO: | |
920 | return (long)hose->io_base_phys; | |
921 | case IOBASE_ISA_IO: | |
922 | return (long)isa_io_base; | |
923 | case IOBASE_ISA_MEM: | |
924 | return (long)isa_mem_base; | |
925 | } | |
926 | ||
927 | return result; | |
928 | } | |
929 | ||
e05b3b4a PM |
930 | unsigned long pci_address_to_pio(phys_addr_t address) |
931 | { | |
a4c9e328 | 932 | struct pci_controller *hose, *tmp; |
e05b3b4a | 933 | |
a4c9e328 | 934 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
e05b3b4a PM |
935 | unsigned int size = hose->io_resource.end - |
936 | hose->io_resource.start + 1; | |
937 | if (address >= hose->io_base_phys && | |
938 | address < (hose->io_base_phys + size)) { | |
939 | unsigned long base = | |
940 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
941 | return base + (address - hose->io_base_phys); | |
942 | } | |
943 | } | |
944 | return (unsigned int)-1; | |
945 | } | |
946 | EXPORT_SYMBOL(pci_address_to_pio); | |
947 | ||
948 | /* | |
949 | * Null PCI config access functions, for the case when we can't | |
950 | * find a hose. | |
951 | */ | |
952 | #define NULL_PCI_OP(rw, size, type) \ | |
953 | static int \ | |
954 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
955 | { \ | |
956 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
957 | } | |
958 | ||
959 | static int | |
960 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
961 | int len, u32 *val) | |
962 | { | |
963 | return PCIBIOS_DEVICE_NOT_FOUND; | |
964 | } | |
965 | ||
966 | static int | |
967 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
968 | int len, u32 val) | |
969 | { | |
970 | return PCIBIOS_DEVICE_NOT_FOUND; | |
971 | } | |
972 | ||
973 | static struct pci_ops null_pci_ops = | |
974 | { | |
6127d1c0 NL |
975 | .read = null_read_config, |
976 | .write = null_write_config, | |
e05b3b4a PM |
977 | }; |
978 | ||
979 | /* | |
980 | * These functions are used early on before PCI scanning is done | |
981 | * and all of the pci_dev and pci_bus structures have been created. | |
982 | */ | |
983 | static struct pci_bus * | |
984 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
985 | { | |
986 | static struct pci_bus bus; | |
987 | ||
988 | if (hose == 0) { | |
989 | hose = pci_bus_to_hose(busnr); | |
990 | if (hose == 0) | |
991 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); | |
992 | } | |
993 | bus.number = busnr; | |
994 | bus.sysdata = hose; | |
995 | bus.ops = hose? hose->ops: &null_pci_ops; | |
996 | return &bus; | |
997 | } | |
998 | ||
999 | #define EARLY_PCI_OP(rw, size, type) \ | |
1000 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1001 | int devfn, int offset, type value) \ | |
1002 | { \ | |
1003 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1004 | devfn, offset, value); \ | |
1005 | } | |
1006 | ||
1007 | EARLY_PCI_OP(read, byte, u8 *) | |
1008 | EARLY_PCI_OP(read, word, u16 *) | |
1009 | EARLY_PCI_OP(read, dword, u32 *) | |
1010 | EARLY_PCI_OP(write, byte, u8) | |
1011 | EARLY_PCI_OP(write, word, u16) | |
1012 | EARLY_PCI_OP(write, dword, u32) | |
38805e5f KG |
1013 | |
1014 | extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); | |
1015 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, | |
1016 | int cap) | |
1017 | { | |
1018 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1019 | } |