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powerpc: Trivially merge several headers from asm-ppc64 to asm-powerpc
[deliverable/linux.git] / arch / powerpc / kernel / pci_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
4 *
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#undef DEBUG
15
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/mm.h>
23#include <linux/list.h>
b2ad7b5e 24#include <linux/syscalls.h>
1da177e4
LT		 25
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/prom.h>
29#include <asm/pci-bridge.h>
30#include <asm/byteorder.h>
31#include <asm/irq.h>
32#include <asm/machdep.h>
d387899f 33#include <asm/ppc-pci.h>
1da177e4
LT		 34
35#ifdef DEBUG
f9e4ec57 36#include <asm/udbg.h>
1da177e4
LT		 37#define DBG(fmt...) udbg_printf(fmt)
38#else
39#define DBG(fmt...)
40#endif
41
42unsigned long pci_probe_only = 1;
43unsigned long pci_assign_all_buses = 0;
44
45/*
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
48 */
49unsigned long io_page_mask;
50
51EXPORT_SYMBOL(io_page_mask);
52
4267292b
PM		 53#ifdef CONFIG_PPC_MULTIPLATFORM
54static void fixup_resource(struct resource *res, struct pci_dev *dev);
55static void do_bus_setup(struct pci_bus *bus);
56#endif
1da177e4
LT		 57
58unsigned int pcibios_assign_all_busses(void)
59{
60 return pci_assign_all_buses;
61}
62
63/* pci_io_base -- the base address from which io bars are offsets.
64 * This is the lowest I/O base address (so bar values are always positive),
65 * and it *must* be the start of ISA space if an ISA bus exists because
66 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
67 * page is mapped and isa_io_limit prevents access to it.
68 */
69unsigned long isa_io_base; /* NULL if no ISA bus */
70EXPORT_SYMBOL(isa_io_base);
71unsigned long pci_io_base;
72EXPORT_SYMBOL(pci_io_base);
73
74void iSeries_pcibios_init(void);
75
76LIST_HEAD(hose_list);
77
78struct dma_mapping_ops pci_dma_ops;
79EXPORT_SYMBOL(pci_dma_ops);
80
81int global_phb_number; /* Global phb counter */
82
83/* Cached ISA bridge dev. */
84struct pci_dev *ppc64_isabridge_dev = NULL;
85
86static void fixup_broken_pcnet32(struct pci_dev* dev)
87{
88 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
89 dev->vendor = PCI_VENDOR_ID_AMD;
90 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
1da177e4
LT		 91 }
92}
93DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
94
95void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
96 struct resource *res)
97{
98 unsigned long offset = 0;
99 struct pci_controller *hose = pci_bus_to_host(dev->bus);
100
101 if (!hose)
102 return;
103
104 if (res->flags & IORESOURCE_IO)
105 offset = (unsigned long)hose->io_base_virt - pci_io_base;
106
107 if (res->flags & IORESOURCE_MEM)
108 offset = hose->pci_mem_offset;
109
110 region->start = res->start - offset;
111 region->end = res->end - offset;
112}
113
43c34735
DB		 114void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
115 struct pci_bus_region *region)
116{
117 unsigned long offset = 0;
118 struct pci_controller *hose = pci_bus_to_host(dev->bus);
119
120 if (!hose)
121 return;
122
123 if (res->flags & IORESOURCE_IO)
124 offset = (unsigned long)hose->io_base_virt - pci_io_base;
125
126 if (res->flags & IORESOURCE_MEM)
127 offset = hose->pci_mem_offset;
128
129 res->start = region->start + offset;
130 res->end = region->end + offset;
131}
132
1da177e4
LT		 133#ifdef CONFIG_HOTPLUG
134EXPORT_SYMBOL(pcibios_resource_to_bus);
43c34735 135EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4
LT		 136#endif
137
138/*
139 * We need to avoid collisions with `mirrored' VGA ports
140 * and other strange ISA hardware, so we always want the
141 * addresses to be allocated in the 0x000-0x0ff region
142 * modulo 0x400.
143 *
144 * Why? Because some silly external IO cards only decode
145 * the low 10 bits of the IO address. The 0x00-0xff region
146 * is reserved for motherboard devices that decode all 16
147 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
148 * but we want to try to avoid allocating at 0x2900-0x2bff
149 * which might have be mirrored at 0x0100-0x03ff..
150 */
151void pcibios_align_resource(void *data, struct resource *res,
152 unsigned long size, unsigned long align)
153{
154 struct pci_dev *dev = data;
155 struct pci_controller *hose = pci_bus_to_host(dev->bus);
156 unsigned long start = res->start;
157 unsigned long alignto;
158
159 if (res->flags & IORESOURCE_IO) {
160 unsigned long offset = (unsigned long)hose->io_base_virt -
161 pci_io_base;
162 /* Make sure we start at our min on all hoses */
163 if (start - offset < PCIBIOS_MIN_IO)
164 start = PCIBIOS_MIN_IO + offset;
165
166 /*
167 * Put everything into 0x00-0xff region modulo 0x400
168 */
169 if (start & 0x300)
170 start = (start + 0x3ff) & ~0x3ff;
171
172 } else if (res->flags & IORESOURCE_MEM) {
173 /* Make sure we start at our min on all hoses */
174 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
175 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
176
177 /* Align to multiple of size of minimum base. */
178 alignto = max(0x1000UL, align);
179 start = ALIGN(start, alignto);
180 }
181
182 res->start = start;
183}
184
185static DEFINE_SPINLOCK(hose_spinlock);
186
187/*
188 * pci_controller(phb) initialized common variables.
189 */
b5166cc2 190static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
1da177e4
LT		 191{
192 memset(hose, 0, sizeof(struct pci_controller));
193
194 spin_lock(&hose_spinlock);
195 hose->global_number = global_phb_number++;
196 list_add_tail(&hose->list_node, &hose_list);
197 spin_unlock(&hose_spinlock);
198}
199
b5166cc2
BH		 200static void add_linux_pci_domain(struct device_node *dev,
201 struct pci_controller *phb)
202{
203 struct property *of_prop;
204 unsigned int size;
205
206 of_prop = (struct property *)
207 get_property(dev, "linux,pci-domain", &size);
208 if (of_prop != NULL)
209 return;
210 WARN_ON(of_prop && size < sizeof(int));
211 if (of_prop && size < sizeof(int))
212 of_prop = NULL;
213 size = sizeof(struct property) + sizeof(int);
214 if (of_prop == NULL) {
215 if (mem_init_done)
216 of_prop = kmalloc(size, GFP_KERNEL);
217 else
218 of_prop = alloc_bootmem(size);
219 }
220 memset(of_prop, 0, sizeof(struct property));
221 of_prop->name = "linux,pci-domain";
222 of_prop->length = sizeof(int);
223 of_prop->value = (unsigned char *)&of_prop[1];
224 *((int *)of_prop->value) = phb->global_number;
225 prom_add_property(dev, of_prop);
226}
227
228struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
229{
230 struct pci_controller *phb;
231
232 if (mem_init_done)
233 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
234 else
235 phb = alloc_bootmem(sizeof (struct pci_controller));
236 if (phb == NULL)
237 return NULL;
238 pci_setup_pci_controller(phb);
239 phb->arch_data = dev;
240 phb->is_dynamic = mem_init_done;
241 if (dev)
242 add_linux_pci_domain(dev, phb);
243 return phb;
244}
245
246void pcibios_free_controller(struct pci_controller *phb)
247{
248 if (phb->arch_data) {
249 struct device_node *np = phb->arch_data;
250 int *domain = (int *)get_property(np,
251 "linux,pci-domain", NULL);
252 if (domain)
253 *domain = -1;
254 }
255 if (phb->is_dynamic)
256 kfree(phb);
257}
258
1da177e4
LT		 259static void __init pcibios_claim_one_bus(struct pci_bus *b)
260{
261 struct pci_dev *dev;
262 struct pci_bus *child_bus;
263
264 list_for_each_entry(dev, &b->devices, bus_list) {
265 int i;
266
267 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
268 struct resource *r = &dev->resource[i];
269
270 if (r->parent || !r->start || !r->flags)
271 continue;
272 pci_claim_resource(dev, i);
273 }
274 }
275
276 list_for_each_entry(child_bus, &b->children, node)
277 pcibios_claim_one_bus(child_bus);
278}
279
280#ifndef CONFIG_PPC_ISERIES
281static void __init pcibios_claim_of_setup(void)
282{
283 struct pci_bus *b;
284
285 list_for_each_entry(b, &pci_root_buses, node)
286 pcibios_claim_one_bus(b);
287}
288#endif
289
4267292b
PM		 290#ifdef CONFIG_PPC_MULTIPLATFORM
291static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
292{
293 u32 *prop;
294 int len;
295
296 prop = (u32 *) get_property(np, name, &len);
297 if (prop && len >= 4)
298 return *prop;
299 return def;
300}
301
302static unsigned int pci_parse_of_flags(u32 addr0)
303{
304 unsigned int flags = 0;
305
306 if (addr0 & 0x02000000) {
d79e743e
PM		 307 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
308 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
309 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
4267292b 310 if (addr0 & 0x40000000)
d79e743e
PM		 311 flags |= IORESOURCE_PREFETCH
312 | PCI_BASE_ADDRESS_MEM_PREFETCH;
4267292b 313 } else if (addr0 & 0x01000000)
d79e743e 314 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
4267292b
PM		 315 return flags;
316}
317
318#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
319
320static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
321{
322 u64 base, size;
323 unsigned int flags;
324 struct resource *res;
325 u32 *addrs, i;
326 int proplen;
327
328 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
329 if (!addrs)
330 return;
331 for (; proplen >= 20; proplen -= 20, addrs += 5) {
332 flags = pci_parse_of_flags(addrs[0]);
333 if (!flags)
334 continue;
335 base = GET_64BIT(addrs, 1);
336 size = GET_64BIT(addrs, 3);
337 if (!size)
338 continue;
339 i = addrs[0] & 0xff;
340 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
341 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
342 } else if (i == dev->rom_base_reg) {
343 res = &dev->resource[PCI_ROM_RESOURCE];
344 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
345 } else {
346 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
347 continue;
348 }
349 res->start = base;
350 res->end = base + size - 1;
351 res->flags = flags;
352 res->name = pci_name(dev);
353 fixup_resource(res, dev);
354 }
355}
356
ead83717
JR		 357struct pci_dev *of_create_pci_dev(struct device_node *node,
358 struct pci_bus *bus, int devfn)
4267292b
PM		 359{
360 struct pci_dev *dev;
361 const char *type;
362
363 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
364 if (!dev)
365 return NULL;
366 type = get_property(node, "device_type", NULL);
367 if (type == NULL)
368 type = "";
369
370 memset(dev, 0, sizeof(struct pci_dev));
371 dev->bus = bus;
372 dev->sysdata = node;
373 dev->dev.parent = bus->bridge;
374 dev->dev.bus = &pci_bus_type;
375 dev->devfn = devfn;
376 dev->multifunction = 0; /* maybe a lie? */
377
378 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
379 dev->device = get_int_prop(node, "device-id", 0xffff);
380 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
381 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
382
383 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
384
385 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
386 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
387 dev->class = get_int_prop(node, "class-code", 0);
388
389 dev->current_state = 4; /* unknown power state */
390
391 if (!strcmp(type, "pci")) {
392 /* a PCI-PCI bridge */
393 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
394 dev->rom_base_reg = PCI_ROM_ADDRESS1;
395 } else if (!strcmp(type, "cardbus")) {
396 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
397 } else {
398 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
399 dev->rom_base_reg = PCI_ROM_ADDRESS;
400 dev->irq = NO_IRQ;
401 if (node->n_intrs > 0) {
402 dev->irq = node->intrs[0].line;
403 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
404 dev->irq);
405 }
406 }
407
408 pci_parse_of_addrs(node, dev);
409
410 pci_device_add(dev, bus);
411
412 /* XXX pci_scan_msi_device(dev); */
413
414 return dev;
415}
ead83717 416EXPORT_SYMBOL(of_create_pci_dev);
4267292b 417
ead83717 418void __devinit of_scan_bus(struct device_node *node,
4267292b
PM		 419 struct pci_bus *bus)
420{
421 struct device_node *child = NULL;
422 u32 *reg;
423 int reglen, devfn;
424 struct pci_dev *dev;
425
426 while ((child = of_get_next_child(node, child)) != NULL) {
427 reg = (u32 *) get_property(child, "reg", &reglen);
428 if (reg == NULL || reglen < 20)
429 continue;
430 devfn = (reg[0] >> 8) & 0xff;
431 /* create a new pci_dev for this device */
432 dev = of_create_pci_dev(child, bus, devfn);
433 if (!dev)
434 continue;
435 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
436 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
437 of_scan_pci_bridge(child, dev);
438 }
439
440 do_bus_setup(bus);
441}
ead83717 442EXPORT_SYMBOL(of_scan_bus);
4267292b 443
ead83717
JR		 444void __devinit of_scan_pci_bridge(struct device_node *node,
445 struct pci_dev *dev)
4267292b
PM		 446{
447 struct pci_bus *bus;
448 u32 *busrange, *ranges;
449 int len, i, mode;
450 struct resource *res;
451 unsigned int flags;
452 u64 size;
453
454 /* parse bus-range property */
455 busrange = (u32 *) get_property(node, "bus-range", &len);
456 if (busrange == NULL || len != 8) {
457 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
458 node->full_name);
459 return;
460 }
461 ranges = (u32 *) get_property(node, "ranges", &len);
462 if (ranges == NULL) {
463 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
464 node->full_name);
465 return;
466 }
467
468 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
469 if (!bus) {
470 printk(KERN_ERR "Failed to create pci bus for %s\n",
471 node->full_name);
472 return;
473 }
474
475 bus->primary = dev->bus->number;
476 bus->subordinate = busrange[1];
477 bus->bridge_ctl = 0;
478 bus->sysdata = node;
479
480 /* parse ranges property */
481 /* PCI #address-cells == 3 and #size-cells == 2 always */
482 res = &dev->resource[PCI_BRIDGE_RESOURCES];
483 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
484 res->flags = 0;
485 bus->resource[i] = res;
486 ++res;
487 }
488 i = 1;
489 for (; len >= 32; len -= 32, ranges += 8) {
490 flags = pci_parse_of_flags(ranges[0]);
491 size = GET_64BIT(ranges, 6);
492 if (flags == 0 || size == 0)
493 continue;
494 if (flags & IORESOURCE_IO) {
495 res = bus->resource[0];
496 if (res->flags) {
497 printk(KERN_ERR "PCI: ignoring extra I/O range"
498 " for bridge %s\n", node->full_name);
499 continue;
500 }
501 } else {
502 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
503 printk(KERN_ERR "PCI: too many memory ranges"
504 " for bridge %s\n", node->full_name);
505 continue;
506 }
507 res = bus->resource[i];
508 ++i;
509 }
510 res->start = GET_64BIT(ranges, 1);
511 res->end = res->start + size - 1;
512 res->flags = flags;
513 fixup_resource(res, dev);
514 }
515 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
516 bus->number);
517
518 mode = PCI_PROBE_NORMAL;
519 if (ppc_md.pci_probe_mode)
520 mode = ppc_md.pci_probe_mode(bus);
521 if (mode == PCI_PROBE_DEVTREE)
522 of_scan_bus(node, bus);
523 else if (mode == PCI_PROBE_NORMAL)
524 pci_scan_child_bus(bus);
525}
ead83717 526EXPORT_SYMBOL(of_scan_pci_bridge);
4267292b
PM		 527#endif /* CONFIG_PPC_MULTIPLATFORM */
528
ead83717 529void __devinit scan_phb(struct pci_controller *hose)
4267292b
PM		 530{
531 struct pci_bus *bus;
532 struct device_node *node = hose->arch_data;
533 int i, mode;
534 struct resource *res;
535
536 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
537 if (bus == NULL) {
538 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
539 hose->global_number);
540 return;
541 }
542 bus->secondary = hose->first_busno;
543 hose->bus = bus;
544
545 bus->resource[0] = res = &hose->io_resource;
546 if (res->flags && request_resource(&ioport_resource, res))
547 printk(KERN_ERR "Failed to request PCI IO region "
548 "on PCI domain %04x\n", hose->global_number);
549
550 for (i = 0; i < 3; ++i) {
551 res = &hose->mem_resources[i];
552 bus->resource[i+1] = res;
553 if (res->flags && request_resource(&iomem_resource, res))
554 printk(KERN_ERR "Failed to request PCI memory region "
555 "on PCI domain %04x\n", hose->global_number);
556 }
557
558 mode = PCI_PROBE_NORMAL;
559#ifdef CONFIG_PPC_MULTIPLATFORM
560 if (ppc_md.pci_probe_mode)
561 mode = ppc_md.pci_probe_mode(bus);
562 if (mode == PCI_PROBE_DEVTREE) {
563 bus->subordinate = hose->last_busno;
564 of_scan_bus(node, bus);
565 }
566#endif /* CONFIG_PPC_MULTIPLATFORM */
567 if (mode == PCI_PROBE_NORMAL)
568 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
569 pci_bus_add_devices(bus);
570}
571
1da177e4
LT		 572static int __init pcibios_init(void)
573{
574 struct pci_controller *hose, *tmp;
1da177e4
LT		 575
576 /* For now, override phys_mem_access_prot. If we need it,
577 * later, we may move that initialization to each ppc_md
578 */
579 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
580
581#ifdef CONFIG_PPC_ISERIES
582 iSeries_pcibios_init();
583#endif
584
585 printk("PCI: Probing PCI hardware\n");
586
587 /* Scan all of the recorded PCI controllers. */
4267292b
PM		 588 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
589 scan_phb(hose);
1da177e4
LT		 590
591#ifndef CONFIG_PPC_ISERIES
592 if (pci_probe_only)
593 pcibios_claim_of_setup();
594 else
595 /* FIXME: `else' will be removed when
596 pci_assign_unassigned_resources() is able to work
597 correctly with [partially] allocated PCI tree. */
598 pci_assign_unassigned_resources();
599#endif /* !CONFIG_PPC_ISERIES */
600
601 /* Call machine dependent final fixup */
602 if (ppc_md.pcibios_fixup)
603 ppc_md.pcibios_fixup();
604
605 /* Cache the location of the ISA bridge (if we have one) */
606 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
607 if (ppc64_isabridge_dev != NULL)
608 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
609
fe360cdf 610#ifdef CONFIG_PPC_MULTIPLATFORM
0f34f490
BH		 611 /* map in PCI I/O space */
612 phbs_remap_io();
fe360cdf 613#endif
0f34f490 614
1da177e4
LT		 615 printk("PCI: Probing PCI hardware done\n");
616
617 return 0;
618}
619
620subsys_initcall(pcibios_init);
621
622char __init *pcibios_setup(char *str)
623{
624 return str;
625}
626
627int pcibios_enable_device(struct pci_dev *dev, int mask)
628{
629 u16 cmd, oldcmd;
630 int i;
631
632 pci_read_config_word(dev, PCI_COMMAND, &cmd);
633 oldcmd = cmd;
634
635 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
636 struct resource *res = &dev->resource[i];
637
638 /* Only set up the requested stuff */
639 if (!(mask & (1<<i)))
640 continue;
641
642 if (res->flags & IORESOURCE_IO)
643 cmd |= PCI_COMMAND_IO;
644 if (res->flags & IORESOURCE_MEM)
645 cmd |= PCI_COMMAND_MEMORY;
646 }
647
648 if (cmd != oldcmd) {
649 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
650 pci_name(dev), cmd);
651 /* Enable the appropriate bits in the PCI command register. */
652 pci_write_config_word(dev, PCI_COMMAND, cmd);
653 }
654 return 0;
655}
656
657/*
658 * Return the domain number for this bus.
659 */
660int pci_domain_nr(struct pci_bus *bus)
661{
662#ifdef CONFIG_PPC_ISERIES
663 return 0;
664#else
665 struct pci_controller *hose = pci_bus_to_host(bus);
666
667 return hose->global_number;
668#endif
669}
670
671EXPORT_SYMBOL(pci_domain_nr);
672
673/* Decide whether to display the domain number in /proc */
674int pci_proc_domain(struct pci_bus *bus)
675{
676#ifdef CONFIG_PPC_ISERIES
677 return 0;
678#else
679 struct pci_controller *hose = pci_bus_to_host(bus);
680 return hose->buid;
681#endif
682}
683
684/*
685 * Platform support for /proc/bus/pci/X/Y mmap()s,
686 * modelled on the sparc64 implementation by Dave Miller.
687 * -- paulus.
688 */
689
690/*
691 * Adjust vm_pgoff of VMA such that it is the physical page offset
692 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
693 *
694 * Basically, the user finds the base address for his device which he wishes
695 * to mmap. They read the 32-bit value from the config space base register,
696 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
697 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
698 *
699 * Returns negative error code on failure, zero on success.
700 */
701static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
702 unsigned long *offset,
703 enum pci_mmap_state mmap_state)
704{
705 struct pci_controller *hose = pci_bus_to_host(dev->bus);
706 unsigned long io_offset = 0;
707 int i, res_bit;
708
709 if (hose == 0)
710 return NULL; /* should never happen */
711
712 /* If memory, add on the PCI bridge address offset */
713 if (mmap_state == pci_mmap_mem) {
714 *offset += hose->pci_mem_offset;
715 res_bit = IORESOURCE_MEM;
716 } else {
2311b1f2 717 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4
LT		 718 *offset += io_offset;
719 res_bit = IORESOURCE_IO;
720 }
721
722 /*
723 * Check that the offset requested corresponds to one of the
724 * resources of the device.
725 */
726 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
727 struct resource *rp = &dev->resource[i];
728 int flags = rp->flags;
729
730 /* treat ROM as memory (should be already) */
731 if (i == PCI_ROM_RESOURCE)
732 flags |= IORESOURCE_MEM;
733
734 /* Active and same type? */
735 if ((flags & res_bit) == 0)
736 continue;
737
738 /* In the range of this resource? */
739 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
740 continue;
741
742 /* found it! construct the final physical address */
743 if (mmap_state == pci_mmap_io)
2311b1f2 744 *offset += hose->io_base_phys - io_offset;
1da177e4
LT		 745 return rp;
746 }
747
748 return NULL;
749}
750
751/*
752 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
753 * device mapping.
754 */
755static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
756 pgprot_t protection,
757 enum pci_mmap_state mmap_state,
758 int write_combine)
759{
760 unsigned long prot = pgprot_val(protection);
761
762 /* Write combine is always 0 on non-memory space mappings. On
763 * memory space, if the user didn't pass 1, we check for a
764 * "prefetchable" resource. This is a bit hackish, but we use
765 * this to workaround the inability of /sysfs to provide a write
766 * combine bit
767 */
768 if (mmap_state != pci_mmap_mem)
769 write_combine = 0;
770 else if (write_combine == 0) {
771 if (rp->flags & IORESOURCE_PREFETCH)
772 write_combine = 1;
773 }
774
775 /* XXX would be nice to have a way to ask for write-through */
776 prot |= _PAGE_NO_CACHE;
777 if (write_combine)
778 prot &= ~_PAGE_GUARDED;
779 else
780 prot |= _PAGE_GUARDED;
781
782 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
783 prot);
784
785 return __pgprot(prot);
786}
787
788/*
789 * This one is used by /dev/mem and fbdev who have no clue about the
790 * PCI device, it tries to find the PCI device first and calls the
791 * above routine
792 */
793pgprot_t pci_phys_mem_access_prot(struct file *file,
8b150478 794 unsigned long pfn,
1da177e4
LT		 795 unsigned long size,
796 pgprot_t protection)
797{
798 struct pci_dev *pdev = NULL;
799 struct resource *found = NULL;
800 unsigned long prot = pgprot_val(protection);
8b150478 801 unsigned long offset = pfn << PAGE_SHIFT;
1da177e4
LT		 802 int i;
803
8b150478 804 if (page_is_ram(pfn))
1f8d419e 805 return __pgprot(prot);
1da177e4
LT		 806
807 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
808
809 for_each_pci_dev(pdev) {
810 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
811 struct resource *rp = &pdev->resource[i];
812 int flags = rp->flags;
813
814 /* Active and same type? */
815 if ((flags & IORESOURCE_MEM) == 0)
816 continue;
817 /* In the range of this resource? */
818 if (offset < (rp->start & PAGE_MASK) ||
819 offset > rp->end)
820 continue;
821 found = rp;
822 break;
823 }
824 if (found)
825 break;
826 }
827 if (found) {
828 if (found->flags & IORESOURCE_PREFETCH)
829 prot &= ~_PAGE_GUARDED;
830 pci_dev_put(pdev);
831 }
832
833 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
834
835 return __pgprot(prot);
836}
837
838
839/*
840 * Perform the actual remap of the pages for a PCI device mapping, as
841 * appropriate for this architecture. The region in the process to map
842 * is described by vm_start and vm_end members of VMA, the base physical
843 * address is found in vm_pgoff.
844 * The pci device structure is provided so that architectures may make mapping
845 * decisions on a per-device or per-bus basis.
846 *
847 * Returns a negative error code on failure, zero on success.
848 */
849int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
850 enum pci_mmap_state mmap_state,
851 int write_combine)
852{
853 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
854 struct resource *rp;
855 int ret;
856
857 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
858 if (rp == NULL)
859 return -EINVAL;
860
861 vma->vm_pgoff = offset >> PAGE_SHIFT;
862 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
863 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
864 vma->vm_page_prot,
865 mmap_state, write_combine);
866
867 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
868 vma->vm_end - vma->vm_start, vma->vm_page_prot);
869
870 return ret;
871}
872
873#ifdef CONFIG_PPC_MULTIPLATFORM
ff381d22 874static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
1da177e4
LT		 875{
876 struct pci_dev *pdev;
877 struct device_node *np;
878
879 pdev = to_pci_dev (dev);
880 np = pci_device_to_OF_node(pdev);
881 if (np == NULL || np->full_name == NULL)
882 return 0;
883 return sprintf(buf, "%s", np->full_name);
884}
885static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
886#endif /* CONFIG_PPC_MULTIPLATFORM */
887
888void pcibios_add_platform_entries(struct pci_dev *pdev)
889{
890#ifdef CONFIG_PPC_MULTIPLATFORM
891 device_create_file(&pdev->dev, &dev_attr_devspec);
892#endif /* CONFIG_PPC_MULTIPLATFORM */
893}
894
895#ifdef CONFIG_PPC_MULTIPLATFORM
896
897#define ISA_SPACE_MASK 0x1
898#define ISA_SPACE_IO 0x1
899
900static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
901 unsigned long phb_io_base_phys,
902 void __iomem * phb_io_base_virt)
903{
904 struct isa_range *range;
905 unsigned long pci_addr;
906 unsigned int isa_addr;
907 unsigned int size;
908 int rlen = 0;
909
910 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
911 if (range == NULL || (rlen < sizeof(struct isa_range))) {
912 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
913 "mapping 64k\n");
dfbacdc1
BH		 914 __ioremap_explicit(phb_io_base_phys,
915 (unsigned long)phb_io_base_virt,
916 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 917 return;
918 }
919
920 /* From "ISA Binding to 1275"
921 * The ranges property is laid out as an array of elements,
922 * each of which comprises:
923 * cells 0 - 1: an ISA address
924 * cells 2 - 4: a PCI address
925 * (size depending on dev->n_addr_cells)
926 * cell 5: the size of the range
927 */
928 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
929 isa_addr = range->isa_addr.a_lo;
930 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
931 range->pci_addr.a_lo;
932
933 /* Assume these are both zero */
934 if ((pci_addr != 0) || (isa_addr != 0)) {
935 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
936 __FUNCTION__);
937 return;
938 }
939
940 size = PAGE_ALIGN(range->size);
941
942 __ioremap_explicit(phb_io_base_phys,
943 (unsigned long) phb_io_base_virt,
dfbacdc1 944 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 945 }
946}
947
948void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
f7abbc19 949 struct device_node *dev, int prim)
1da177e4 950{
f7abbc19 951 unsigned int *ranges, pci_space;
1da177e4
LT		 952 unsigned long size;
953 int rlen = 0;
954 int memno = 0;
955 struct resource *res;
956 int np, na = prom_n_addr_cells(dev);
957 unsigned long pci_addr, cpu_phys_addr;
958
959 np = na + 5;
960
961 /* From "PCI Binding to 1275"
962 * The ranges property is laid out as an array of elements,
963 * each of which comprises:
964 * cells 0 - 2: a PCI address
965 * cells 3 or 3+4: a CPU physical address
966 * (size depending on dev->n_addr_cells)
967 * cells 4+5 or 5+6: the size of the range
968 */
1da177e4 969 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
b5166cc2
BH		 970 if (ranges == NULL)
971 return;
972 hose->io_base_phys = 0;
1da177e4
LT		 973 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
974 res = NULL;
f7abbc19
PM		 975 pci_space = ranges[0];
976 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1da177e4
LT		 977
978 cpu_phys_addr = ranges[3];
f7abbc19
PM		 979 if (na >= 2)
980 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1da177e4 981
f7abbc19
PM		 982 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
983 ranges += np;
1da177e4
LT		 984 if (size == 0)
985 continue;
f7abbc19
PM		 986
987 /* Now consume following elements while they are contiguous */
988 while (rlen >= np * sizeof(unsigned int)) {
989 unsigned long addr, phys;
990
991 if (ranges[0] != pci_space)
992 break;
993 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
994 phys = ranges[3];
995 if (na >= 2)
996 phys = (phys << 32) | ranges[4];
997 if (addr != pci_addr + size ||
998 phys != cpu_phys_addr + size)
999 break;
1000
1001 size += ((unsigned long)ranges[na+3] << 32)
1002 | ranges[na+4];
1003 ranges += np;
1004 rlen -= np * sizeof(unsigned int);
1005 }
1006
1007 switch ((pci_space >> 24) & 0x3) {
1da177e4
LT		 1008 case 1: /* I/O space */
1009 hose->io_base_phys = cpu_phys_addr;
1010 hose->pci_io_size = size;
1011
1012 res = &hose->io_resource;
1013 res->flags = IORESOURCE_IO;
1014 res->start = pci_addr;
1015 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1016 res->start, res->start + size - 1);
1017 break;
1018 case 2: /* memory space */
1019 memno = 0;
1020 while (memno < 3 && hose->mem_resources[memno].flags)
1021 ++memno;
1022
1023 if (memno == 0)
1024 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1025 if (memno < 3) {
1026 res = &hose->mem_resources[memno];
1027 res->flags = IORESOURCE_MEM;
1028 res->start = cpu_phys_addr;
1029 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1030 res->start, res->start + size - 1);
1031 }
1032 break;
1033 }
1034 if (res != NULL) {
1035 res->name = dev->full_name;
1036 res->end = res->start + size - 1;
1037 res->parent = NULL;
1038 res->sibling = NULL;
1039 res->child = NULL;
1040 }
1da177e4
LT		 1041 }
1042}
1043
1044void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1045{
1046 unsigned long size = hose->pci_io_size;
1047 unsigned long io_virt_offset;
1048 struct resource *res;
1049 struct device_node *isa_dn;
1050
1051 hose->io_base_virt = reserve_phb_iospace(size);
1052 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1053 hose->global_number, hose->io_base_phys,
1054 (unsigned long) hose->io_base_virt);
1055
1056 if (primary) {
1057 pci_io_base = (unsigned long)hose->io_base_virt;
1058 isa_dn = of_find_node_by_type(NULL, "isa");
1059 if (isa_dn) {
1060 isa_io_base = pci_io_base;
1061 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1062 hose->io_base_virt);
1063 of_node_put(isa_dn);
1064 /* Allow all IO */
1065 io_page_mask = -1;
1066 }
1067 }
1068
1069 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1070 res = &hose->io_resource;
1071 res->start += io_virt_offset;
1072 res->end += io_virt_offset;
1073}
1074
1075void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1076 int primary)
1077{
1078 unsigned long size = hose->pci_io_size;
1079 unsigned long io_virt_offset;
1080 struct resource *res;
1081
1082 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
dfbacdc1 1083 _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 1084 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1085 hose->global_number, hose->io_base_phys,
1086 (unsigned long) hose->io_base_virt);
1087
1088 if (primary)
1089 pci_io_base = (unsigned long)hose->io_base_virt;
1090
1091 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1092 res = &hose->io_resource;
1093 res->start += io_virt_offset;
1094 res->end += io_virt_offset;
1095}
1096
1097
1098static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1099 unsigned long *start_virt, unsigned long *size)
1100{
1101 struct pci_controller *hose = pci_bus_to_host(bus);
1102 struct pci_bus_region region;
1103 struct resource *res;
1104
1105 if (bus->self) {
1106 res = bus->resource[0];
1107 pcibios_resource_to_bus(bus->self, &region, res);
1108 *start_phys = hose->io_base_phys + region.start;
1109 *start_virt = (unsigned long) hose->io_base_virt +
1110 region.start;
1111 if (region.end > region.start)
1112 *size = region.end - region.start + 1;
1113 else {
1114 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1115 __FUNCTION__, region.start, region.end);
1116 return 1;
1117 }
1118
1119 } else {
1120 /* Root Bus */
1121 res = &hose->io_resource;
1122 *start_phys = hose->io_base_phys;
1123 *start_virt = (unsigned long) hose->io_base_virt;
1124 if (res->end > res->start)
1125 *size = res->end - res->start + 1;
1126 else {
1127 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1128 __FUNCTION__, res->start, res->end);
1129 return 1;
1130 }
1131 }
1132
1133 return 0;
1134}
1135
1136int unmap_bus_range(struct pci_bus *bus)
1137{
1138 unsigned long start_phys;
1139 unsigned long start_virt;
1140 unsigned long size;
1141
1142 if (!bus) {
1143 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1144 return 1;
1145 }
1146
1147 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1148 return 1;
1149 if (iounmap_explicit((void __iomem *) start_virt, size))
1150 return 1;
1151
1152 return 0;
1153}
1154EXPORT_SYMBOL(unmap_bus_range);
1155
1156int remap_bus_range(struct pci_bus *bus)
1157{
1158 unsigned long start_phys;
1159 unsigned long start_virt;
1160 unsigned long size;
1161
1162 if (!bus) {
1163 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1164 return 1;
1165 }
1166
1167
1168 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1169 return 1;
b5166cc2
BH		 1170 if (start_phys == 0)
1171 return 1;
1da177e4 1172 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
dfbacdc1
BH		 1173 if (__ioremap_explicit(start_phys, start_virt, size,
1174 _PAGE_NO_CACHE | _PAGE_GUARDED))
1da177e4
LT		 1175 return 1;
1176
1177 return 0;
1178}
1179EXPORT_SYMBOL(remap_bus_range);
1180
1181void phbs_remap_io(void)
1182{
1183 struct pci_controller *hose, *tmp;
1184
1185 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1186 remap_bus_range(hose->bus);
1187}
1188
1189/*
1190 * ppc64 can have multifunction devices that do not respond to function 0.
1191 * In this case we must scan all functions.
4267292b
PM		 1192 * XXX this can go now, we use the OF device tree in all the
1193 * cases that caused problems. -- paulus
1da177e4
LT		 1194 */
1195int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
1196{
4267292b
PM		 1197 return 0;
1198}
1da177e4 1199
4267292b
PM		 1200static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1201{
1202 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1203 unsigned long start, end, mask, offset;
1da177e4 1204
4267292b
PM		 1205 if (res->flags & IORESOURCE_IO) {
1206 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4 1207
4267292b
PM		 1208 start = res->start += offset;
1209 end = res->end += offset;
1da177e4 1210
4267292b
PM		 1211 /* Need to allow IO access to pages that are in the
1212 ISA range */
1213 if (start < MAX_ISA_PORT) {
1214 if (end > MAX_ISA_PORT)
1215 end = MAX_ISA_PORT;
1216
1217 start >>= PAGE_SHIFT;
1218 end >>= PAGE_SHIFT;
1da177e4 1219
4267292b
PM		 1220 /* get the range of pages for the map */
1221 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1222 io_page_mask |= mask;
1223 }
1224 } else if (res->flags & IORESOURCE_MEM) {
1225 res->start += hose->pci_mem_offset;
1226 res->end += hose->pci_mem_offset;
1227 }
1228}
1da177e4
LT		 1229
1230void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
4267292b 1231 struct pci_bus *bus)
1da177e4
LT		 1232{
1233 /* Update device resources. */
1da177e4
LT		 1234 int i;
1235
4267292b
PM		 1236 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1237 if (dev->resource[i].flags)
1238 fixup_resource(&dev->resource[i], dev);
1da177e4
LT		 1239}
1240EXPORT_SYMBOL(pcibios_fixup_device_resources);
1241
4267292b 1242static void __devinit do_bus_setup(struct pci_bus *bus)
1da177e4 1243{
4267292b 1244 struct pci_dev *dev;
1da177e4 1245
4267292b 1246 ppc_md.iommu_bus_setup(bus);
1da177e4 1247
4267292b
PM		 1248 list_for_each_entry(dev, &bus->devices, bus_list)
1249 ppc_md.iommu_dev_setup(dev);
1da177e4 1250
4267292b
PM		 1251 if (ppc_md.irq_bus_setup)
1252 ppc_md.irq_bus_setup(bus);
1253}
1da177e4 1254
4267292b
PM		 1255void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1256{
1257 struct pci_dev *dev = bus->self;
1258
1259 if (dev && pci_probe_only &&
1260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4
LT		 1261 /* This is a subordinate bridge */
1262
1263 pci_read_bridge_bases(bus);
1264 pcibios_fixup_device_resources(dev, bus);
1265 }
1266
4267292b 1267 do_bus_setup(bus);
dad32bbf 1268
1da177e4
LT		 1269 if (!pci_probe_only)
1270 return;
1271
4267292b 1272 list_for_each_entry(dev, &bus->devices, bus_list)
1da177e4
LT		 1273 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1274 pcibios_fixup_device_resources(dev, bus);
1da177e4
LT		 1275}
1276EXPORT_SYMBOL(pcibios_fixup_bus);
1277
1278/*
1279 * Reads the interrupt pin to determine if interrupt is use by card.
1280 * If the interrupt is used, then gets the interrupt line from the
1281 * openfirmware and sets it in the pci_dev and pci_config line.
1282 */
1283int pci_read_irq_line(struct pci_dev *pci_dev)
1284{
1285 u8 intpin;
1286 struct device_node *node;
1287
1288 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1289 if (intpin == 0)
1290 return 0;
1291
1292 node = pci_device_to_OF_node(pci_dev);
1293 if (node == NULL)
1294 return -1;
1295
1296 if (node->n_intrs == 0)
1297 return -1;
1298
1299 pci_dev->irq = node->intrs[0].line;
1300
1301 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1302
1303 return 0;
1304}
1305EXPORT_SYMBOL(pci_read_irq_line);
1306
2311b1f2
ME		 1307void pci_resource_to_user(const struct pci_dev *dev, int bar,
1308 const struct resource *rsrc,
1309 u64 *start, u64 *end)
1310{
1311 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1312 unsigned long offset = 0;
1313
1314 if (hose == NULL)
1315 return;
1316
1317 if (rsrc->flags & IORESOURCE_IO)
1318 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1319 hose->io_base_phys;
1320
1321 *start = rsrc->start + offset;
1322 *end = rsrc->end + offset;
1323}
1324
1da177e4 1325#endif /* CONFIG_PPC_MULTIPLATFORM */
b2ad7b5e
PM		 1326
1327
1328#define IOBASE_BRIDGE_NUMBER 0
1329#define IOBASE_MEMORY 1
1330#define IOBASE_IO 2
1331#define IOBASE_ISA_IO 3
1332#define IOBASE_ISA_MEM 4
1333
1334long sys_pciconfig_iobase(long which, unsigned long in_bus,
1335 unsigned long in_devfn)
1336{
1337 struct pci_controller* hose;
1338 struct list_head *ln;
1339 struct pci_bus *bus = NULL;
1340 struct device_node *hose_node;
1341
1342 /* Argh ! Please forgive me for that hack, but that's the
1343 * simplest way to get existing XFree to not lockup on some
1344 * G5 machines... So when something asks for bus 0 io base
1345 * (bus 0 is HT root), we return the AGP one instead.
1346 */
799d6046 1347 if (machine_is_compatible("MacRISC4"))
b2ad7b5e
PM		 1348 if (in_bus == 0)
1349 in_bus = 0xf0;
b2ad7b5e
PM		 1350
1351 /* That syscall isn't quite compatible with PCI domains, but it's
1352 * used on pre-domains setup. We return the first match
1353 */
1354
1355 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1356 bus = pci_bus_b(ln);
1357 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1358 break;
1359 bus = NULL;
1360 }
1361 if (bus == NULL || bus->sysdata == NULL)
1362 return -ENODEV;
1363
1364 hose_node = (struct device_node *)bus->sysdata;
1365 hose = PCI_DN(hose_node)->phb;
1366
1367 switch (which) {
1368 case IOBASE_BRIDGE_NUMBER:
1369 return (long)hose->first_busno;
1370 case IOBASE_MEMORY:
1371 return (long)hose->pci_mem_offset;
1372 case IOBASE_IO:
1373 return (long)hose->io_base_phys;
1374 case IOBASE_ISA_IO:
1375 return (long)isa_io_base;
1376 case IOBASE_ISA_MEM:
1377 return -EINVAL;
1378 }
1379
1380 return -EOPNOTSUPP;
1381}
Linux kernel - Deliverables
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