Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/pci.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/list.h> | |
b2ad7b5e | 23 | #include <linux/syscalls.h> |
6e99e458 | 24 | #include <linux/irq.h> |
3d5134ee | 25 | #include <linux/vmalloc.h> |
1da177e4 LT |
26 | |
27 | #include <asm/processor.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/prom.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/byteorder.h> | |
1da177e4 | 32 | #include <asm/machdep.h> |
d387899f | 33 | #include <asm/ppc-pci.h> |
1da177e4 LT |
34 | |
35 | #ifdef DEBUG | |
f9e4ec57 | 36 | #include <asm/udbg.h> |
1beb6a7d | 37 | #define DBG(fmt...) printk(fmt) |
1da177e4 LT |
38 | #else |
39 | #define DBG(fmt...) | |
40 | #endif | |
41 | ||
42 | unsigned long pci_probe_only = 1; | |
f8ef2705 | 43 | int pci_assign_all_buses = 0; |
1da177e4 | 44 | |
4267292b PM |
45 | static void fixup_resource(struct resource *res, struct pci_dev *dev); |
46 | static void do_bus_setup(struct pci_bus *bus); | |
1da177e4 | 47 | |
1da177e4 LT |
48 | /* pci_io_base -- the base address from which io bars are offsets. |
49 | * This is the lowest I/O base address (so bar values are always positive), | |
50 | * and it *must* be the start of ISA space if an ISA bus exists because | |
3d5134ee BH |
51 | * ISA drivers use hard coded offsets. If no ISA bus exists nothing |
52 | * is mapped on the first 64K of IO space | |
1da177e4 | 53 | */ |
3d5134ee | 54 | unsigned long pci_io_base = ISA_IO_BASE; |
1da177e4 LT |
55 | EXPORT_SYMBOL(pci_io_base); |
56 | ||
1da177e4 LT |
57 | LIST_HEAD(hose_list); |
58 | ||
57190708 | 59 | static struct dma_mapping_ops *pci_dma_ops; |
1da177e4 | 60 | |
98747770 SR |
61 | void set_pci_dma_ops(struct dma_mapping_ops *dma_ops) |
62 | { | |
63 | pci_dma_ops = dma_ops; | |
64 | } | |
65 | ||
57190708 SR |
66 | struct dma_mapping_ops *get_pci_dma_ops(void) |
67 | { | |
68 | return pci_dma_ops; | |
69 | } | |
70 | EXPORT_SYMBOL(get_pci_dma_ops); | |
71 | ||
1da177e4 LT |
72 | static void fixup_broken_pcnet32(struct pci_dev* dev) |
73 | { | |
74 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
75 | dev->vendor = PCI_VENDOR_ID_AMD; | |
76 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
77 | } |
78 | } | |
79 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
80 | ||
81 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
82 | struct resource *res) | |
83 | { | |
84 | unsigned long offset = 0; | |
85 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
86 | ||
87 | if (!hose) | |
88 | return; | |
89 | ||
90 | if (res->flags & IORESOURCE_IO) | |
3d5134ee | 91 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
1da177e4 LT |
92 | |
93 | if (res->flags & IORESOURCE_MEM) | |
94 | offset = hose->pci_mem_offset; | |
95 | ||
96 | region->start = res->start - offset; | |
97 | region->end = res->end - offset; | |
98 | } | |
99 | ||
43c34735 DB |
100 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
101 | struct pci_bus_region *region) | |
102 | { | |
103 | unsigned long offset = 0; | |
104 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
105 | ||
106 | if (!hose) | |
107 | return; | |
108 | ||
109 | if (res->flags & IORESOURCE_IO) | |
3d5134ee | 110 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
43c34735 DB |
111 | |
112 | if (res->flags & IORESOURCE_MEM) | |
113 | offset = hose->pci_mem_offset; | |
114 | ||
115 | res->start = region->start + offset; | |
116 | res->end = region->end + offset; | |
117 | } | |
118 | ||
1da177e4 LT |
119 | #ifdef CONFIG_HOTPLUG |
120 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 121 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
122 | #endif |
123 | ||
124 | /* | |
125 | * We need to avoid collisions with `mirrored' VGA ports | |
126 | * and other strange ISA hardware, so we always want the | |
127 | * addresses to be allocated in the 0x000-0x0ff region | |
128 | * modulo 0x400. | |
129 | * | |
130 | * Why? Because some silly external IO cards only decode | |
131 | * the low 10 bits of the IO address. The 0x00-0xff region | |
132 | * is reserved for motherboard devices that decode all 16 | |
133 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
134 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
135 | * which might have be mirrored at 0x0100-0x03ff.. | |
136 | */ | |
137 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 138 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
139 | { |
140 | struct pci_dev *dev = data; | |
141 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
e31dd6e4 | 142 | resource_size_t start = res->start; |
1da177e4 LT |
143 | unsigned long alignto; |
144 | ||
145 | if (res->flags & IORESOURCE_IO) { | |
146 | unsigned long offset = (unsigned long)hose->io_base_virt - | |
3d5134ee | 147 | _IO_BASE; |
1da177e4 LT |
148 | /* Make sure we start at our min on all hoses */ |
149 | if (start - offset < PCIBIOS_MIN_IO) | |
150 | start = PCIBIOS_MIN_IO + offset; | |
151 | ||
152 | /* | |
153 | * Put everything into 0x00-0xff region modulo 0x400 | |
154 | */ | |
155 | if (start & 0x300) | |
156 | start = (start + 0x3ff) & ~0x3ff; | |
157 | ||
158 | } else if (res->flags & IORESOURCE_MEM) { | |
159 | /* Make sure we start at our min on all hoses */ | |
160 | if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) | |
161 | start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; | |
162 | ||
163 | /* Align to multiple of size of minimum base. */ | |
164 | alignto = max(0x1000UL, align); | |
165 | start = ALIGN(start, alignto); | |
166 | } | |
167 | ||
168 | res->start = start; | |
169 | } | |
170 | ||
facf0787 | 171 | void __devinit pcibios_claim_one_bus(struct pci_bus *b) |
1da177e4 LT |
172 | { |
173 | struct pci_dev *dev; | |
174 | struct pci_bus *child_bus; | |
175 | ||
176 | list_for_each_entry(dev, &b->devices, bus_list) { | |
177 | int i; | |
178 | ||
179 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
180 | struct resource *r = &dev->resource[i]; | |
181 | ||
182 | if (r->parent || !r->start || !r->flags) | |
183 | continue; | |
184 | pci_claim_resource(dev, i); | |
185 | } | |
186 | } | |
187 | ||
188 | list_for_each_entry(child_bus, &b->children, node) | |
189 | pcibios_claim_one_bus(child_bus); | |
190 | } | |
af9deabe | 191 | #ifdef CONFIG_HOTPLUG |
192 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
193 | #endif | |
1da177e4 | 194 | |
1da177e4 LT |
195 | static void __init pcibios_claim_of_setup(void) |
196 | { | |
197 | struct pci_bus *b; | |
198 | ||
199 | list_for_each_entry(b, &pci_root_buses, node) | |
200 | pcibios_claim_one_bus(b); | |
201 | } | |
1da177e4 | 202 | |
4267292b PM |
203 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) |
204 | { | |
a7f67bdf | 205 | const u32 *prop; |
4267292b PM |
206 | int len; |
207 | ||
e2eb6392 | 208 | prop = of_get_property(np, name, &len); |
4267292b PM |
209 | if (prop && len >= 4) |
210 | return *prop; | |
211 | return def; | |
212 | } | |
213 | ||
214 | static unsigned int pci_parse_of_flags(u32 addr0) | |
215 | { | |
216 | unsigned int flags = 0; | |
217 | ||
218 | if (addr0 & 0x02000000) { | |
d79e743e PM |
219 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
220 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
221 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
4267292b | 222 | if (addr0 & 0x40000000) |
d79e743e PM |
223 | flags |= IORESOURCE_PREFETCH |
224 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
4267292b | 225 | } else if (addr0 & 0x01000000) |
d79e743e | 226 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
4267292b PM |
227 | return flags; |
228 | } | |
229 | ||
4267292b PM |
230 | |
231 | static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) | |
232 | { | |
233 | u64 base, size; | |
234 | unsigned int flags; | |
235 | struct resource *res; | |
a7f67bdf JK |
236 | const u32 *addrs; |
237 | u32 i; | |
4267292b PM |
238 | int proplen; |
239 | ||
e2eb6392 | 240 | addrs = of_get_property(node, "assigned-addresses", &proplen); |
4267292b PM |
241 | if (!addrs) |
242 | return; | |
1beb6a7d | 243 | DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs); |
4267292b PM |
244 | for (; proplen >= 20; proplen -= 20, addrs += 5) { |
245 | flags = pci_parse_of_flags(addrs[0]); | |
246 | if (!flags) | |
247 | continue; | |
327e22df JL |
248 | base = of_read_number(&addrs[1], 2); |
249 | size = of_read_number(&addrs[3], 2); | |
4267292b PM |
250 | if (!size) |
251 | continue; | |
252 | i = addrs[0] & 0xff; | |
1beb6a7d BH |
253 | DBG(" base: %llx, size: %llx, i: %x\n", |
254 | (unsigned long long)base, (unsigned long long)size, i); | |
255 | ||
4267292b PM |
256 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { |
257 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
258 | } else if (i == dev->rom_base_reg) { | |
259 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
260 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
261 | } else { | |
262 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
263 | continue; | |
264 | } | |
265 | res->start = base; | |
266 | res->end = base + size - 1; | |
267 | res->flags = flags; | |
268 | res->name = pci_name(dev); | |
269 | fixup_resource(res, dev); | |
270 | } | |
271 | } | |
272 | ||
ead83717 JR |
273 | struct pci_dev *of_create_pci_dev(struct device_node *node, |
274 | struct pci_bus *bus, int devfn) | |
4267292b PM |
275 | { |
276 | struct pci_dev *dev; | |
277 | const char *type; | |
278 | ||
bab41e9b | 279 | dev = alloc_pci_dev(); |
4267292b PM |
280 | if (!dev) |
281 | return NULL; | |
e2eb6392 | 282 | type = of_get_property(node, "device_type", NULL); |
4267292b PM |
283 | if (type == NULL) |
284 | type = ""; | |
285 | ||
1beb6a7d BH |
286 | DBG(" create device, devfn: %x, type: %s\n", devfn, type); |
287 | ||
4267292b PM |
288 | dev->bus = bus; |
289 | dev->sysdata = node; | |
290 | dev->dev.parent = bus->bridge; | |
291 | dev->dev.bus = &pci_bus_type; | |
292 | dev->devfn = devfn; | |
293 | dev->multifunction = 0; /* maybe a lie? */ | |
294 | ||
295 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); | |
296 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
297 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
298 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
299 | ||
9d17a5c6 | 300 | dev->cfg_size = pci_cfg_space_size(dev); |
4267292b PM |
301 | |
302 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
303 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
304 | dev->class = get_int_prop(node, "class-code", 0); | |
b8a3a521 | 305 | dev->revision = get_int_prop(node, "revision-id", 0); |
4267292b | 306 | |
1beb6a7d | 307 | DBG(" class: 0x%x\n", dev->class); |
b8a3a521 | 308 | DBG(" revision: 0x%x\n", dev->revision); |
1beb6a7d | 309 | |
4267292b | 310 | dev->current_state = 4; /* unknown power state */ |
bb63ab13 | 311 | dev->error_state = pci_channel_io_normal; |
8f2ea1fd | 312 | dev->dma_mask = 0xffffffff; |
4267292b | 313 | |
bb53bb3d | 314 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
4267292b PM |
315 | /* a PCI-PCI bridge */ |
316 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
317 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
318 | } else if (!strcmp(type, "cardbus")) { | |
319 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
320 | } else { | |
321 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
322 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
0ebfff14 | 323 | /* Maybe do a default OF mapping here */ |
4267292b | 324 | dev->irq = NO_IRQ; |
4267292b PM |
325 | } |
326 | ||
327 | pci_parse_of_addrs(node, dev); | |
328 | ||
1beb6a7d BH |
329 | DBG(" adding to system ...\n"); |
330 | ||
4267292b PM |
331 | pci_device_add(dev, bus); |
332 | ||
4267292b PM |
333 | return dev; |
334 | } | |
ead83717 | 335 | EXPORT_SYMBOL(of_create_pci_dev); |
4267292b | 336 | |
ead83717 | 337 | void __devinit of_scan_bus(struct device_node *node, |
4267292b PM |
338 | struct pci_bus *bus) |
339 | { | |
340 | struct device_node *child = NULL; | |
a7f67bdf | 341 | const u32 *reg; |
4267292b PM |
342 | int reglen, devfn; |
343 | struct pci_dev *dev; | |
344 | ||
1beb6a7d BH |
345 | DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number); |
346 | ||
4267292b | 347 | while ((child = of_get_next_child(node, child)) != NULL) { |
1beb6a7d | 348 | DBG(" * %s\n", child->full_name); |
e2eb6392 | 349 | reg = of_get_property(child, "reg", ®len); |
4267292b PM |
350 | if (reg == NULL || reglen < 20) |
351 | continue; | |
352 | devfn = (reg[0] >> 8) & 0xff; | |
1beb6a7d | 353 | |
4267292b PM |
354 | /* create a new pci_dev for this device */ |
355 | dev = of_create_pci_dev(child, bus, devfn); | |
356 | if (!dev) | |
357 | continue; | |
1beb6a7d BH |
358 | DBG("dev header type: %x\n", dev->hdr_type); |
359 | ||
4267292b PM |
360 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
361 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
362 | of_scan_pci_bridge(child, dev); | |
363 | } | |
364 | ||
365 | do_bus_setup(bus); | |
366 | } | |
ead83717 | 367 | EXPORT_SYMBOL(of_scan_bus); |
4267292b | 368 | |
ead83717 JR |
369 | void __devinit of_scan_pci_bridge(struct device_node *node, |
370 | struct pci_dev *dev) | |
4267292b PM |
371 | { |
372 | struct pci_bus *bus; | |
a7f67bdf | 373 | const u32 *busrange, *ranges; |
4267292b PM |
374 | int len, i, mode; |
375 | struct resource *res; | |
376 | unsigned int flags; | |
377 | u64 size; | |
378 | ||
1beb6a7d BH |
379 | DBG("of_scan_pci_bridge(%s)\n", node->full_name); |
380 | ||
4267292b | 381 | /* parse bus-range property */ |
e2eb6392 | 382 | busrange = of_get_property(node, "bus-range", &len); |
4267292b | 383 | if (busrange == NULL || len != 8) { |
1beb6a7d | 384 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", |
4267292b PM |
385 | node->full_name); |
386 | return; | |
387 | } | |
e2eb6392 | 388 | ranges = of_get_property(node, "ranges", &len); |
4267292b | 389 | if (ranges == NULL) { |
1beb6a7d | 390 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", |
4267292b PM |
391 | node->full_name); |
392 | return; | |
393 | } | |
394 | ||
395 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
396 | if (!bus) { | |
397 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
398 | node->full_name); | |
399 | return; | |
400 | } | |
401 | ||
402 | bus->primary = dev->bus->number; | |
403 | bus->subordinate = busrange[1]; | |
404 | bus->bridge_ctl = 0; | |
405 | bus->sysdata = node; | |
406 | ||
407 | /* parse ranges property */ | |
408 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
409 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
410 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
411 | res->flags = 0; | |
412 | bus->resource[i] = res; | |
413 | ++res; | |
414 | } | |
415 | i = 1; | |
416 | for (; len >= 32; len -= 32, ranges += 8) { | |
417 | flags = pci_parse_of_flags(ranges[0]); | |
327e22df | 418 | size = of_read_number(&ranges[6], 2); |
4267292b PM |
419 | if (flags == 0 || size == 0) |
420 | continue; | |
421 | if (flags & IORESOURCE_IO) { | |
422 | res = bus->resource[0]; | |
423 | if (res->flags) { | |
424 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
425 | " for bridge %s\n", node->full_name); | |
426 | continue; | |
427 | } | |
428 | } else { | |
429 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
430 | printk(KERN_ERR "PCI: too many memory ranges" | |
431 | " for bridge %s\n", node->full_name); | |
432 | continue; | |
433 | } | |
434 | res = bus->resource[i]; | |
435 | ++i; | |
436 | } | |
327e22df | 437 | res->start = of_read_number(&ranges[1], 2); |
4267292b PM |
438 | res->end = res->start + size - 1; |
439 | res->flags = flags; | |
440 | fixup_resource(res, dev); | |
441 | } | |
442 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
443 | bus->number); | |
1beb6a7d | 444 | DBG(" bus name: %s\n", bus->name); |
4267292b PM |
445 | |
446 | mode = PCI_PROBE_NORMAL; | |
447 | if (ppc_md.pci_probe_mode) | |
448 | mode = ppc_md.pci_probe_mode(bus); | |
1beb6a7d BH |
449 | DBG(" probe mode: %d\n", mode); |
450 | ||
4267292b PM |
451 | if (mode == PCI_PROBE_DEVTREE) |
452 | of_scan_bus(node, bus); | |
453 | else if (mode == PCI_PROBE_NORMAL) | |
454 | pci_scan_child_bus(bus); | |
455 | } | |
ead83717 | 456 | EXPORT_SYMBOL(of_scan_pci_bridge); |
4267292b | 457 | |
ead83717 | 458 | void __devinit scan_phb(struct pci_controller *hose) |
4267292b PM |
459 | { |
460 | struct pci_bus *bus; | |
44ef3390 | 461 | struct device_node *node = hose->dn; |
4267292b PM |
462 | int i, mode; |
463 | struct resource *res; | |
464 | ||
1beb6a7d BH |
465 | DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>"); |
466 | ||
803d4573 | 467 | bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node); |
4267292b PM |
468 | if (bus == NULL) { |
469 | printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", | |
470 | hose->global_number); | |
471 | return; | |
472 | } | |
473 | bus->secondary = hose->first_busno; | |
474 | hose->bus = bus; | |
475 | ||
9ccc4fd2 | 476 | pcibios_map_io_space(bus); |
3d5134ee | 477 | |
4267292b | 478 | bus->resource[0] = res = &hose->io_resource; |
3d5134ee | 479 | if (res->flags && request_resource(&ioport_resource, res)) { |
4267292b PM |
480 | printk(KERN_ERR "Failed to request PCI IO region " |
481 | "on PCI domain %04x\n", hose->global_number); | |
3d5134ee BH |
482 | DBG("res->start = 0x%016lx, res->end = 0x%016lx\n", |
483 | res->start, res->end); | |
484 | } | |
4267292b PM |
485 | |
486 | for (i = 0; i < 3; ++i) { | |
487 | res = &hose->mem_resources[i]; | |
488 | bus->resource[i+1] = res; | |
489 | if (res->flags && request_resource(&iomem_resource, res)) | |
490 | printk(KERN_ERR "Failed to request PCI memory region " | |
491 | "on PCI domain %04x\n", hose->global_number); | |
492 | } | |
493 | ||
494 | mode = PCI_PROBE_NORMAL; | |
99a565ba | 495 | |
1beb6a7d | 496 | if (node && ppc_md.pci_probe_mode) |
4267292b | 497 | mode = ppc_md.pci_probe_mode(bus); |
1beb6a7d | 498 | DBG(" probe mode: %d\n", mode); |
4267292b PM |
499 | if (mode == PCI_PROBE_DEVTREE) { |
500 | bus->subordinate = hose->last_busno; | |
501 | of_scan_bus(node, bus); | |
502 | } | |
99a565ba | 503 | |
4267292b PM |
504 | if (mode == PCI_PROBE_NORMAL) |
505 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
4267292b PM |
506 | } |
507 | ||
1da177e4 LT |
508 | static int __init pcibios_init(void) |
509 | { | |
510 | struct pci_controller *hose, *tmp; | |
1da177e4 LT |
511 | |
512 | /* For now, override phys_mem_access_prot. If we need it, | |
513 | * later, we may move that initialization to each ppc_md | |
514 | */ | |
515 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
516 | ||
e884e9c5 | 517 | printk(KERN_DEBUG "PCI: Probing PCI hardware\n"); |
1da177e4 LT |
518 | |
519 | /* Scan all of the recorded PCI controllers. */ | |
92eb4602 | 520 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
4267292b | 521 | scan_phb(hose); |
92eb4602 JR |
522 | pci_bus_add_devices(hose->bus); |
523 | } | |
1da177e4 | 524 | |
9ccc4fd2 SR |
525 | if (pci_probe_only) |
526 | pcibios_claim_of_setup(); | |
527 | else | |
528 | /* FIXME: `else' will be removed when | |
529 | pci_assign_unassigned_resources() is able to work | |
530 | correctly with [partially] allocated PCI tree. */ | |
531 | pci_assign_unassigned_resources(); | |
1da177e4 LT |
532 | |
533 | /* Call machine dependent final fixup */ | |
534 | if (ppc_md.pcibios_fixup) | |
535 | ppc_md.pcibios_fixup(); | |
536 | ||
e884e9c5 | 537 | printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); |
1da177e4 LT |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
542 | subsys_initcall(pcibios_init); | |
543 | ||
1da177e4 LT |
544 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
545 | { | |
546 | u16 cmd, oldcmd; | |
547 | int i; | |
548 | ||
549 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
550 | oldcmd = cmd; | |
551 | ||
552 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
553 | struct resource *res = &dev->resource[i]; | |
554 | ||
555 | /* Only set up the requested stuff */ | |
556 | if (!(mask & (1<<i))) | |
557 | continue; | |
558 | ||
559 | if (res->flags & IORESOURCE_IO) | |
560 | cmd |= PCI_COMMAND_IO; | |
561 | if (res->flags & IORESOURCE_MEM) | |
562 | cmd |= PCI_COMMAND_MEMORY; | |
563 | } | |
564 | ||
565 | if (cmd != oldcmd) { | |
566 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
567 | pci_name(dev), cmd); | |
568 | /* Enable the appropriate bits in the PCI command register. */ | |
569 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
570 | } | |
571 | return 0; | |
572 | } | |
573 | ||
1da177e4 LT |
574 | /* Decide whether to display the domain number in /proc */ |
575 | int pci_proc_domain(struct pci_bus *bus) | |
576 | { | |
c96bede6 SR |
577 | struct pci_controller *hose = pci_bus_to_host(bus); |
578 | return hose->buid != 0; | |
1da177e4 LT |
579 | } |
580 | ||
1da177e4 | 581 | |
3d5134ee BH |
582 | #ifdef CONFIG_HOTPLUG |
583 | ||
584 | int pcibios_unmap_io_space(struct pci_bus *bus) | |
1da177e4 | 585 | { |
3d5134ee | 586 | struct pci_controller *hose; |
1da177e4 | 587 | |
3d5134ee | 588 | WARN_ON(bus == NULL); |
de821204 | 589 | |
3d5134ee BH |
590 | /* If this is not a PHB, we only flush the hash table over |
591 | * the area mapped by this bridge. We don't play with the PTE | |
592 | * mappings since we might have to deal with sub-page alignemnts | |
593 | * so flushing the hash table is the only sane way to make sure | |
594 | * that no hash entries are covering that removed bridge area | |
595 | * while still allowing other busses overlapping those pages | |
596 | */ | |
597 | if (bus->self) { | |
598 | struct resource *res = bus->resource[0]; | |
1da177e4 | 599 | |
3d5134ee BH |
600 | DBG("IO unmapping for PCI-PCI bridge %s\n", |
601 | pci_name(bus->self)); | |
de821204 | 602 | |
3d5134ee BH |
603 | __flush_hash_table_range(&init_mm, res->start + _IO_BASE, |
604 | res->end - res->start + 1); | |
605 | return 0; | |
606 | } | |
1da177e4 | 607 | |
3d5134ee BH |
608 | /* Get the host bridge */ |
609 | hose = pci_bus_to_host(bus); | |
1da177e4 | 610 | |
3d5134ee BH |
611 | /* Check if we have IOs allocated */ |
612 | if (hose->io_base_alloc == 0) | |
613 | return 0; | |
de821204 | 614 | |
44ef3390 | 615 | DBG("IO unmapping for PHB %s\n", hose->dn->full_name); |
3d5134ee | 616 | DBG(" alloc=0x%p\n", hose->io_base_alloc); |
1da177e4 | 617 | |
3d5134ee BH |
618 | /* This is a PHB, we fully unmap the IO area */ |
619 | vunmap(hose->io_base_alloc); | |
1da177e4 | 620 | |
3d5134ee | 621 | return 0; |
1da177e4 | 622 | } |
3d5134ee | 623 | EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); |
1da177e4 | 624 | |
3d5134ee | 625 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 | 626 | |
3d5134ee | 627 | int __devinit pcibios_map_io_space(struct pci_bus *bus) |
1da177e4 | 628 | { |
3d5134ee BH |
629 | struct vm_struct *area; |
630 | unsigned long phys_page; | |
631 | unsigned long size_page; | |
632 | unsigned long io_virt_offset; | |
633 | struct pci_controller *hose; | |
de821204 | 634 | |
3d5134ee | 635 | WARN_ON(bus == NULL); |
31e92e0a | 636 | |
3d5134ee BH |
637 | /* If this not a PHB, nothing to do, page tables still exist and |
638 | * thus HPTEs will be faulted in when needed | |
639 | */ | |
640 | if (bus->self) { | |
641 | DBG("IO mapping for PCI-PCI bridge %s\n", | |
642 | pci_name(bus->self)); | |
643 | DBG(" virt=0x%016lx...0x%016lx\n", | |
644 | bus->resource[0]->start + _IO_BASE, | |
645 | bus->resource[0]->end + _IO_BASE); | |
646 | return 0; | |
1da177e4 LT |
647 | } |
648 | ||
3d5134ee BH |
649 | /* Get the host bridge */ |
650 | hose = pci_bus_to_host(bus); | |
651 | phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); | |
652 | size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); | |
1da177e4 | 653 | |
3d5134ee BH |
654 | /* Make sure IO area address is clear */ |
655 | hose->io_base_alloc = NULL; | |
1da177e4 | 656 | |
3d5134ee BH |
657 | /* If there's no IO to map on that bus, get away too */ |
658 | if (hose->pci_io_size == 0 || hose->io_base_phys == 0) | |
659 | return 0; | |
1da177e4 | 660 | |
3d5134ee BH |
661 | /* Let's allocate some IO space for that guy. We don't pass |
662 | * VM_IOREMAP because we don't care about alignment tricks that | |
663 | * the core does in that case. Maybe we should due to stupid card | |
664 | * with incomplete address decoding but I'd rather not deal with | |
665 | * those outside of the reserved 64K legacy region. | |
666 | */ | |
667 | area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); | |
668 | if (area == NULL) | |
669 | return -ENOMEM; | |
670 | hose->io_base_alloc = area->addr; | |
671 | hose->io_base_virt = (void __iomem *)(area->addr + | |
672 | hose->io_base_phys - phys_page); | |
673 | ||
44ef3390 | 674 | DBG("IO mapping for PHB %s\n", hose->dn->full_name); |
3d5134ee BH |
675 | DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n", |
676 | hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); | |
677 | DBG(" size=0x%016lx (alloc=0x%016lx)\n", | |
678 | hose->pci_io_size, size_page); | |
679 | ||
680 | /* Establish the mapping */ | |
681 | if (__ioremap_at(phys_page, area->addr, size_page, | |
682 | _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) | |
683 | return -ENOMEM; | |
684 | ||
685 | /* Fixup hose IO resource */ | |
686 | io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
687 | hose->io_resource.start += io_virt_offset; | |
688 | hose->io_resource.end += io_virt_offset; | |
689 | ||
690 | DBG(" hose->io_resource=0x%016lx...0x%016lx\n", | |
691 | hose->io_resource.start, hose->io_resource.end); | |
1da177e4 LT |
692 | |
693 | return 0; | |
694 | } | |
3d5134ee | 695 | EXPORT_SYMBOL_GPL(pcibios_map_io_space); |
1da177e4 | 696 | |
4267292b PM |
697 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) |
698 | { | |
699 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
c256f4b9 | 700 | unsigned long offset; |
1da177e4 | 701 | |
4267292b | 702 | if (res->flags & IORESOURCE_IO) { |
3d5134ee | 703 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
c256f4b9 AB |
704 | res->start += offset; |
705 | res->end += offset; | |
4267292b PM |
706 | } else if (res->flags & IORESOURCE_MEM) { |
707 | res->start += hose->pci_mem_offset; | |
708 | res->end += hose->pci_mem_offset; | |
709 | } | |
710 | } | |
1da177e4 LT |
711 | |
712 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, | |
4267292b | 713 | struct pci_bus *bus) |
1da177e4 LT |
714 | { |
715 | /* Update device resources. */ | |
1da177e4 LT |
716 | int i; |
717 | ||
3d5134ee BH |
718 | DBG("%s: Fixup resources:\n", pci_name(dev)); |
719 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
720 | struct resource *res = &dev->resource[i]; | |
721 | if (!res->flags) | |
722 | continue; | |
723 | ||
724 | DBG(" 0x%02x < %08lx:0x%016lx...0x%016lx\n", | |
725 | i, res->flags, res->start, res->end); | |
726 | ||
727 | fixup_resource(res, dev); | |
728 | ||
729 | DBG(" > %08lx:0x%016lx...0x%016lx\n", | |
730 | res->flags, res->start, res->end); | |
731 | } | |
1da177e4 LT |
732 | } |
733 | EXPORT_SYMBOL(pcibios_fixup_device_resources); | |
734 | ||
12d04eef BH |
735 | void __devinit pcibios_setup_new_device(struct pci_dev *dev) |
736 | { | |
737 | struct dev_archdata *sd = &dev->dev.archdata; | |
738 | ||
739 | sd->of_node = pci_device_to_OF_node(dev); | |
740 | ||
741 | DBG("PCI device %s OF node: %s\n", pci_name(dev), | |
742 | sd->of_node ? sd->of_node->full_name : "<none>"); | |
743 | ||
744 | sd->dma_ops = pci_dma_ops; | |
745 | #ifdef CONFIG_NUMA | |
746 | sd->numa_node = pcibus_to_node(dev->bus); | |
747 | #else | |
748 | sd->numa_node = -1; | |
749 | #endif | |
750 | if (ppc_md.pci_dma_dev_setup) | |
751 | ppc_md.pci_dma_dev_setup(dev); | |
752 | } | |
753 | EXPORT_SYMBOL(pcibios_setup_new_device); | |
463ce0e1 | 754 | |
4267292b | 755 | static void __devinit do_bus_setup(struct pci_bus *bus) |
1da177e4 | 756 | { |
4267292b | 757 | struct pci_dev *dev; |
1da177e4 | 758 | |
12d04eef BH |
759 | if (ppc_md.pci_dma_bus_setup) |
760 | ppc_md.pci_dma_bus_setup(bus); | |
1da177e4 | 761 | |
4267292b | 762 | list_for_each_entry(dev, &bus->devices, bus_list) |
12d04eef | 763 | pcibios_setup_new_device(dev); |
1da177e4 | 764 | |
f90bb153 BH |
765 | /* Read default IRQs and fixup if necessary */ |
766 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
767 | pci_read_irq_line(dev); | |
768 | if (ppc_md.pci_irq_fixup) | |
769 | ppc_md.pci_irq_fixup(dev); | |
770 | } | |
4267292b | 771 | } |
1da177e4 | 772 | |
4267292b PM |
773 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
774 | { | |
775 | struct pci_dev *dev = bus->self; | |
4c9d2800 BH |
776 | struct device_node *np; |
777 | ||
778 | np = pci_bus_to_OF_node(bus); | |
779 | ||
780 | DBG("pcibios_fixup_bus(%s)\n", np ? np->full_name : "<???>"); | |
4267292b PM |
781 | |
782 | if (dev && pci_probe_only && | |
783 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1da177e4 LT |
784 | /* This is a subordinate bridge */ |
785 | ||
786 | pci_read_bridge_bases(bus); | |
787 | pcibios_fixup_device_resources(dev, bus); | |
788 | } | |
789 | ||
4267292b | 790 | do_bus_setup(bus); |
dad32bbf | 791 | |
1da177e4 LT |
792 | if (!pci_probe_only) |
793 | return; | |
794 | ||
4267292b | 795 | list_for_each_entry(dev, &bus->devices, bus_list) |
1da177e4 LT |
796 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
797 | pcibios_fixup_device_resources(dev, bus); | |
1da177e4 LT |
798 | } |
799 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
800 | ||
f2c4583a | 801 | unsigned long pci_address_to_pio(phys_addr_t address) |
d4e4b352 SR |
802 | { |
803 | struct pci_controller *hose, *tmp; | |
804 | ||
805 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
806 | if (address >= hose->io_base_phys && | |
f2c4583a BH |
807 | address < (hose->io_base_phys + hose->pci_io_size)) { |
808 | unsigned long base = | |
3d5134ee | 809 | (unsigned long)hose->io_base_virt - _IO_BASE; |
f2c4583a BH |
810 | return base + (address - hose->io_base_phys); |
811 | } | |
d4e4b352 SR |
812 | } |
813 | return (unsigned int)-1; | |
814 | } | |
815 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
816 | ||
b2ad7b5e PM |
817 | |
818 | #define IOBASE_BRIDGE_NUMBER 0 | |
819 | #define IOBASE_MEMORY 1 | |
820 | #define IOBASE_IO 2 | |
821 | #define IOBASE_ISA_IO 3 | |
822 | #define IOBASE_ISA_MEM 4 | |
823 | ||
824 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
825 | unsigned long in_devfn) | |
826 | { | |
827 | struct pci_controller* hose; | |
828 | struct list_head *ln; | |
829 | struct pci_bus *bus = NULL; | |
830 | struct device_node *hose_node; | |
831 | ||
832 | /* Argh ! Please forgive me for that hack, but that's the | |
833 | * simplest way to get existing XFree to not lockup on some | |
834 | * G5 machines... So when something asks for bus 0 io base | |
835 | * (bus 0 is HT root), we return the AGP one instead. | |
836 | */ | |
799d6046 | 837 | if (machine_is_compatible("MacRISC4")) |
b2ad7b5e PM |
838 | if (in_bus == 0) |
839 | in_bus = 0xf0; | |
b2ad7b5e PM |
840 | |
841 | /* That syscall isn't quite compatible with PCI domains, but it's | |
842 | * used on pre-domains setup. We return the first match | |
843 | */ | |
844 | ||
845 | for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { | |
846 | bus = pci_bus_b(ln); | |
545da94f | 847 | if (in_bus >= bus->number && in_bus <= bus->subordinate) |
b2ad7b5e PM |
848 | break; |
849 | bus = NULL; | |
850 | } | |
851 | if (bus == NULL || bus->sysdata == NULL) | |
852 | return -ENODEV; | |
853 | ||
854 | hose_node = (struct device_node *)bus->sysdata; | |
855 | hose = PCI_DN(hose_node)->phb; | |
856 | ||
857 | switch (which) { | |
858 | case IOBASE_BRIDGE_NUMBER: | |
859 | return (long)hose->first_busno; | |
860 | case IOBASE_MEMORY: | |
861 | return (long)hose->pci_mem_offset; | |
862 | case IOBASE_IO: | |
863 | return (long)hose->io_base_phys; | |
864 | case IOBASE_ISA_IO: | |
865 | return (long)isa_io_base; | |
866 | case IOBASE_ISA_MEM: | |
867 | return -EINVAL; | |
868 | } | |
869 | ||
870 | return -EOPNOTSUPP; | |
871 | } | |
357518fa AB |
872 | |
873 | #ifdef CONFIG_NUMA | |
874 | int pcibus_to_node(struct pci_bus *bus) | |
875 | { | |
876 | struct pci_controller *phb = pci_bus_to_host(bus); | |
877 | return phb->node; | |
878 | } | |
879 | EXPORT_SYMBOL(pcibus_to_node); | |
880 | #endif |