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[PATCH] ibmveth: Remove ibmveth "liobn" field
[deliverable/linux.git] / arch / powerpc / kernel / pci_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
4 *
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#undef DEBUG
15
1da177e4
LT		 16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/bootmem.h>
21#include <linux/mm.h>
22#include <linux/list.h>
b2ad7b5e 23#include <linux/syscalls.h>
6e99e458 24#include <linux/irq.h>
1da177e4
LT		 25
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/prom.h>
29#include <asm/pci-bridge.h>
30#include <asm/byteorder.h>
1da177e4 31#include <asm/machdep.h>
d387899f 32#include <asm/ppc-pci.h>
eecba334 33#include <asm/firmware.h>
1da177e4
LT		 34
35#ifdef DEBUG
f9e4ec57 36#include <asm/udbg.h>
1beb6a7d 37#define DBG(fmt...) printk(fmt)
1da177e4
LT		 38#else
39#define DBG(fmt...)
40#endif
41
42unsigned long pci_probe_only = 1;
f8ef2705 43int pci_assign_all_buses = 0;
1da177e4 44
4267292b
PM		 45static void fixup_resource(struct resource *res, struct pci_dev *dev);
46static void do_bus_setup(struct pci_bus *bus);
9623b5d3 47static void phbs_remap_io(void);
1da177e4 48
1da177e4
LT		 49/* pci_io_base -- the base address from which io bars are offsets.
50 * This is the lowest I/O base address (so bar values are always positive),
51 * and it *must* be the start of ISA space if an ISA bus exists because
52 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
53 * page is mapped and isa_io_limit prevents access to it.
54 */
55unsigned long isa_io_base; /* NULL if no ISA bus */
56EXPORT_SYMBOL(isa_io_base);
57unsigned long pci_io_base;
58EXPORT_SYMBOL(pci_io_base);
59
60void iSeries_pcibios_init(void);
61
62LIST_HEAD(hose_list);
63
64struct dma_mapping_ops pci_dma_ops;
65EXPORT_SYMBOL(pci_dma_ops);
66
67int global_phb_number; /* Global phb counter */
68
69/* Cached ISA bridge dev. */
70struct pci_dev *ppc64_isabridge_dev = NULL;
b239cbe9 71EXPORT_SYMBOL_GPL(ppc64_isabridge_dev);
1da177e4
LT		 72
73static void fixup_broken_pcnet32(struct pci_dev* dev)
74{
75 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
76 dev->vendor = PCI_VENDOR_ID_AMD;
77 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
1da177e4
LT		 78 }
79}
80DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
81
82void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
83 struct resource *res)
84{
85 unsigned long offset = 0;
86 struct pci_controller *hose = pci_bus_to_host(dev->bus);
87
88 if (!hose)
89 return;
90
91 if (res->flags & IORESOURCE_IO)
92 offset = (unsigned long)hose->io_base_virt - pci_io_base;
93
94 if (res->flags & IORESOURCE_MEM)
95 offset = hose->pci_mem_offset;
96
97 region->start = res->start - offset;
98 region->end = res->end - offset;
99}
100
43c34735
DB		 101void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
102 struct pci_bus_region *region)
103{
104 unsigned long offset = 0;
105 struct pci_controller *hose = pci_bus_to_host(dev->bus);
106
107 if (!hose)
108 return;
109
110 if (res->flags & IORESOURCE_IO)
111 offset = (unsigned long)hose->io_base_virt - pci_io_base;
112
113 if (res->flags & IORESOURCE_MEM)
114 offset = hose->pci_mem_offset;
115
116 res->start = region->start + offset;
117 res->end = region->end + offset;
118}
119
1da177e4
LT		 120#ifdef CONFIG_HOTPLUG
121EXPORT_SYMBOL(pcibios_resource_to_bus);
43c34735 122EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4
LT		 123#endif
124
125/*
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
129 * modulo 0x400.
130 *
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
137 */
138void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 139 resource_size_t size, resource_size_t align)
1da177e4
LT		 140{
141 struct pci_dev *dev = data;
142 struct pci_controller *hose = pci_bus_to_host(dev->bus);
e31dd6e4 143 resource_size_t start = res->start;
1da177e4
LT		 144 unsigned long alignto;
145
146 if (res->flags & IORESOURCE_IO) {
147 unsigned long offset = (unsigned long)hose->io_base_virt -
148 pci_io_base;
149 /* Make sure we start at our min on all hoses */
150 if (start - offset < PCIBIOS_MIN_IO)
151 start = PCIBIOS_MIN_IO + offset;
152
153 /*
154 * Put everything into 0x00-0xff region modulo 0x400
155 */
156 if (start & 0x300)
157 start = (start + 0x3ff) & ~0x3ff;
158
159 } else if (res->flags & IORESOURCE_MEM) {
160 /* Make sure we start at our min on all hoses */
161 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
162 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
163
164 /* Align to multiple of size of minimum base. */
165 alignto = max(0x1000UL, align);
166 start = ALIGN(start, alignto);
167 }
168
169 res->start = start;
170}
171
172static DEFINE_SPINLOCK(hose_spinlock);
173
174/*
175 * pci_controller(phb) initialized common variables.
176 */
b5166cc2 177static void __devinit pci_setup_pci_controller(struct pci_controller *hose)
1da177e4
LT		 178{
179 memset(hose, 0, sizeof(struct pci_controller));
180
181 spin_lock(&hose_spinlock);
182 hose->global_number = global_phb_number++;
183 list_add_tail(&hose->list_node, &hose_list);
184 spin_unlock(&hose_spinlock);
185}
186
b5166cc2
BH		 187struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
188{
189 struct pci_controller *phb;
190
191 if (mem_init_done)
192 phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
193 else
194 phb = alloc_bootmem(sizeof (struct pci_controller));
195 if (phb == NULL)
196 return NULL;
197 pci_setup_pci_controller(phb);
198 phb->arch_data = dev;
199 phb->is_dynamic = mem_init_done;
284a9406
AB		 200 if (dev) {
201 int nid = of_node_to_nid(dev);
202
203 if (nid < 0 || !node_online(nid))
204 nid = -1;
205
206 PHB_SET_NODE(phb, nid);
207 }
b5166cc2
BH		 208 return phb;
209}
210
211void pcibios_free_controller(struct pci_controller *phb)
212{
b5166cc2
BH		 213 if (phb->is_dynamic)
214 kfree(phb);
215}
216
facf0787 217void __devinit pcibios_claim_one_bus(struct pci_bus *b)
1da177e4
LT		 218{
219 struct pci_dev *dev;
220 struct pci_bus *child_bus;
221
222 list_for_each_entry(dev, &b->devices, bus_list) {
223 int i;
224
225 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
226 struct resource *r = &dev->resource[i];
227
228 if (r->parent || !r->start || !r->flags)
229 continue;
230 pci_claim_resource(dev, i);
231 }
232 }
233
234 list_for_each_entry(child_bus, &b->children, node)
235 pcibios_claim_one_bus(child_bus);
236}
af9deabe 237#ifdef CONFIG_HOTPLUG
238EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
239#endif
1da177e4 240
1da177e4
LT		 241static void __init pcibios_claim_of_setup(void)
242{
243 struct pci_bus *b;
244
eecba334
SR		 245 if (firmware_has_feature(FW_FEATURE_ISERIES))
246 return;
247
1da177e4
LT		 248 list_for_each_entry(b, &pci_root_buses, node)
249 pcibios_claim_one_bus(b);
250}
1da177e4 251
4267292b
PM		 252static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
253{
a7f67bdf 254 const u32 *prop;
4267292b
PM		 255 int len;
256
a7f67bdf 257 prop = get_property(np, name, &len);
4267292b
PM		 258 if (prop && len >= 4)
259 return *prop;
260 return def;
261}
262
263static unsigned int pci_parse_of_flags(u32 addr0)
264{
265 unsigned int flags = 0;
266
267 if (addr0 & 0x02000000) {
d79e743e
PM		 268 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
269 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
270 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
4267292b 271 if (addr0 & 0x40000000)
d79e743e
PM		 272 flags |= IORESOURCE_PREFETCH
273 | PCI_BASE_ADDRESS_MEM_PREFETCH;
4267292b 274 } else if (addr0 & 0x01000000)
d79e743e 275 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
4267292b
PM		 276 return flags;
277}
278
279#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
280
281static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
282{
283 u64 base, size;
284 unsigned int flags;
285 struct resource *res;
a7f67bdf
JK		 286 const u32 *addrs;
287 u32 i;
4267292b
PM		 288 int proplen;
289
a7f67bdf 290 addrs = get_property(node, "assigned-addresses", &proplen);
4267292b
PM		 291 if (!addrs)
292 return;
1beb6a7d 293 DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
4267292b
PM		 294 for (; proplen >= 20; proplen -= 20, addrs += 5) {
295 flags = pci_parse_of_flags(addrs[0]);
296 if (!flags)
297 continue;
298 base = GET_64BIT(addrs, 1);
299 size = GET_64BIT(addrs, 3);
300 if (!size)
301 continue;
302 i = addrs[0] & 0xff;
1beb6a7d
BH		 303 DBG(" base: %llx, size: %llx, i: %x\n",
304 (unsigned long long)base, (unsigned long long)size, i);
305
4267292b
PM		 306 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
307 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
308 } else if (i == dev->rom_base_reg) {
309 res = &dev->resource[PCI_ROM_RESOURCE];
310 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
311 } else {
312 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
313 continue;
314 }
315 res->start = base;
316 res->end = base + size - 1;
317 res->flags = flags;
318 res->name = pci_name(dev);
319 fixup_resource(res, dev);
320 }
321}
322
ead83717
JR		 323struct pci_dev *of_create_pci_dev(struct device_node *node,
324 struct pci_bus *bus, int devfn)
4267292b
PM		 325{
326 struct pci_dev *dev;
327 const char *type;
328
329 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
330 if (!dev)
331 return NULL;
332 type = get_property(node, "device_type", NULL);
333 if (type == NULL)
334 type = "";
335
1beb6a7d
BH		 336 DBG(" create device, devfn: %x, type: %s\n", devfn, type);
337
4267292b
PM		 338 memset(dev, 0, sizeof(struct pci_dev));
339 dev->bus = bus;
340 dev->sysdata = node;
341 dev->dev.parent = bus->bridge;
342 dev->dev.bus = &pci_bus_type;
343 dev->devfn = devfn;
344 dev->multifunction = 0; /* maybe a lie? */
345
346 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
347 dev->device = get_int_prop(node, "device-id", 0xffff);
348 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
349 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
350
9d17a5c6 351 dev->cfg_size = pci_cfg_space_size(dev);
4267292b
PM		 352
353 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
354 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
355 dev->class = get_int_prop(node, "class-code", 0);
356
1beb6a7d
BH		 357 DBG(" class: 0x%x\n", dev->class);
358
4267292b
PM		 359 dev->current_state = 4; /* unknown power state */
360
bb53bb3d 361 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
4267292b
PM		 362 /* a PCI-PCI bridge */
363 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
364 dev->rom_base_reg = PCI_ROM_ADDRESS1;
365 } else if (!strcmp(type, "cardbus")) {
366 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
367 } else {
368 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
369 dev->rom_base_reg = PCI_ROM_ADDRESS;
0ebfff14 370 /* Maybe do a default OF mapping here */
4267292b 371 dev->irq = NO_IRQ;
4267292b
PM		 372 }
373
374 pci_parse_of_addrs(node, dev);
375
1beb6a7d
BH		 376 DBG(" adding to system ...\n");
377
4267292b
PM		 378 pci_device_add(dev, bus);
379
380 /* XXX pci_scan_msi_device(dev); */
381
382 return dev;
383}
ead83717 384EXPORT_SYMBOL(of_create_pci_dev);
4267292b 385
ead83717 386void __devinit of_scan_bus(struct device_node *node,
4267292b
PM		 387 struct pci_bus *bus)
388{
389 struct device_node *child = NULL;
a7f67bdf 390 const u32 *reg;
4267292b
PM		 391 int reglen, devfn;
392 struct pci_dev *dev;
393
1beb6a7d
BH		 394 DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
395
4267292b 396 while ((child = of_get_next_child(node, child)) != NULL) {
1beb6a7d 397 DBG(" * %s\n", child->full_name);
a7f67bdf 398 reg = get_property(child, "reg", &reglen);
4267292b
PM		 399 if (reg == NULL || reglen < 20)
400 continue;
401 devfn = (reg[0] >> 8) & 0xff;
1beb6a7d 402
4267292b
PM		 403 /* create a new pci_dev for this device */
404 dev = of_create_pci_dev(child, bus, devfn);
405 if (!dev)
406 continue;
1beb6a7d
BH		 407 DBG("dev header type: %x\n", dev->hdr_type);
408
4267292b
PM		 409 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
410 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
411 of_scan_pci_bridge(child, dev);
412 }
413
414 do_bus_setup(bus);
415}
ead83717 416EXPORT_SYMBOL(of_scan_bus);
4267292b 417
ead83717
JR		 418void __devinit of_scan_pci_bridge(struct device_node *node,
419 struct pci_dev *dev)
4267292b
PM		 420{
421 struct pci_bus *bus;
a7f67bdf 422 const u32 *busrange, *ranges;
4267292b
PM		 423 int len, i, mode;
424 struct resource *res;
425 unsigned int flags;
426 u64 size;
427
1beb6a7d
BH		 428 DBG("of_scan_pci_bridge(%s)\n", node->full_name);
429
4267292b 430 /* parse bus-range property */
a7f67bdf 431 busrange = get_property(node, "bus-range", &len);
4267292b 432 if (busrange == NULL || len != 8) {
1beb6a7d 433 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
4267292b
PM		 434 node->full_name);
435 return;
436 }
a7f67bdf 437 ranges = get_property(node, "ranges", &len);
4267292b 438 if (ranges == NULL) {
1beb6a7d 439 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
4267292b
PM		 440 node->full_name);
441 return;
442 }
443
444 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
445 if (!bus) {
446 printk(KERN_ERR "Failed to create pci bus for %s\n",
447 node->full_name);
448 return;
449 }
450
451 bus->primary = dev->bus->number;
452 bus->subordinate = busrange[1];
453 bus->bridge_ctl = 0;
454 bus->sysdata = node;
455
456 /* parse ranges property */
457 /* PCI #address-cells == 3 and #size-cells == 2 always */
458 res = &dev->resource[PCI_BRIDGE_RESOURCES];
459 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
460 res->flags = 0;
461 bus->resource[i] = res;
462 ++res;
463 }
464 i = 1;
465 for (; len >= 32; len -= 32, ranges += 8) {
466 flags = pci_parse_of_flags(ranges[0]);
467 size = GET_64BIT(ranges, 6);
468 if (flags == 0 || size == 0)
469 continue;
470 if (flags & IORESOURCE_IO) {
471 res = bus->resource[0];
472 if (res->flags) {
473 printk(KERN_ERR "PCI: ignoring extra I/O range"
474 " for bridge %s\n", node->full_name);
475 continue;
476 }
477 } else {
478 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
479 printk(KERN_ERR "PCI: too many memory ranges"
480 " for bridge %s\n", node->full_name);
481 continue;
482 }
483 res = bus->resource[i];
484 ++i;
485 }
486 res->start = GET_64BIT(ranges, 1);
487 res->end = res->start + size - 1;
488 res->flags = flags;
489 fixup_resource(res, dev);
490 }
491 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
492 bus->number);
1beb6a7d 493 DBG(" bus name: %s\n", bus->name);
4267292b
PM		 494
495 mode = PCI_PROBE_NORMAL;
496 if (ppc_md.pci_probe_mode)
497 mode = ppc_md.pci_probe_mode(bus);
1beb6a7d
BH		 498 DBG(" probe mode: %d\n", mode);
499
4267292b
PM		 500 if (mode == PCI_PROBE_DEVTREE)
501 of_scan_bus(node, bus);
502 else if (mode == PCI_PROBE_NORMAL)
503 pci_scan_child_bus(bus);
504}
ead83717 505EXPORT_SYMBOL(of_scan_pci_bridge);
4267292b 506
ead83717 507void __devinit scan_phb(struct pci_controller *hose)
4267292b
PM		 508{
509 struct pci_bus *bus;
510 struct device_node *node = hose->arch_data;
511 int i, mode;
512 struct resource *res;
513
1beb6a7d
BH		 514 DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
515
4267292b
PM		 516 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
517 if (bus == NULL) {
518 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
519 hose->global_number);
520 return;
521 }
522 bus->secondary = hose->first_busno;
523 hose->bus = bus;
524
525 bus->resource[0] = res = &hose->io_resource;
526 if (res->flags && request_resource(&ioport_resource, res))
527 printk(KERN_ERR "Failed to request PCI IO region "
528 "on PCI domain %04x\n", hose->global_number);
529
530 for (i = 0; i < 3; ++i) {
531 res = &hose->mem_resources[i];
532 bus->resource[i+1] = res;
533 if (res->flags && request_resource(&iomem_resource, res))
534 printk(KERN_ERR "Failed to request PCI memory region "
535 "on PCI domain %04x\n", hose->global_number);
536 }
537
538 mode = PCI_PROBE_NORMAL;
99a565ba 539
1beb6a7d 540 if (node && ppc_md.pci_probe_mode)
4267292b 541 mode = ppc_md.pci_probe_mode(bus);
1beb6a7d 542 DBG(" probe mode: %d\n", mode);
4267292b
PM		 543 if (mode == PCI_PROBE_DEVTREE) {
544 bus->subordinate = hose->last_busno;
545 of_scan_bus(node, bus);
546 }
99a565ba 547
4267292b
PM		 548 if (mode == PCI_PROBE_NORMAL)
549 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
4267292b
PM		 550}
551
1da177e4
LT		 552static int __init pcibios_init(void)
553{
554 struct pci_controller *hose, *tmp;
1da177e4
LT		 555
556 /* For now, override phys_mem_access_prot. If we need it,
557 * later, we may move that initialization to each ppc_md
558 */
559 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
560
eecba334
SR		 561 if (firmware_has_feature(FW_FEATURE_ISERIES))
562 iSeries_pcibios_init();
1da177e4 563
e884e9c5 564 printk(KERN_DEBUG "PCI: Probing PCI hardware\n");
1da177e4
LT		 565
566 /* Scan all of the recorded PCI controllers. */
92eb4602 567 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
4267292b 568 scan_phb(hose);
92eb4602
JR		 569 pci_bus_add_devices(hose->bus);
570 }
1da177e4 571
eecba334
SR		 572 if (!firmware_has_feature(FW_FEATURE_ISERIES)) {
573 if (pci_probe_only)
574 pcibios_claim_of_setup();
575 else
576 /* FIXME: `else' will be removed when
577 pci_assign_unassigned_resources() is able to work
578 correctly with [partially] allocated PCI tree. */
579 pci_assign_unassigned_resources();
580 }
1da177e4
LT		 581
582 /* Call machine dependent final fixup */
583 if (ppc_md.pcibios_fixup)
584 ppc_md.pcibios_fixup();
585
586 /* Cache the location of the ISA bridge (if we have one) */
587 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
588 if (ppc64_isabridge_dev != NULL)
e884e9c5 589 printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
1da177e4 590
eecba334
SR		 591 if (!firmware_has_feature(FW_FEATURE_ISERIES))
592 /* map in PCI I/O space */
593 phbs_remap_io();
0f34f490 594
e884e9c5 595 printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
1da177e4
LT		 596
597 return 0;
598}
599
600subsys_initcall(pcibios_init);
601
602char __init *pcibios_setup(char *str)
603{
604 return str;
605}
606
607int pcibios_enable_device(struct pci_dev *dev, int mask)
608{
609 u16 cmd, oldcmd;
610 int i;
611
612 pci_read_config_word(dev, PCI_COMMAND, &cmd);
613 oldcmd = cmd;
614
615 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
616 struct resource *res = &dev->resource[i];
617
618 /* Only set up the requested stuff */
619 if (!(mask & (1<<i)))
620 continue;
621
622 if (res->flags & IORESOURCE_IO)
623 cmd |= PCI_COMMAND_IO;
624 if (res->flags & IORESOURCE_MEM)
625 cmd |= PCI_COMMAND_MEMORY;
626 }
627
628 if (cmd != oldcmd) {
629 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
630 pci_name(dev), cmd);
631 /* Enable the appropriate bits in the PCI command register. */
632 pci_write_config_word(dev, PCI_COMMAND, cmd);
633 }
634 return 0;
635}
636
637/*
638 * Return the domain number for this bus.
639 */
640int pci_domain_nr(struct pci_bus *bus)
641{
eecba334
SR		 642 if (firmware_has_feature(FW_FEATURE_ISERIES))
643 return 0;
644 else {
645 struct pci_controller *hose = pci_bus_to_host(bus);
1da177e4 646
eecba334
SR		 647 return hose->global_number;
648 }
1da177e4
LT		 649}
650
651EXPORT_SYMBOL(pci_domain_nr);
652
653/* Decide whether to display the domain number in /proc */
654int pci_proc_domain(struct pci_bus *bus)
655{
eecba334
SR		 656 if (firmware_has_feature(FW_FEATURE_ISERIES))
657 return 0;
658 else {
659 struct pci_controller *hose = pci_bus_to_host(bus);
660 return hose->buid;
661 }
1da177e4
LT		 662}
663
664/*
665 * Platform support for /proc/bus/pci/X/Y mmap()s,
666 * modelled on the sparc64 implementation by Dave Miller.
667 * -- paulus.
668 */
669
670/*
671 * Adjust vm_pgoff of VMA such that it is the physical page offset
672 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
673 *
674 * Basically, the user finds the base address for his device which he wishes
675 * to mmap. They read the 32-bit value from the config space base register,
676 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
677 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
678 *
679 * Returns negative error code on failure, zero on success.
680 */
681static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
682 unsigned long *offset,
683 enum pci_mmap_state mmap_state)
684{
685 struct pci_controller *hose = pci_bus_to_host(dev->bus);
686 unsigned long io_offset = 0;
687 int i, res_bit;
688
689 if (hose == 0)
690 return NULL; /* should never happen */
691
692 /* If memory, add on the PCI bridge address offset */
693 if (mmap_state == pci_mmap_mem) {
694 *offset += hose->pci_mem_offset;
695 res_bit = IORESOURCE_MEM;
696 } else {
2311b1f2 697 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4
LT		 698 *offset += io_offset;
699 res_bit = IORESOURCE_IO;
700 }
701
702 /*
703 * Check that the offset requested corresponds to one of the
704 * resources of the device.
705 */
706 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
707 struct resource *rp = &dev->resource[i];
708 int flags = rp->flags;
709
710 /* treat ROM as memory (should be already) */
711 if (i == PCI_ROM_RESOURCE)
712 flags |= IORESOURCE_MEM;
713
714 /* Active and same type? */
715 if ((flags & res_bit) == 0)
716 continue;
717
718 /* In the range of this resource? */
719 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
720 continue;
721
722 /* found it! construct the final physical address */
723 if (mmap_state == pci_mmap_io)
2311b1f2 724 *offset += hose->io_base_phys - io_offset;
1da177e4
LT		 725 return rp;
726 }
727
728 return NULL;
729}
730
731/*
732 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
733 * device mapping.
734 */
735static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
736 pgprot_t protection,
737 enum pci_mmap_state mmap_state,
738 int write_combine)
739{
740 unsigned long prot = pgprot_val(protection);
741
742 /* Write combine is always 0 on non-memory space mappings. On
743 * memory space, if the user didn't pass 1, we check for a
744 * "prefetchable" resource. This is a bit hackish, but we use
745 * this to workaround the inability of /sysfs to provide a write
746 * combine bit
747 */
748 if (mmap_state != pci_mmap_mem)
749 write_combine = 0;
750 else if (write_combine == 0) {
751 if (rp->flags & IORESOURCE_PREFETCH)
752 write_combine = 1;
753 }
754
755 /* XXX would be nice to have a way to ask for write-through */
756 prot |= _PAGE_NO_CACHE;
757 if (write_combine)
758 prot &= ~_PAGE_GUARDED;
759 else
760 prot |= _PAGE_GUARDED;
761
e884e9c5 762 printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
1da177e4
LT		 763 prot);
764
765 return __pgprot(prot);
766}
767
768/*
769 * This one is used by /dev/mem and fbdev who have no clue about the
770 * PCI device, it tries to find the PCI device first and calls the
771 * above routine
772 */
773pgprot_t pci_phys_mem_access_prot(struct file *file,
8b150478 774 unsigned long pfn,
1da177e4
LT		 775 unsigned long size,
776 pgprot_t protection)
777{
778 struct pci_dev *pdev = NULL;
779 struct resource *found = NULL;
780 unsigned long prot = pgprot_val(protection);
8b150478 781 unsigned long offset = pfn << PAGE_SHIFT;
1da177e4
LT		 782 int i;
783
8b150478 784 if (page_is_ram(pfn))
1f8d419e 785 return __pgprot(prot);
1da177e4
LT		 786
787 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
788
789 for_each_pci_dev(pdev) {
790 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
791 struct resource *rp = &pdev->resource[i];
792 int flags = rp->flags;
793
794 /* Active and same type? */
795 if ((flags & IORESOURCE_MEM) == 0)
796 continue;
797 /* In the range of this resource? */
798 if (offset < (rp->start & PAGE_MASK) ||
799 offset > rp->end)
800 continue;
801 found = rp;
802 break;
803 }
804 if (found)
805 break;
806 }
807 if (found) {
808 if (found->flags & IORESOURCE_PREFETCH)
809 prot &= ~_PAGE_GUARDED;
810 pci_dev_put(pdev);
811 }
812
813 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
814
815 return __pgprot(prot);
816}
817
818
819/*
820 * Perform the actual remap of the pages for a PCI device mapping, as
821 * appropriate for this architecture. The region in the process to map
822 * is described by vm_start and vm_end members of VMA, the base physical
823 * address is found in vm_pgoff.
824 * The pci device structure is provided so that architectures may make mapping
825 * decisions on a per-device or per-bus basis.
826 *
827 * Returns a negative error code on failure, zero on success.
828 */
829int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1beb6a7d 830 enum pci_mmap_state mmap_state, int write_combine)
1da177e4
LT		 831{
832 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
833 struct resource *rp;
834 int ret;
835
836 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
837 if (rp == NULL)
838 return -EINVAL;
839
840 vma->vm_pgoff = offset >> PAGE_SHIFT;
1da177e4
LT		 841 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
842 vma->vm_page_prot,
843 mmap_state, write_combine);
844
845 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
846 vma->vm_end - vma->vm_start, vma->vm_page_prot);
847
848 return ret;
849}
850
efbd3869
SR		 851static ssize_t pci_show_devspec(struct device *dev,
852 struct device_attribute *attr, char *buf)
1da177e4
LT		 853{
854 struct pci_dev *pdev;
855 struct device_node *np;
856
857 pdev = to_pci_dev (dev);
858 np = pci_device_to_OF_node(pdev);
859 if (np == NULL || np->full_name == NULL)
860 return 0;
861 return sprintf(buf, "%s", np->full_name);
862}
863static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
1da177e4
LT		 864
865void pcibios_add_platform_entries(struct pci_dev *pdev)
866{
1da177e4 867 device_create_file(&pdev->dev, &dev_attr_devspec);
1da177e4
LT		 868}
869
1da177e4
LT		 870#define ISA_SPACE_MASK 0x1
871#define ISA_SPACE_IO 0x1
872
873static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
874 unsigned long phb_io_base_phys,
875 void __iomem * phb_io_base_virt)
876{
cc5d0189
BH		 877 /* Remove these asap */
878
879 struct pci_address {
880 u32 a_hi;
881 u32 a_mid;
882 u32 a_lo;
883 };
884
885 struct isa_address {
886 u32 a_hi;
887 u32 a_lo;
888 };
889
890 struct isa_range {
891 struct isa_address isa_addr;
892 struct pci_address pci_addr;
893 unsigned int size;
894 };
895
a7f67bdf 896 const struct isa_range *range;
1da177e4
LT		 897 unsigned long pci_addr;
898 unsigned int isa_addr;
899 unsigned int size;
900 int rlen = 0;
901
a7f67bdf 902 range = get_property(isa_node, "ranges", &rlen);
1da177e4
LT		 903 if (range == NULL || (rlen < sizeof(struct isa_range))) {
904 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
905 "mapping 64k\n");
dfbacdc1
BH		 906 __ioremap_explicit(phb_io_base_phys,
907 (unsigned long)phb_io_base_virt,
908 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 909 return;
910 }
911
912 /* From "ISA Binding to 1275"
913 * The ranges property is laid out as an array of elements,
914 * each of which comprises:
915 * cells 0 - 1: an ISA address
916 * cells 2 - 4: a PCI address
917 * (size depending on dev->n_addr_cells)
918 * cell 5: the size of the range
919 */
920 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
921 isa_addr = range->isa_addr.a_lo;
922 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
923 range->pci_addr.a_lo;
924
925 /* Assume these are both zero */
926 if ((pci_addr != 0) || (isa_addr != 0)) {
927 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
928 __FUNCTION__);
929 return;
930 }
931
932 size = PAGE_ALIGN(range->size);
933
934 __ioremap_explicit(phb_io_base_phys,
935 (unsigned long) phb_io_base_virt,
dfbacdc1 936 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 937 }
938}
939
940void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
f7abbc19 941 struct device_node *dev, int prim)
1da177e4 942{
a7f67bdf
JK		 943 const unsigned int *ranges;
944 unsigned int pci_space;
1da177e4
LT		 945 unsigned long size;
946 int rlen = 0;
947 int memno = 0;
948 struct resource *res;
949 int np, na = prom_n_addr_cells(dev);
950 unsigned long pci_addr, cpu_phys_addr;
951
952 np = na + 5;
953
954 /* From "PCI Binding to 1275"
955 * The ranges property is laid out as an array of elements,
956 * each of which comprises:
957 * cells 0 - 2: a PCI address
958 * cells 3 or 3+4: a CPU physical address
959 * (size depending on dev->n_addr_cells)
960 * cells 4+5 or 5+6: the size of the range
961 */
a7f67bdf 962 ranges = get_property(dev, "ranges", &rlen);
b5166cc2
BH		 963 if (ranges == NULL)
964 return;
965 hose->io_base_phys = 0;
1da177e4
LT		 966 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
967 res = NULL;
f7abbc19
PM		 968 pci_space = ranges[0];
969 pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2];
1da177e4
LT		 970
971 cpu_phys_addr = ranges[3];
f7abbc19
PM		 972 if (na >= 2)
973 cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4];
1da177e4 974
f7abbc19
PM		 975 size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4];
976 ranges += np;
1da177e4
LT		 977 if (size == 0)
978 continue;
f7abbc19
PM		 979
980 /* Now consume following elements while they are contiguous */
981 while (rlen >= np * sizeof(unsigned int)) {
982 unsigned long addr, phys;
983
984 if (ranges[0] != pci_space)
985 break;
986 addr = ((unsigned long)ranges[1] << 32) | ranges[2];
987 phys = ranges[3];
988 if (na >= 2)
989 phys = (phys << 32) | ranges[4];
990 if (addr != pci_addr + size ||
991 phys != cpu_phys_addr + size)
992 break;
993
994 size += ((unsigned long)ranges[na+3] << 32)
995 | ranges[na+4];
996 ranges += np;
997 rlen -= np * sizeof(unsigned int);
998 }
999
1000 switch ((pci_space >> 24) & 0x3) {
1da177e4
LT		 1001 case 1: /* I/O space */
1002 hose->io_base_phys = cpu_phys_addr;
1003 hose->pci_io_size = size;
1004
1005 res = &hose->io_resource;
1006 res->flags = IORESOURCE_IO;
1007 res->start = pci_addr;
1008 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
1009 res->start, res->start + size - 1);
1010 break;
1011 case 2: /* memory space */
1012 memno = 0;
1013 while (memno < 3 && hose->mem_resources[memno].flags)
1014 ++memno;
1015
1016 if (memno == 0)
1017 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
1018 if (memno < 3) {
1019 res = &hose->mem_resources[memno];
1020 res->flags = IORESOURCE_MEM;
1021 res->start = cpu_phys_addr;
1022 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
1023 res->start, res->start + size - 1);
1024 }
1025 break;
1026 }
1027 if (res != NULL) {
1028 res->name = dev->full_name;
1029 res->end = res->start + size - 1;
1030 res->parent = NULL;
1031 res->sibling = NULL;
1032 res->child = NULL;
1033 }
1da177e4
LT		 1034 }
1035}
1036
1037void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
1038{
1039 unsigned long size = hose->pci_io_size;
1040 unsigned long io_virt_offset;
1041 struct resource *res;
1042 struct device_node *isa_dn;
1043
1044 hose->io_base_virt = reserve_phb_iospace(size);
1045 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1046 hose->global_number, hose->io_base_phys,
1047 (unsigned long) hose->io_base_virt);
1048
1049 if (primary) {
1050 pci_io_base = (unsigned long)hose->io_base_virt;
1051 isa_dn = of_find_node_by_type(NULL, "isa");
1052 if (isa_dn) {
1053 isa_io_base = pci_io_base;
1054 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
1055 hose->io_base_virt);
1056 of_node_put(isa_dn);
1da177e4
LT		 1057 }
1058 }
1059
1060 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1061 res = &hose->io_resource;
1062 res->start += io_virt_offset;
1063 res->end += io_virt_offset;
1064}
1065
1066void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
1067 int primary)
1068{
1069 unsigned long size = hose->pci_io_size;
1070 unsigned long io_virt_offset;
1071 struct resource *res;
1072
1073 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
dfbacdc1 1074 _PAGE_NO_CACHE | _PAGE_GUARDED);
1da177e4
LT		 1075 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
1076 hose->global_number, hose->io_base_phys,
1077 (unsigned long) hose->io_base_virt);
1078
1079 if (primary)
1080 pci_io_base = (unsigned long)hose->io_base_virt;
1081
1082 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1083 res = &hose->io_resource;
1084 res->start += io_virt_offset;
1085 res->end += io_virt_offset;
1086}
1087
1088
1089static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1090 unsigned long *start_virt, unsigned long *size)
1091{
1092 struct pci_controller *hose = pci_bus_to_host(bus);
1093 struct pci_bus_region region;
1094 struct resource *res;
1095
1096 if (bus->self) {
1097 res = bus->resource[0];
1098 pcibios_resource_to_bus(bus->self, &region, res);
1099 *start_phys = hose->io_base_phys + region.start;
1100 *start_virt = (unsigned long) hose->io_base_virt +
1101 region.start;
1102 if (region.end > region.start)
1103 *size = region.end - region.start + 1;
1104 else {
1105 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1106 __FUNCTION__, region.start, region.end);
1107 return 1;
1108 }
1109
1110 } else {
1111 /* Root Bus */
1112 res = &hose->io_resource;
1113 *start_phys = hose->io_base_phys;
1114 *start_virt = (unsigned long) hose->io_base_virt;
1115 if (res->end > res->start)
1116 *size = res->end - res->start + 1;
1117 else {
1118 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1119 __FUNCTION__, res->start, res->end);
1120 return 1;
1121 }
1122 }
1123
1124 return 0;
1125}
1126
1127int unmap_bus_range(struct pci_bus *bus)
1128{
1129 unsigned long start_phys;
1130 unsigned long start_virt;
1131 unsigned long size;
1132
1133 if (!bus) {
1134 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1135 return 1;
1136 }
1137
1138 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1139 return 1;
1140 if (iounmap_explicit((void __iomem *) start_virt, size))
1141 return 1;
1142
1143 return 0;
1144}
1145EXPORT_SYMBOL(unmap_bus_range);
1146
1147int remap_bus_range(struct pci_bus *bus)
1148{
1149 unsigned long start_phys;
1150 unsigned long start_virt;
1151 unsigned long size;
1152
1153 if (!bus) {
1154 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1155 return 1;
1156 }
1157
1158
1159 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1160 return 1;
b5166cc2
BH		 1161 if (start_phys == 0)
1162 return 1;
e884e9c5 1163 printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
dfbacdc1
BH		 1164 if (__ioremap_explicit(start_phys, start_virt, size,
1165 _PAGE_NO_CACHE | _PAGE_GUARDED))
1da177e4
LT		 1166 return 1;
1167
1168 return 0;
1169}
1170EXPORT_SYMBOL(remap_bus_range);
1171
9623b5d3 1172static void phbs_remap_io(void)
1da177e4
LT		 1173{
1174 struct pci_controller *hose, *tmp;
1175
1176 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1177 remap_bus_range(hose->bus);
1178}
1179
4267292b
PM		 1180static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1181{
1182 struct pci_controller *hose = pci_bus_to_host(dev->bus);
c256f4b9 1183 unsigned long offset;
1da177e4 1184
4267292b
PM		 1185 if (res->flags & IORESOURCE_IO) {
1186 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1da177e4 1187
c256f4b9
AB		 1188 res->start += offset;
1189 res->end += offset;
4267292b
PM		 1190 } else if (res->flags & IORESOURCE_MEM) {
1191 res->start += hose->pci_mem_offset;
1192 res->end += hose->pci_mem_offset;
1193 }
1194}
1da177e4
LT		 1195
1196void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
4267292b 1197 struct pci_bus *bus)
1da177e4
LT		 1198{
1199 /* Update device resources. */
1da177e4
LT		 1200 int i;
1201
4267292b
PM		 1202 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1203 if (dev->resource[i].flags)
1204 fixup_resource(&dev->resource[i], dev);
1da177e4
LT		 1205}
1206EXPORT_SYMBOL(pcibios_fixup_device_resources);
1207
463ce0e1 1208
4267292b 1209static void __devinit do_bus_setup(struct pci_bus *bus)
1da177e4 1210{
4267292b 1211 struct pci_dev *dev;
1da177e4 1212
4267292b 1213 ppc_md.iommu_bus_setup(bus);
1da177e4 1214
4267292b
PM		 1215 list_for_each_entry(dev, &bus->devices, bus_list)
1216 ppc_md.iommu_dev_setup(dev);
1da177e4 1217
f90bb153
BH		 1218 /* Read default IRQs and fixup if necessary */
1219 list_for_each_entry(dev, &bus->devices, bus_list) {
1220 pci_read_irq_line(dev);
1221 if (ppc_md.pci_irq_fixup)
1222 ppc_md.pci_irq_fixup(dev);
1223 }
4267292b 1224}
1da177e4 1225
4267292b
PM		 1226void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1227{
1228 struct pci_dev *dev = bus->self;
1229
1230 if (dev && pci_probe_only &&
1231 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1da177e4
LT		 1232 /* This is a subordinate bridge */
1233
1234 pci_read_bridge_bases(bus);
1235 pcibios_fixup_device_resources(dev, bus);
1236 }
1237
4267292b 1238 do_bus_setup(bus);
dad32bbf 1239
1da177e4
LT		 1240 if (!pci_probe_only)
1241 return;
1242
4267292b 1243 list_for_each_entry(dev, &bus->devices, bus_list)
1da177e4
LT		 1244 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1245 pcibios_fixup_device_resources(dev, bus);
1da177e4
LT		 1246}
1247EXPORT_SYMBOL(pcibios_fixup_bus);
1248
1249/*
1250 * Reads the interrupt pin to determine if interrupt is use by card.
1251 * If the interrupt is used, then gets the interrupt line from the
1252 * openfirmware and sets it in the pci_dev and pci_config line.
1253 */
1254int pci_read_irq_line(struct pci_dev *pci_dev)
1255{
0ebfff14
BH		 1256 struct of_irq oirq;
1257 unsigned int virq;
1da177e4 1258
0ebfff14 1259 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1da177e4 1260
006b64de
BH		 1261#ifdef DEBUG
1262 memset(&oirq, 0xff, sizeof(oirq));
1263#endif
6e99e458 1264 /* Try to get a mapping from the device-tree */
0ebfff14 1265 if (of_irq_map_pci(pci_dev, &oirq)) {
6e99e458
BH		 1266 u8 line, pin;
1267
1268 /* If that fails, lets fallback to what is in the config
1269 * space and map that through the default controller. We
1270 * also set the type to level low since that's what PCI
1271 * interrupts are. If your platform does differently, then
1272 * either provide a proper interrupt tree or don't use this
1273 * function.
1274 */
1275 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
1276 return -1;
1277 if (pin == 0)
1278 return -1;
1279 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
1280 line == 0xff) {
1281 return -1;
1282 }
1283 DBG(" -> no map ! Using irq line %d from PCI config\n", line);
1da177e4 1284
6e99e458
BH		 1285 virq = irq_create_mapping(NULL, line);
1286 if (virq != NO_IRQ)
1287 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1288 } else {
006b64de
BH		 1289 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1290 oirq.size, oirq.specifier[0], oirq.specifier[1],
1291 oirq.controller->full_name);
1da177e4 1292
6e99e458
BH		 1293 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1294 oirq.size);
1295 }
0ebfff14
BH		 1296 if(virq == NO_IRQ) {
1297 DBG(" -> failed to map !\n");
1298 return -1;
1299 }
006b64de
BH		 1300
1301 DBG(" -> mapped to linux irq %d\n", virq);
1302
0ebfff14
BH		 1303 pci_dev->irq = virq;
1304 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1da177e4
LT		 1305
1306 return 0;
1307}
1308EXPORT_SYMBOL(pci_read_irq_line);
1309
2311b1f2
ME		 1310void pci_resource_to_user(const struct pci_dev *dev, int bar,
1311 const struct resource *rsrc,
1312 u64 *start, u64 *end)
1313{
1314 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1315 unsigned long offset = 0;
1316
1317 if (hose == NULL)
1318 return;
1319
1320 if (rsrc->flags & IORESOURCE_IO)
1321 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1322 hose->io_base_phys;
1323
1324 *start = rsrc->start + offset;
1325 *end = rsrc->end + offset;
1326}
1327
463ce0e1
BH		 1328struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
1329{
1330 if (!have_of)
1331 return NULL;
1332 while(node) {
1333 struct pci_controller *hose, *tmp;
1334 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1335 if (hose->arch_data == node)
1336 return hose;
1337 node = node->parent;
1338 }
1339 return NULL;
1340}
1341
f2c4583a 1342unsigned long pci_address_to_pio(phys_addr_t address)
d4e4b352
SR		 1343{
1344 struct pci_controller *hose, *tmp;
1345
1346 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1347 if (address >= hose->io_base_phys &&
f2c4583a
BH		 1348 address < (hose->io_base_phys + hose->pci_io_size)) {
1349 unsigned long base =
1350 (unsigned long)hose->io_base_virt - pci_io_base;
1351 return base + (address - hose->io_base_phys);
1352 }
d4e4b352
SR		 1353 }
1354 return (unsigned int)-1;
1355}
1356EXPORT_SYMBOL_GPL(pci_address_to_pio);
1357
b2ad7b5e
PM		 1358
1359#define IOBASE_BRIDGE_NUMBER 0
1360#define IOBASE_MEMORY 1
1361#define IOBASE_IO 2
1362#define IOBASE_ISA_IO 3
1363#define IOBASE_ISA_MEM 4
1364
1365long sys_pciconfig_iobase(long which, unsigned long in_bus,
1366 unsigned long in_devfn)
1367{
1368 struct pci_controller* hose;
1369 struct list_head *ln;
1370 struct pci_bus *bus = NULL;
1371 struct device_node *hose_node;
1372
1373 /* Argh ! Please forgive me for that hack, but that's the
1374 * simplest way to get existing XFree to not lockup on some
1375 * G5 machines... So when something asks for bus 0 io base
1376 * (bus 0 is HT root), we return the AGP one instead.
1377 */
799d6046 1378 if (machine_is_compatible("MacRISC4"))
b2ad7b5e
PM		 1379 if (in_bus == 0)
1380 in_bus = 0xf0;
b2ad7b5e
PM		 1381
1382 /* That syscall isn't quite compatible with PCI domains, but it's
1383 * used on pre-domains setup. We return the first match
1384 */
1385
1386 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1387 bus = pci_bus_b(ln);
1388 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1389 break;
1390 bus = NULL;
1391 }
1392 if (bus == NULL || bus->sysdata == NULL)
1393 return -ENODEV;
1394
1395 hose_node = (struct device_node *)bus->sysdata;
1396 hose = PCI_DN(hose_node)->phb;
1397
1398 switch (which) {
1399 case IOBASE_BRIDGE_NUMBER:
1400 return (long)hose->first_busno;
1401 case IOBASE_MEMORY:
1402 return (long)hose->pci_mem_offset;
1403 case IOBASE_IO:
1404 return (long)hose->io_base_phys;
1405 case IOBASE_ISA_IO:
1406 return (long)isa_io_base;
1407 case IOBASE_ISA_MEM:
1408 return -EINVAL;
1409 }
1410
1411 return -EOPNOTSUPP;
1412}
357518fa
AB		 1413
1414#ifdef CONFIG_NUMA
1415int pcibus_to_node(struct pci_bus *bus)
1416{
1417 struct pci_controller *phb = pci_bus_to_host(bus);
1418 return phb->node;
1419}
1420EXPORT_SYMBOL(pcibus_to_node);
1421#endif
Linux kernel - Deliverables
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