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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/pci.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/list.h> | |
b2ad7b5e | 23 | #include <linux/syscalls.h> |
6e99e458 | 24 | #include <linux/irq.h> |
3d5134ee | 25 | #include <linux/vmalloc.h> |
1da177e4 LT |
26 | |
27 | #include <asm/processor.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/prom.h> | |
30 | #include <asm/pci-bridge.h> | |
31 | #include <asm/byteorder.h> | |
1da177e4 | 32 | #include <asm/machdep.h> |
d387899f | 33 | #include <asm/ppc-pci.h> |
1da177e4 | 34 | |
1da177e4 | 35 | unsigned long pci_probe_only = 1; |
1da177e4 | 36 | |
1da177e4 LT |
37 | /* pci_io_base -- the base address from which io bars are offsets. |
38 | * This is the lowest I/O base address (so bar values are always positive), | |
39 | * and it *must* be the start of ISA space if an ISA bus exists because | |
3d5134ee BH |
40 | * ISA drivers use hard coded offsets. If no ISA bus exists nothing |
41 | * is mapped on the first 64K of IO space | |
1da177e4 | 42 | */ |
3d5134ee | 43 | unsigned long pci_io_base = ISA_IO_BASE; |
1da177e4 LT |
44 | EXPORT_SYMBOL(pci_io_base); |
45 | ||
1da177e4 LT |
46 | LIST_HEAD(hose_list); |
47 | ||
1da177e4 LT |
48 | static void fixup_broken_pcnet32(struct pci_dev* dev) |
49 | { | |
50 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
51 | dev->vendor = PCI_VENDOR_ID_AMD; | |
52 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
53 | } |
54 | } | |
55 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
56 | ||
1da177e4 | 57 | |
4267292b PM |
58 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) |
59 | { | |
a7f67bdf | 60 | const u32 *prop; |
4267292b PM |
61 | int len; |
62 | ||
e2eb6392 | 63 | prop = of_get_property(np, name, &len); |
4267292b PM |
64 | if (prop && len >= 4) |
65 | return *prop; | |
66 | return def; | |
67 | } | |
68 | ||
69 | static unsigned int pci_parse_of_flags(u32 addr0) | |
70 | { | |
71 | unsigned int flags = 0; | |
72 | ||
73 | if (addr0 & 0x02000000) { | |
d79e743e PM |
74 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
75 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
76 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
4267292b | 77 | if (addr0 & 0x40000000) |
d79e743e PM |
78 | flags |= IORESOURCE_PREFETCH |
79 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
4267292b | 80 | } else if (addr0 & 0x01000000) |
d79e743e | 81 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
4267292b PM |
82 | return flags; |
83 | } | |
84 | ||
4267292b PM |
85 | |
86 | static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) | |
87 | { | |
88 | u64 base, size; | |
89 | unsigned int flags; | |
90 | struct resource *res; | |
a7f67bdf JK |
91 | const u32 *addrs; |
92 | u32 i; | |
4267292b PM |
93 | int proplen; |
94 | ||
e2eb6392 | 95 | addrs = of_get_property(node, "assigned-addresses", &proplen); |
4267292b PM |
96 | if (!addrs) |
97 | return; | |
b0494bc8 | 98 | pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs); |
4267292b PM |
99 | for (; proplen >= 20; proplen -= 20, addrs += 5) { |
100 | flags = pci_parse_of_flags(addrs[0]); | |
101 | if (!flags) | |
102 | continue; | |
327e22df JL |
103 | base = of_read_number(&addrs[1], 2); |
104 | size = of_read_number(&addrs[3], 2); | |
4267292b PM |
105 | if (!size) |
106 | continue; | |
107 | i = addrs[0] & 0xff; | |
b0494bc8 BH |
108 | pr_debug(" base: %llx, size: %llx, i: %x\n", |
109 | (unsigned long long)base, | |
110 | (unsigned long long)size, i); | |
1beb6a7d | 111 | |
4267292b PM |
112 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { |
113 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
114 | } else if (i == dev->rom_base_reg) { | |
115 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
116 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
117 | } else { | |
118 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
119 | continue; | |
120 | } | |
121 | res->start = base; | |
122 | res->end = base + size - 1; | |
123 | res->flags = flags; | |
124 | res->name = pci_name(dev); | |
4267292b PM |
125 | } |
126 | } | |
127 | ||
ead83717 JR |
128 | struct pci_dev *of_create_pci_dev(struct device_node *node, |
129 | struct pci_bus *bus, int devfn) | |
4267292b PM |
130 | { |
131 | struct pci_dev *dev; | |
132 | const char *type; | |
133 | ||
bab41e9b | 134 | dev = alloc_pci_dev(); |
4267292b PM |
135 | if (!dev) |
136 | return NULL; | |
e2eb6392 | 137 | type = of_get_property(node, "device_type", NULL); |
4267292b PM |
138 | if (type == NULL) |
139 | type = ""; | |
140 | ||
b0494bc8 | 141 | pr_debug(" create device, devfn: %x, type: %s\n", devfn, type); |
1beb6a7d | 142 | |
4267292b PM |
143 | dev->bus = bus; |
144 | dev->sysdata = node; | |
145 | dev->dev.parent = bus->bridge; | |
146 | dev->dev.bus = &pci_bus_type; | |
147 | dev->devfn = devfn; | |
148 | dev->multifunction = 0; /* maybe a lie? */ | |
149 | ||
150 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); | |
151 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
152 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
153 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
154 | ||
9d17a5c6 | 155 | dev->cfg_size = pci_cfg_space_size(dev); |
4267292b | 156 | |
420b5eea | 157 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), |
4267292b PM |
158 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
159 | dev->class = get_int_prop(node, "class-code", 0); | |
b8a3a521 | 160 | dev->revision = get_int_prop(node, "revision-id", 0); |
4267292b | 161 | |
b0494bc8 BH |
162 | pr_debug(" class: 0x%x\n", dev->class); |
163 | pr_debug(" revision: 0x%x\n", dev->revision); | |
1beb6a7d | 164 | |
4267292b | 165 | dev->current_state = 4; /* unknown power state */ |
bb63ab13 | 166 | dev->error_state = pci_channel_io_normal; |
8f2ea1fd | 167 | dev->dma_mask = 0xffffffff; |
4267292b | 168 | |
bb53bb3d | 169 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
4267292b PM |
170 | /* a PCI-PCI bridge */ |
171 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
172 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
173 | } else if (!strcmp(type, "cardbus")) { | |
174 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
175 | } else { | |
176 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
177 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
0ebfff14 | 178 | /* Maybe do a default OF mapping here */ |
4267292b | 179 | dev->irq = NO_IRQ; |
4267292b PM |
180 | } |
181 | ||
182 | pci_parse_of_addrs(node, dev); | |
183 | ||
b0494bc8 | 184 | pr_debug(" adding to system ...\n"); |
1beb6a7d | 185 | |
4267292b PM |
186 | pci_device_add(dev, bus); |
187 | ||
4267292b PM |
188 | return dev; |
189 | } | |
ead83717 | 190 | EXPORT_SYMBOL(of_create_pci_dev); |
4267292b | 191 | |
ead83717 | 192 | void __devinit of_scan_bus(struct device_node *node, |
bf5e2ba2 | 193 | struct pci_bus *bus) |
4267292b | 194 | { |
85e99b9f | 195 | struct device_node *child; |
a7f67bdf | 196 | const u32 *reg; |
4267292b PM |
197 | int reglen, devfn; |
198 | struct pci_dev *dev; | |
199 | ||
b0494bc8 BH |
200 | pr_debug("of_scan_bus(%s) bus no %d... \n", |
201 | node->full_name, bus->number); | |
1beb6a7d | 202 | |
bf5e2ba2 | 203 | /* Scan direct children */ |
85e99b9f | 204 | for_each_child_of_node(node, child) { |
b0494bc8 | 205 | pr_debug(" * %s\n", child->full_name); |
e2eb6392 | 206 | reg = of_get_property(child, "reg", ®len); |
4267292b PM |
207 | if (reg == NULL || reglen < 20) |
208 | continue; | |
209 | devfn = (reg[0] >> 8) & 0xff; | |
1beb6a7d | 210 | |
4267292b PM |
211 | /* create a new pci_dev for this device */ |
212 | dev = of_create_pci_dev(child, bus, devfn); | |
213 | if (!dev) | |
214 | continue; | |
b0494bc8 | 215 | pr_debug(" dev header type: %x\n", dev->hdr_type); |
bf5e2ba2 BH |
216 | } |
217 | ||
218 | /* Ally all fixups */ | |
219 | pcibios_fixup_of_probed_bus(bus); | |
1beb6a7d | 220 | |
bf5e2ba2 BH |
221 | /* Now scan child busses */ |
222 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
4267292b | 223 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
bf5e2ba2 BH |
224 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) { |
225 | struct device_node *child = pci_device_to_OF_node(dev); | |
226 | if (dev) | |
227 | of_scan_pci_bridge(child, dev); | |
228 | } | |
4267292b | 229 | } |
4267292b | 230 | } |
ead83717 | 231 | EXPORT_SYMBOL(of_scan_bus); |
4267292b | 232 | |
ead83717 | 233 | void __devinit of_scan_pci_bridge(struct device_node *node, |
bf5e2ba2 | 234 | struct pci_dev *dev) |
4267292b PM |
235 | { |
236 | struct pci_bus *bus; | |
a7f67bdf | 237 | const u32 *busrange, *ranges; |
4267292b PM |
238 | int len, i, mode; |
239 | struct resource *res; | |
240 | unsigned int flags; | |
241 | u64 size; | |
242 | ||
b0494bc8 | 243 | pr_debug("of_scan_pci_bridge(%s)\n", node->full_name); |
1beb6a7d | 244 | |
4267292b | 245 | /* parse bus-range property */ |
e2eb6392 | 246 | busrange = of_get_property(node, "bus-range", &len); |
4267292b | 247 | if (busrange == NULL || len != 8) { |
1beb6a7d | 248 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", |
4267292b PM |
249 | node->full_name); |
250 | return; | |
251 | } | |
e2eb6392 | 252 | ranges = of_get_property(node, "ranges", &len); |
4267292b | 253 | if (ranges == NULL) { |
1beb6a7d | 254 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", |
4267292b PM |
255 | node->full_name); |
256 | return; | |
257 | } | |
258 | ||
259 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
260 | if (!bus) { | |
261 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
262 | node->full_name); | |
263 | return; | |
264 | } | |
265 | ||
266 | bus->primary = dev->bus->number; | |
267 | bus->subordinate = busrange[1]; | |
268 | bus->bridge_ctl = 0; | |
269 | bus->sysdata = node; | |
270 | ||
271 | /* parse ranges property */ | |
272 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
273 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
274 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
275 | res->flags = 0; | |
276 | bus->resource[i] = res; | |
277 | ++res; | |
278 | } | |
279 | i = 1; | |
280 | for (; len >= 32; len -= 32, ranges += 8) { | |
281 | flags = pci_parse_of_flags(ranges[0]); | |
327e22df | 282 | size = of_read_number(&ranges[6], 2); |
4267292b PM |
283 | if (flags == 0 || size == 0) |
284 | continue; | |
285 | if (flags & IORESOURCE_IO) { | |
286 | res = bus->resource[0]; | |
287 | if (res->flags) { | |
288 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
289 | " for bridge %s\n", node->full_name); | |
290 | continue; | |
291 | } | |
292 | } else { | |
293 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
294 | printk(KERN_ERR "PCI: too many memory ranges" | |
295 | " for bridge %s\n", node->full_name); | |
296 | continue; | |
297 | } | |
298 | res = bus->resource[i]; | |
299 | ++i; | |
300 | } | |
327e22df | 301 | res->start = of_read_number(&ranges[1], 2); |
4267292b PM |
302 | res->end = res->start + size - 1; |
303 | res->flags = flags; | |
4267292b PM |
304 | } |
305 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
306 | bus->number); | |
b0494bc8 | 307 | pr_debug(" bus name: %s\n", bus->name); |
4267292b PM |
308 | |
309 | mode = PCI_PROBE_NORMAL; | |
310 | if (ppc_md.pci_probe_mode) | |
311 | mode = ppc_md.pci_probe_mode(bus); | |
b0494bc8 | 312 | pr_debug(" probe mode: %d\n", mode); |
1beb6a7d | 313 | |
4267292b PM |
314 | if (mode == PCI_PROBE_DEVTREE) |
315 | of_scan_bus(node, bus); | |
316 | else if (mode == PCI_PROBE_NORMAL) | |
317 | pci_scan_child_bus(bus); | |
318 | } | |
ead83717 | 319 | EXPORT_SYMBOL(of_scan_pci_bridge); |
4267292b | 320 | |
ead83717 | 321 | void __devinit scan_phb(struct pci_controller *hose) |
4267292b PM |
322 | { |
323 | struct pci_bus *bus; | |
44ef3390 | 324 | struct device_node *node = hose->dn; |
53280323 | 325 | int mode; |
4267292b | 326 | |
b0494bc8 BH |
327 | pr_debug("PCI: Scanning PHB %s\n", |
328 | node ? node->full_name : "<NO NAME>"); | |
1beb6a7d | 329 | |
3fd94c6b | 330 | /* Create an empty bus for the toplevel */ |
803d4573 | 331 | bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node); |
4267292b PM |
332 | if (bus == NULL) { |
333 | printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", | |
334 | hose->global_number); | |
335 | return; | |
336 | } | |
337 | bus->secondary = hose->first_busno; | |
338 | hose->bus = bus; | |
339 | ||
3fd94c6b | 340 | /* Get some IO space for the new PHB */ |
9ccc4fd2 | 341 | pcibios_map_io_space(bus); |
3d5134ee | 342 | |
3fd94c6b | 343 | /* Wire up PHB bus resources */ |
53280323 | 344 | pcibios_setup_phb_resources(hose); |
4267292b | 345 | |
3fd94c6b | 346 | /* Get probe mode and perform scan */ |
4267292b | 347 | mode = PCI_PROBE_NORMAL; |
1beb6a7d | 348 | if (node && ppc_md.pci_probe_mode) |
4267292b | 349 | mode = ppc_md.pci_probe_mode(bus); |
b0494bc8 | 350 | pr_debug(" probe mode: %d\n", mode); |
4267292b PM |
351 | if (mode == PCI_PROBE_DEVTREE) { |
352 | bus->subordinate = hose->last_busno; | |
353 | of_scan_bus(node, bus); | |
354 | } | |
99a565ba | 355 | |
4267292b PM |
356 | if (mode == PCI_PROBE_NORMAL) |
357 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
4267292b PM |
358 | } |
359 | ||
1da177e4 LT |
360 | static int __init pcibios_init(void) |
361 | { | |
362 | struct pci_controller *hose, *tmp; | |
1da177e4 | 363 | |
3fd94c6b BH |
364 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); |
365 | ||
53280323 | 366 | /* For now, override phys_mem_access_prot. If we need it,g |
1da177e4 LT |
367 | * later, we may move that initialization to each ppc_md |
368 | */ | |
369 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
370 | ||
3fd94c6b BH |
371 | if (pci_probe_only) |
372 | ppc_pci_flags |= PPC_PCI_PROBE_ONLY; | |
1da177e4 | 373 | |
1fd0f525 BH |
374 | /* On ppc64, we always enable PCI domains and we keep domain 0 |
375 | * backward compatible in /proc for video cards | |
376 | */ | |
377 | ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0; | |
378 | ||
1da177e4 | 379 | /* Scan all of the recorded PCI controllers. */ |
92eb4602 | 380 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
4267292b | 381 | scan_phb(hose); |
92eb4602 JR |
382 | pci_bus_add_devices(hose->bus); |
383 | } | |
1da177e4 | 384 | |
3fd94c6b BH |
385 | /* Call common code to handle resource allocation */ |
386 | pcibios_resource_survey(); | |
1da177e4 | 387 | |
e884e9c5 | 388 | printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); |
1da177e4 LT |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | subsys_initcall(pcibios_init); | |
394 | ||
3d5134ee BH |
395 | #ifdef CONFIG_HOTPLUG |
396 | ||
397 | int pcibios_unmap_io_space(struct pci_bus *bus) | |
1da177e4 | 398 | { |
3d5134ee | 399 | struct pci_controller *hose; |
1da177e4 | 400 | |
3d5134ee | 401 | WARN_ON(bus == NULL); |
de821204 | 402 | |
3d5134ee BH |
403 | /* If this is not a PHB, we only flush the hash table over |
404 | * the area mapped by this bridge. We don't play with the PTE | |
405 | * mappings since we might have to deal with sub-page alignemnts | |
406 | * so flushing the hash table is the only sane way to make sure | |
407 | * that no hash entries are covering that removed bridge area | |
408 | * while still allowing other busses overlapping those pages | |
409 | */ | |
410 | if (bus->self) { | |
411 | struct resource *res = bus->resource[0]; | |
1da177e4 | 412 | |
b0494bc8 BH |
413 | pr_debug("IO unmapping for PCI-PCI bridge %s\n", |
414 | pci_name(bus->self)); | |
de821204 | 415 | |
3d5134ee | 416 | __flush_hash_table_range(&init_mm, res->start + _IO_BASE, |
b30115ea | 417 | res->end + _IO_BASE + 1); |
3d5134ee BH |
418 | return 0; |
419 | } | |
1da177e4 | 420 | |
3d5134ee BH |
421 | /* Get the host bridge */ |
422 | hose = pci_bus_to_host(bus); | |
1da177e4 | 423 | |
3d5134ee BH |
424 | /* Check if we have IOs allocated */ |
425 | if (hose->io_base_alloc == 0) | |
426 | return 0; | |
de821204 | 427 | |
b0494bc8 BH |
428 | pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); |
429 | pr_debug(" alloc=0x%p\n", hose->io_base_alloc); | |
1da177e4 | 430 | |
3d5134ee BH |
431 | /* This is a PHB, we fully unmap the IO area */ |
432 | vunmap(hose->io_base_alloc); | |
1da177e4 | 433 | |
3d5134ee | 434 | return 0; |
1da177e4 | 435 | } |
3d5134ee | 436 | EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); |
1da177e4 | 437 | |
3d5134ee | 438 | #endif /* CONFIG_HOTPLUG */ |
1da177e4 | 439 | |
3d5134ee | 440 | int __devinit pcibios_map_io_space(struct pci_bus *bus) |
1da177e4 | 441 | { |
3d5134ee BH |
442 | struct vm_struct *area; |
443 | unsigned long phys_page; | |
444 | unsigned long size_page; | |
445 | unsigned long io_virt_offset; | |
446 | struct pci_controller *hose; | |
de821204 | 447 | |
3d5134ee | 448 | WARN_ON(bus == NULL); |
31e92e0a | 449 | |
3d5134ee BH |
450 | /* If this not a PHB, nothing to do, page tables still exist and |
451 | * thus HPTEs will be faulted in when needed | |
452 | */ | |
453 | if (bus->self) { | |
b0494bc8 BH |
454 | pr_debug("IO mapping for PCI-PCI bridge %s\n", |
455 | pci_name(bus->self)); | |
456 | pr_debug(" virt=0x%016lx...0x%016lx\n", | |
457 | bus->resource[0]->start + _IO_BASE, | |
458 | bus->resource[0]->end + _IO_BASE); | |
3d5134ee | 459 | return 0; |
1da177e4 LT |
460 | } |
461 | ||
3d5134ee BH |
462 | /* Get the host bridge */ |
463 | hose = pci_bus_to_host(bus); | |
464 | phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); | |
465 | size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); | |
1da177e4 | 466 | |
3d5134ee BH |
467 | /* Make sure IO area address is clear */ |
468 | hose->io_base_alloc = NULL; | |
1da177e4 | 469 | |
3d5134ee BH |
470 | /* If there's no IO to map on that bus, get away too */ |
471 | if (hose->pci_io_size == 0 || hose->io_base_phys == 0) | |
472 | return 0; | |
1da177e4 | 473 | |
3d5134ee BH |
474 | /* Let's allocate some IO space for that guy. We don't pass |
475 | * VM_IOREMAP because we don't care about alignment tricks that | |
476 | * the core does in that case. Maybe we should due to stupid card | |
477 | * with incomplete address decoding but I'd rather not deal with | |
478 | * those outside of the reserved 64K legacy region. | |
479 | */ | |
480 | area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); | |
481 | if (area == NULL) | |
482 | return -ENOMEM; | |
483 | hose->io_base_alloc = area->addr; | |
484 | hose->io_base_virt = (void __iomem *)(area->addr + | |
485 | hose->io_base_phys - phys_page); | |
486 | ||
b0494bc8 BH |
487 | pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); |
488 | pr_debug(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n", | |
489 | hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); | |
490 | pr_debug(" size=0x%016lx (alloc=0x%016lx)\n", | |
491 | hose->pci_io_size, size_page); | |
3d5134ee BH |
492 | |
493 | /* Establish the mapping */ | |
494 | if (__ioremap_at(phys_page, area->addr, size_page, | |
495 | _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) | |
496 | return -ENOMEM; | |
497 | ||
498 | /* Fixup hose IO resource */ | |
499 | io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
500 | hose->io_resource.start += io_virt_offset; | |
501 | hose->io_resource.end += io_virt_offset; | |
502 | ||
b0494bc8 BH |
503 | pr_debug(" hose->io_resource=0x%016lx...0x%016lx\n", |
504 | hose->io_resource.start, hose->io_resource.end); | |
1da177e4 LT |
505 | |
506 | return 0; | |
507 | } | |
3d5134ee | 508 | EXPORT_SYMBOL_GPL(pcibios_map_io_space); |
1da177e4 | 509 | |
f2c4583a | 510 | unsigned long pci_address_to_pio(phys_addr_t address) |
d4e4b352 SR |
511 | { |
512 | struct pci_controller *hose, *tmp; | |
513 | ||
514 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
515 | if (address >= hose->io_base_phys && | |
f2c4583a BH |
516 | address < (hose->io_base_phys + hose->pci_io_size)) { |
517 | unsigned long base = | |
3d5134ee | 518 | (unsigned long)hose->io_base_virt - _IO_BASE; |
f2c4583a BH |
519 | return base + (address - hose->io_base_phys); |
520 | } | |
d4e4b352 SR |
521 | } |
522 | return (unsigned int)-1; | |
523 | } | |
524 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
525 | ||
b2ad7b5e PM |
526 | |
527 | #define IOBASE_BRIDGE_NUMBER 0 | |
528 | #define IOBASE_MEMORY 1 | |
529 | #define IOBASE_IO 2 | |
530 | #define IOBASE_ISA_IO 3 | |
531 | #define IOBASE_ISA_MEM 4 | |
532 | ||
533 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
534 | unsigned long in_devfn) | |
535 | { | |
536 | struct pci_controller* hose; | |
537 | struct list_head *ln; | |
538 | struct pci_bus *bus = NULL; | |
539 | struct device_node *hose_node; | |
540 | ||
541 | /* Argh ! Please forgive me for that hack, but that's the | |
542 | * simplest way to get existing XFree to not lockup on some | |
543 | * G5 machines... So when something asks for bus 0 io base | |
544 | * (bus 0 is HT root), we return the AGP one instead. | |
545 | */ | |
799d6046 | 546 | if (machine_is_compatible("MacRISC4")) |
b2ad7b5e PM |
547 | if (in_bus == 0) |
548 | in_bus = 0xf0; | |
b2ad7b5e PM |
549 | |
550 | /* That syscall isn't quite compatible with PCI domains, but it's | |
551 | * used on pre-domains setup. We return the first match | |
552 | */ | |
553 | ||
554 | for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { | |
555 | bus = pci_bus_b(ln); | |
545da94f | 556 | if (in_bus >= bus->number && in_bus <= bus->subordinate) |
b2ad7b5e PM |
557 | break; |
558 | bus = NULL; | |
559 | } | |
560 | if (bus == NULL || bus->sysdata == NULL) | |
561 | return -ENODEV; | |
562 | ||
563 | hose_node = (struct device_node *)bus->sysdata; | |
564 | hose = PCI_DN(hose_node)->phb; | |
565 | ||
566 | switch (which) { | |
567 | case IOBASE_BRIDGE_NUMBER: | |
568 | return (long)hose->first_busno; | |
569 | case IOBASE_MEMORY: | |
570 | return (long)hose->pci_mem_offset; | |
571 | case IOBASE_IO: | |
572 | return (long)hose->io_base_phys; | |
573 | case IOBASE_ISA_IO: | |
574 | return (long)isa_io_base; | |
575 | case IOBASE_ISA_MEM: | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | return -EOPNOTSUPP; | |
580 | } | |
357518fa AB |
581 | |
582 | #ifdef CONFIG_NUMA | |
583 | int pcibus_to_node(struct pci_bus *bus) | |
584 | { | |
585 | struct pci_controller *phb = pci_bus_to_host(bus); | |
586 | return phb->node; | |
587 | } | |
588 | EXPORT_SYMBOL(pcibus_to_node); | |
589 | #endif |