[deliverable/linux.git] / arch / powerpc / kernel / pci_64.c

/*
 * Port for PPC64 David Engebretsen, IBM Corp.
 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
 * 
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/list.h>
#include <linux/syscalls.h>
#include <linux/irq.h>
#include <linux/vmalloc.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/ppc-pci.h>

#ifdef DEBUG
#include <asm/udbg.h>
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif

unsigned long pci_probe_only = 1;

/* pci_io_base -- the base address from which io bars are offsets.
 * This is the lowest I/O base address (so bar values are always positive),
 * and it *must* be the start of ISA space if an ISA bus exists because
 * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
 * is mapped on the first 64K of IO space
 */
unsigned long pci_io_base = ISA_IO_BASE;
EXPORT_SYMBOL(pci_io_base);

LIST_HEAD(hose_list);

static void fixup_broken_pcnet32(struct pci_dev* dev)
{
	if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
		dev->vendor = PCI_VENDOR_ID_AMD;
		pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);


static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
{
	const u32 *prop;
	int len;

	prop = of_get_property(np, name, &len);
	if (prop && len >= 4)
		return *prop;
	return def;
}

static unsigned int pci_parse_of_flags(u32 addr0)
{
	unsigned int flags = 0;

	if (addr0 & 0x02000000) {
		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
		flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
		flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
		if (addr0 & 0x40000000)
			flags |= IORESOURCE_PREFETCH
				 | PCI_BASE_ADDRESS_MEM_PREFETCH;
	} else if (addr0 & 0x01000000)
		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
	return flags;
}


static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
{
	u64 base, size;
	unsigned int flags;
	struct resource *res;
	const u32 *addrs;
	u32 i;
	int proplen;

	addrs = of_get_property(node, "assigned-addresses", &proplen);
	if (!addrs)
		return;
	DBG("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
	for (; proplen >= 20; proplen -= 20, addrs += 5) {
		flags = pci_parse_of_flags(addrs[0]);
		if (!flags)
			continue;
		base = of_read_number(&addrs[1], 2);
		size = of_read_number(&addrs[3], 2);
		if (!size)
			continue;
		i = addrs[0] & 0xff;
		DBG("  base: %llx, size: %llx, i: %x\n",
		    (unsigned long long)base, (unsigned long long)size, i);

		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
		} else if (i == dev->rom_base_reg) {
			res = &dev->resource[PCI_ROM_RESOURCE];
			flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
		} else {
			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
			continue;
		}
		res->start = base;
		res->end = base + size - 1;
		res->flags = flags;
		res->name = pci_name(dev);
	}
}

struct pci_dev *of_create_pci_dev(struct device_node *node,
				 struct pci_bus *bus, int devfn)
{
	struct pci_dev *dev;
	const char *type;

	dev = alloc_pci_dev();
	if (!dev)
		return NULL;
	type = of_get_property(node, "device_type", NULL);
	if (type == NULL)
		type = "";

	DBG("    create device, devfn: %x, type: %s\n", devfn, type);

	dev->bus = bus;
	dev->sysdata = node;
	dev->dev.parent = bus->bridge;
	dev->dev.bus = &pci_bus_type;
	dev->devfn = devfn;
	dev->multifunction = 0;		/* maybe a lie? */

	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	dev->device = get_int_prop(node, "device-id", 0xffff);
	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);

	dev->cfg_size = pci_cfg_space_size(dev);

	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	dev->class = get_int_prop(node, "class-code", 0);
	dev->revision = get_int_prop(node, "revision-id", 0);

	DBG("    class: 0x%x\n", dev->class);
	DBG("    revision: 0x%x\n", dev->revision);

	dev->current_state = 4;		/* unknown power state */
	dev->error_state = pci_channel_io_normal;
	dev->dma_mask = 0xffffffff;

	if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
		/* a PCI-PCI bridge */
		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
		dev->rom_base_reg = PCI_ROM_ADDRESS1;
	} else if (!strcmp(type, "cardbus")) {
		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	} else {
		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
		dev->rom_base_reg = PCI_ROM_ADDRESS;
		/* Maybe do a default OF mapping here */
		dev->irq = NO_IRQ;
	}

	pci_parse_of_addrs(node, dev);

	DBG("    adding to system ...\n");

	pci_device_add(dev, bus);

	return dev;
}
EXPORT_SYMBOL(of_create_pci_dev);

void __devinit of_scan_bus(struct device_node *node,
			   struct pci_bus *bus)
{
	struct device_node *child;
	const u32 *reg;
	int reglen, devfn;
	struct pci_dev *dev;

	DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);

	/* Scan direct children */
	for_each_child_of_node(node, child) {
		DBG("  * %s\n", child->full_name);
		reg = of_get_property(child, "reg", &reglen);
		if (reg == NULL || reglen < 20)
			continue;
		devfn = (reg[0] >> 8) & 0xff;

		/* create a new pci_dev for this device */
		dev = of_create_pci_dev(child, bus, devfn);
		if (!dev)
			continue;
		DBG("    dev header type: %x\n", dev->hdr_type);
	}

	/* Ally all fixups */
	pcibios_fixup_of_probed_bus(bus);

	/* Now scan child busses */
	list_for_each_entry(dev, &bus->devices, bus_list) {
		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
		    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
			struct device_node *child = pci_device_to_OF_node(dev);
			if (dev)
				of_scan_pci_bridge(child, dev);
		}
	}
}
EXPORT_SYMBOL(of_scan_bus);

void __devinit of_scan_pci_bridge(struct device_node *node,
				  struct pci_dev *dev)
{
	struct pci_bus *bus;
	const u32 *busrange, *ranges;
	int len, i, mode;
	struct resource *res;
	unsigned int flags;
	u64 size;

	DBG("of_scan_pci_bridge(%s)\n", node->full_name);

	/* parse bus-range property */
	busrange = of_get_property(node, "bus-range", &len);
	if (busrange == NULL || len != 8) {
		printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
		       node->full_name);
		return;
	}
	ranges = of_get_property(node, "ranges", &len);
	if (ranges == NULL) {
		printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
		       node->full_name);
		return;
	}

	bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
	if (!bus) {
		printk(KERN_ERR "Failed to create pci bus for %s\n",
		       node->full_name);
		return;
	}

	bus->primary = dev->bus->number;
	bus->subordinate = busrange[1];
	bus->bridge_ctl = 0;
	bus->sysdata = node;

	/* parse ranges property */
	/* PCI #address-cells == 3 and #size-cells == 2 always */
	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
		res->flags = 0;
		bus->resource[i] = res;
		++res;
	}
	i = 1;
	for (; len >= 32; len -= 32, ranges += 8) {
		flags = pci_parse_of_flags(ranges[0]);
		size = of_read_number(&ranges[6], 2);
		if (flags == 0 || size == 0)
			continue;
		if (flags & IORESOURCE_IO) {
			res = bus->resource[0];
			if (res->flags) {
				printk(KERN_ERR "PCI: ignoring extra I/O range"
				       " for bridge %s\n", node->full_name);
				continue;
			}
		} else {
			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
				printk(KERN_ERR "PCI: too many memory ranges"
				       " for bridge %s\n", node->full_name);
				continue;
			}
			res = bus->resource[i];
			++i;
		}
		res->start = of_read_number(&ranges[1], 2);
		res->end = res->start + size - 1;
		res->flags = flags;
	}
	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
		bus->number);
	DBG("    bus name: %s\n", bus->name);

	mode = PCI_PROBE_NORMAL;
	if (ppc_md.pci_probe_mode)
		mode = ppc_md.pci_probe_mode(bus);
	DBG("    probe mode: %d\n", mode);

	if (mode == PCI_PROBE_DEVTREE)
		of_scan_bus(node, bus);
	else if (mode == PCI_PROBE_NORMAL)
		pci_scan_child_bus(bus);
}
EXPORT_SYMBOL(of_scan_pci_bridge);

void __devinit scan_phb(struct pci_controller *hose)
{
	struct pci_bus *bus;
	struct device_node *node = hose->dn;
	int i, mode;

	DBG("PCI: Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");

	/* Create an empty bus for the toplevel */
	bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
	if (bus == NULL) {
		printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
		       hose->global_number);
		return;
	}
	bus->secondary = hose->first_busno;
	hose->bus = bus;

	/* Get some IO space for the new PHB */
	pcibios_map_io_space(bus);

	/* Wire up PHB bus resources */
	DBG("PCI: PHB IO resource    = %016lx-%016lx [%lx]\n",
	    hose->io_resource.start, hose->io_resource.end,
	    hose->io_resource.flags);
	bus->resource[0] = &hose->io_resource;
	for (i = 0; i < 3; ++i) {
		DBG("PCI: PHB MEM resource %d = %016lx-%016lx [%lx]\n", i,
		    hose->mem_resources[i].start,
		    hose->mem_resources[i].end,
		    hose->mem_resources[i].flags);
		bus->resource[i+1] = &hose->mem_resources[i];
	}
	DBG("PCI: PHB MEM offset     = %016lx\n", hose->pci_mem_offset);
	DBG("PCI: PHB IO  offset     = %08lx\n",
	    (unsigned long)hose->io_base_virt - _IO_BASE);

	/* Get probe mode and perform scan */
	mode = PCI_PROBE_NORMAL;
	if (node && ppc_md.pci_probe_mode)
		mode = ppc_md.pci_probe_mode(bus);
	DBG("    probe mode: %d\n", mode);
	if (mode == PCI_PROBE_DEVTREE) {
		bus->subordinate = hose->last_busno;
		of_scan_bus(node, bus);
	}

	if (mode == PCI_PROBE_NORMAL)
		hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose, *tmp;

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

	/* For now, override phys_mem_access_prot. If we need it,
	 * later, we may move that initialization to each ppc_md
	 */
	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	if (pci_probe_only)
		ppc_pci_flags |= PPC_PCI_PROBE_ONLY;

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		scan_phb(hose);
		pci_bus_add_devices(hose->bus);
	}

	/* Call common code to handle resource allocation */
	pcibios_resource_survey();

	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");

	return 0;
}

subsys_initcall(pcibios_init);

#ifdef CONFIG_HOTPLUG

int pcibios_unmap_io_space(struct pci_bus *bus)
{
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this is not a PHB, we only flush the hash table over
	 * the area mapped by this bridge. We don't play with the PTE
	 * mappings since we might have to deal with sub-page alignemnts
	 * so flushing the hash table is the only sane way to make sure
	 * that no hash entries are covering that removed bridge area
	 * while still allowing other busses overlapping those pages
	 */
	if (bus->self) {
		struct resource *res = bus->resource[0];

		DBG("IO unmapping for PCI-PCI bridge %s\n",
		    pci_name(bus->self));

		__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
					 res->end + _IO_BASE + 1);
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);

	/* Check if we have IOs allocated */
	if (hose->io_base_alloc == 0)
		return 0;

	DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
	DBG("  alloc=0x%p\n", hose->io_base_alloc);

	/* This is a PHB, we fully unmap the IO area */
	vunmap(hose->io_base_alloc);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);

#endif /* CONFIG_HOTPLUG */

int __devinit pcibios_map_io_space(struct pci_bus *bus)
{
	struct vm_struct *area;
	unsigned long phys_page;
	unsigned long size_page;
	unsigned long io_virt_offset;
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this not a PHB, nothing to do, page tables still exist and
	 * thus HPTEs will be faulted in when needed
	 */
	if (bus->self) {
		DBG("IO mapping for PCI-PCI bridge %s\n",
		    pci_name(bus->self));
		DBG("  virt=0x%016lx...0x%016lx\n",
		    bus->resource[0]->start + _IO_BASE,
		    bus->resource[0]->end + _IO_BASE);
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);
	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);

	/* Make sure IO area address is clear */
	hose->io_base_alloc = NULL;

	/* If there's no IO to map on that bus, get away too */
	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
		return 0;

	/* Let's allocate some IO space for that guy. We don't pass
	 * VM_IOREMAP because we don't care about alignment tricks that
	 * the core does in that case. Maybe we should due to stupid card
	 * with incomplete address decoding but I'd rather not deal with
	 * those outside of the reserved 64K legacy region.
	 */
	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	if (area == NULL)
		return -ENOMEM;
	hose->io_base_alloc = area->addr;
	hose->io_base_virt = (void __iomem *)(area->addr +
					      hose->io_base_phys - phys_page);

	DBG("IO mapping for PHB %s\n", hose->dn->full_name);
	DBG("  phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
	    hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
	DBG("  size=0x%016lx (alloc=0x%016lx)\n",
	    hose->pci_io_size, size_page);

	/* Establish the mapping */
	if (__ioremap_at(phys_page, area->addr, size_page,
			 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
		return -ENOMEM;

	/* Fixup hose IO resource */
	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	hose->io_resource.start += io_virt_offset;
	hose->io_resource.end += io_virt_offset;

	DBG("  hose->io_resource=0x%016lx...0x%016lx\n",
	    hose->io_resource.start, hose->io_resource.end);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_map_io_space);

void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
{
	struct pci_dev *dev;

	if (ppc_md.pci_dma_bus_setup)
		ppc_md.pci_dma_bus_setup(bus);

	list_for_each_entry(dev, &bus->devices, bus_list)
		pcibios_setup_new_device(dev);
}

unsigned long pci_address_to_pio(phys_addr_t address)
{
	struct pci_controller *hose, *tmp;

	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		if (address >= hose->io_base_phys &&
		    address < (hose->io_base_phys + hose->pci_io_size)) {
			unsigned long base =
				(unsigned long)hose->io_base_virt - _IO_BASE;
			return base + (address - hose->io_base_phys);
		}
	}
	return (unsigned int)-1;
}
EXPORT_SYMBOL_GPL(pci_address_to_pio);


#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

long sys_pciconfig_iobase(long which, unsigned long in_bus,
			  unsigned long in_devfn)
{
	struct pci_controller* hose;
	struct list_head *ln;
	struct pci_bus *bus = NULL;
	struct device_node *hose_node;

	/* Argh ! Please forgive me for that hack, but that's the
	 * simplest way to get existing XFree to not lockup on some
	 * G5 machines... So when something asks for bus 0 io base
	 * (bus 0 is HT root), we return the AGP one instead.
	 */
	if (machine_is_compatible("MacRISC4"))
		if (in_bus == 0)
			in_bus = 0xf0;

	/* That syscall isn't quite compatible with PCI domains, but it's
	 * used on pre-domains setup. We return the first match
	 */

	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
		bus = pci_bus_b(ln);
		if (in_bus >= bus->number && in_bus <= bus->subordinate)
			break;
		bus = NULL;
	}
	if (bus == NULL || bus->sysdata == NULL)
		return -ENODEV;

	hose_node = (struct device_node *)bus->sysdata;
	hose = PCI_DN(hose_node)->phb;

	switch (which) {
	case IOBASE_BRIDGE_NUMBER:
		return (long)hose->first_busno;
	case IOBASE_MEMORY:
		return (long)hose->pci_mem_offset;
	case IOBASE_IO:
		return (long)hose->io_base_phys;
	case IOBASE_ISA_IO:
		return (long)isa_io_base;
	case IOBASE_ISA_MEM:
		return -EINVAL;
	}

	return -EOPNOTSUPP;
}

#ifdef CONFIG_NUMA
int pcibus_to_node(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);
	return phb->node;
}
EXPORT_SYMBOL(pcibus_to_node);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Port for PPC64 David Engebretsen, IBM Corp.
	3	* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
	4	*
	5	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	6	* Rework, based on alpha PCI code.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#undef DEBUG
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/bootmem.h>
	21	#include <linux/mm.h>
	22	#include <linux/list.h>
b2ad7b5e	23	#include <linux/syscalls.h>
6e99e458	24	#include <linux/irq.h>
3d5134ee	25	#include <linux/vmalloc.h>
1da177e4 LT	26
	27	#include <asm/processor.h>
	28	#include <asm/io.h>
	29	#include <asm/prom.h>
	30	#include <asm/pci-bridge.h>
	31	#include <asm/byteorder.h>
1da177e4	32	#include <asm/machdep.h>
d387899f	33	#include <asm/ppc-pci.h>
1da177e4 LT	34
1da177e4 LT	35	#ifdef DEBUG
f9e4ec57	36	#include <asm/udbg.h>
1beb6a7d	37	#define DBG(fmt...) printk(fmt)
1da177e4 LT	38	#else
	39	#define DBG(fmt...)
	40	#endif
	41
	42	unsigned long pci_probe_only = 1;
1da177e4	43
1da177e4 LT	44	/* pci_io_base -- the base address from which io bars are offsets.
	45	* This is the lowest I/O base address (so bar values are always positive),
	46	* and it must be the start of ISA space if an ISA bus exists because
3d5134ee BH	47	* ISA drivers use hard coded offsets. If no ISA bus exists nothing
3d5134ee BH	48	* is mapped on the first 64K of IO space
1da177e4	49	*/
3d5134ee	50	unsigned long pci_io_base = ISA_IO_BASE;
1da177e4 LT	51	EXPORT_SYMBOL(pci_io_base);
1da177e4 LT	52
1da177e4 LT	53	LIST_HEAD(hose_list);
1da177e4 LT	54
1da177e4 LT	55	static void fixup_broken_pcnet32(struct pci_dev* dev)
	56	{
	57	if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
	58	dev->vendor = PCI_VENDOR_ID_AMD;
	59	pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
1da177e4 LT	60	}
	61	}
	62	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
	63
1da177e4	64
4267292b PM	65	static u32 get_int_prop(struct device_node np, const char name, u32 def)
4267292b PM	66	{
a7f67bdf	67	const u32 *prop;
4267292b PM	68	int len;
4267292b PM	69
e2eb6392	70	prop = of_get_property(np, name, &len);
4267292b PM	71	if (prop && len >= 4)
	72	return *prop;
	73	return def;
	74	}
	75
	76	static unsigned int pci_parse_of_flags(u32 addr0)
	77	{
	78	unsigned int flags = 0;
	79
	80	if (addr0 & 0x02000000) {
d79e743e PM	81	flags = IORESOURCE_MEM \| PCI_BASE_ADDRESS_SPACE_MEMORY;
	82	flags \|= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
	83	flags \|= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
4267292b	84	if (addr0 & 0x40000000)
d79e743e PM	85	flags \|= IORESOURCE_PREFETCH
d79e743e PM	86	\| PCI_BASE_ADDRESS_MEM_PREFETCH;
4267292b	87	} else if (addr0 & 0x01000000)
d79e743e	88	flags = IORESOURCE_IO \| PCI_BASE_ADDRESS_SPACE_IO;
4267292b PM	89	return flags;
	90	}
	91
4267292b PM	92
	93	static void pci_parse_of_addrs(struct device_node node, struct pci_dev dev)
	94	{
	95	u64 base, size;
	96	unsigned int flags;
	97	struct resource *res;
a7f67bdf JK	98	const u32 *addrs;
a7f67bdf JK	99	u32 i;
4267292b PM	100	int proplen;
4267292b PM	101
e2eb6392	102	addrs = of_get_property(node, "assigned-addresses", &proplen);
4267292b PM	103	if (!addrs)
4267292b PM	104	return;
1beb6a7d	105	DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
4267292b PM	106	for (; proplen >= 20; proplen -= 20, addrs += 5) {
	107	flags = pci_parse_of_flags(addrs[0]);
	108	if (!flags)
	109	continue;
327e22df JL	110	base = of_read_number(&addrs[1], 2);
327e22df JL	111	size = of_read_number(&addrs[3], 2);
4267292b PM	112	if (!size)
	113	continue;
	114	i = addrs[0] & 0xff;
1beb6a7d BH	115	DBG(" base: %llx, size: %llx, i: %x\n",
	116	(unsigned long long)base, (unsigned long long)size, i);
	117
4267292b PM	118	if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
	119	res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
	120	} else if (i == dev->rom_base_reg) {
	121	res = &dev->resource[PCI_ROM_RESOURCE];
	122	flags \|= IORESOURCE_READONLY \| IORESOURCE_CACHEABLE;
	123	} else {
	124	printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
	125	continue;
	126	}
	127	res->start = base;
	128	res->end = base + size - 1;
	129	res->flags = flags;
	130	res->name = pci_name(dev);
4267292b PM	131	}
	132	}
	133
ead83717 JR	134	struct pci_dev of_create_pci_dev(struct device_node node,
ead83717 JR	135	struct pci_bus *bus, int devfn)
4267292b PM	136	{
	137	struct pci_dev *dev;
	138	const char *type;
	139
bab41e9b	140	dev = alloc_pci_dev();
4267292b PM	141	if (!dev)
4267292b PM	142	return NULL;
e2eb6392	143	type = of_get_property(node, "device_type", NULL);
4267292b PM	144	if (type == NULL)
	145	type = "";
	146
1beb6a7d BH	147	DBG(" create device, devfn: %x, type: %s\n", devfn, type);
1beb6a7d BH	148
4267292b PM	149	dev->bus = bus;
	150	dev->sysdata = node;
	151	dev->dev.parent = bus->bridge;
	152	dev->dev.bus = &pci_bus_type;
	153	dev->devfn = devfn;
	154	dev->multifunction = 0; /* maybe a lie? */
	155
	156	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	157	dev->device = get_int_prop(node, "device-id", 0xffff);
	158	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	159	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
	160
9d17a5c6	161	dev->cfg_size = pci_cfg_space_size(dev);
4267292b	162
420b5eea	163	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
4267292b PM	164	dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
4267292b PM	165	dev->class = get_int_prop(node, "class-code", 0);
b8a3a521	166	dev->revision = get_int_prop(node, "revision-id", 0);
4267292b	167
1beb6a7d	168	DBG(" class: 0x%x\n", dev->class);
b8a3a521	169	DBG(" revision: 0x%x\n", dev->revision);
1beb6a7d	170
4267292b	171	dev->current_state = 4; /* unknown power state */
bb63ab13	172	dev->error_state = pci_channel_io_normal;
8f2ea1fd	173	dev->dma_mask = 0xffffffff;
4267292b	174
bb53bb3d	175	if (!strcmp(type, "pci") \|\| !strcmp(type, "pciex")) {
4267292b PM	176	/* a PCI-PCI bridge */
	177	dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
	178	dev->rom_base_reg = PCI_ROM_ADDRESS1;
	179	} else if (!strcmp(type, "cardbus")) {
	180	dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	181	} else {
	182	dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
	183	dev->rom_base_reg = PCI_ROM_ADDRESS;
0ebfff14	184	/* Maybe do a default OF mapping here */
4267292b	185	dev->irq = NO_IRQ;
4267292b PM	186	}
	187
	188	pci_parse_of_addrs(node, dev);
	189
1beb6a7d BH	190	DBG(" adding to system ...\n");
1beb6a7d BH	191
4267292b PM	192	pci_device_add(dev, bus);
4267292b PM	193
4267292b PM	194	return dev;
4267292b PM	195	}
ead83717	196	EXPORT_SYMBOL(of_create_pci_dev);
4267292b	197
ead83717	198	void __devinit of_scan_bus(struct device_node *node,
bf5e2ba2	199	struct pci_bus *bus)
4267292b	200	{
85e99b9f	201	struct device_node *child;
a7f67bdf	202	const u32 *reg;
4267292b PM	203	int reglen, devfn;
	204	struct pci_dev *dev;
	205
1beb6a7d BH	206	DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number);
1beb6a7d BH	207
bf5e2ba2	208	/* Scan direct children */
85e99b9f	209	for_each_child_of_node(node, child) {
1beb6a7d	210	DBG(" * %s\n", child->full_name);
e2eb6392	211	reg = of_get_property(child, "reg", &reglen);
4267292b PM	212	if (reg == NULL \|\| reglen < 20)
	213	continue;
	214	devfn = (reg[0] >> 8) & 0xff;
1beb6a7d	215
4267292b PM	216	/* create a new pci_dev for this device */
	217	dev = of_create_pci_dev(child, bus, devfn);
	218	if (!dev)
	219	continue;
bf5e2ba2 BH	220	DBG(" dev header type: %x\n", dev->hdr_type);
	221	}
	222
	223	/* Ally all fixups */
	224	pcibios_fixup_of_probed_bus(bus);
1beb6a7d	225
bf5e2ba2 BH	226	/* Now scan child busses */
bf5e2ba2 BH	227	list_for_each_entry(dev, &bus->devices, bus_list) {
4267292b	228	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE \|\|
bf5e2ba2 BH	229	dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
	230	struct device_node *child = pci_device_to_OF_node(dev);
	231	if (dev)
	232	of_scan_pci_bridge(child, dev);
	233	}
4267292b	234	}
4267292b	235	}
ead83717	236	EXPORT_SYMBOL(of_scan_bus);
4267292b	237
ead83717	238	void __devinit of_scan_pci_bridge(struct device_node *node,
bf5e2ba2	239	struct pci_dev *dev)
4267292b PM	240	{
4267292b PM	241	struct pci_bus *bus;
a7f67bdf	242	const u32 busrange, ranges;
4267292b PM	243	int len, i, mode;
	244	struct resource *res;
	245	unsigned int flags;
	246	u64 size;
	247
1beb6a7d BH	248	DBG("of_scan_pci_bridge(%s)\n", node->full_name);
1beb6a7d BH	249
4267292b	250	/* parse bus-range property */
e2eb6392	251	busrange = of_get_property(node, "bus-range", &len);
4267292b	252	if (busrange == NULL \|\| len != 8) {
1beb6a7d	253	printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
4267292b PM	254	node->full_name);
	255	return;
	256	}
e2eb6392	257	ranges = of_get_property(node, "ranges", &len);
4267292b	258	if (ranges == NULL) {
1beb6a7d	259	printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
4267292b PM	260	node->full_name);
	261	return;
	262	}
	263
	264	bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
	265	if (!bus) {
	266	printk(KERN_ERR "Failed to create pci bus for %s\n",
	267	node->full_name);
	268	return;
	269	}
	270
	271	bus->primary = dev->bus->number;
	272	bus->subordinate = busrange[1];
	273	bus->bridge_ctl = 0;
	274	bus->sysdata = node;
	275
	276	/* parse ranges property */
	277	/* PCI #address-cells == 3 and #size-cells == 2 always */
	278	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	279	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
	280	res->flags = 0;
	281	bus->resource[i] = res;
	282	++res;
	283	}
	284	i = 1;
	285	for (; len >= 32; len -= 32, ranges += 8) {
	286	flags = pci_parse_of_flags(ranges[0]);
327e22df	287	size = of_read_number(&ranges[6], 2);
4267292b PM	288	if (flags == 0 \|\| size == 0)
	289	continue;
	290	if (flags & IORESOURCE_IO) {
	291	res = bus->resource[0];
	292	if (res->flags) {
	293	printk(KERN_ERR "PCI: ignoring extra I/O range"
	294	" for bridge %s\n", node->full_name);
	295	continue;
	296	}
	297	} else {
	298	if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
	299	printk(KERN_ERR "PCI: too many memory ranges"
	300	" for bridge %s\n", node->full_name);
	301	continue;
	302	}
	303	res = bus->resource[i];
	304	++i;
	305	}
327e22df	306	res->start = of_read_number(&ranges[1], 2);
4267292b PM	307	res->end = res->start + size - 1;
4267292b PM	308	res->flags = flags;
4267292b PM	309	}
	310	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
	311	bus->number);
1beb6a7d	312	DBG(" bus name: %s\n", bus->name);
4267292b PM	313
	314	mode = PCI_PROBE_NORMAL;
	315	if (ppc_md.pci_probe_mode)
	316	mode = ppc_md.pci_probe_mode(bus);
1beb6a7d BH	317	DBG(" probe mode: %d\n", mode);
1beb6a7d BH	318
4267292b PM	319	if (mode == PCI_PROBE_DEVTREE)
	320	of_scan_bus(node, bus);
	321	else if (mode == PCI_PROBE_NORMAL)
	322	pci_scan_child_bus(bus);
	323	}
ead83717	324	EXPORT_SYMBOL(of_scan_pci_bridge);
4267292b	325
ead83717	326	void __devinit scan_phb(struct pci_controller *hose)
4267292b PM	327	{
4267292b PM	328	struct pci_bus *bus;
44ef3390	329	struct device_node *node = hose->dn;
4267292b	330	int i, mode;
4267292b	331
50c9bc2f	332	DBG("PCI: Scanning PHB %s\n", node ? node->full_name : "<NO NAME>");
1beb6a7d	333
3fd94c6b	334	/* Create an empty bus for the toplevel */
803d4573	335	bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
4267292b PM	336	if (bus == NULL) {
	337	printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
	338	hose->global_number);
	339	return;
	340	}
	341	bus->secondary = hose->first_busno;
	342	hose->bus = bus;
	343
3fd94c6b	344	/* Get some IO space for the new PHB */
9ccc4fd2	345	pcibios_map_io_space(bus);
3d5134ee	346
3fd94c6b	347	/* Wire up PHB bus resources */
9d5f4928 BH	348	DBG("PCI: PHB IO resource = %016lx-%016lx [%lx]\n",
	349	hose->io_resource.start, hose->io_resource.end,
	350	hose->io_resource.flags);
	351	bus->resource[0] = &hose->io_resource;
50c9bc2f BH	352	for (i = 0; i < 3; ++i) {
	353	DBG("PCI: PHB MEM resource %d = %016lx-%016lx [%lx]\n", i,
	354	hose->mem_resources[i].start,
	355	hose->mem_resources[i].end,
	356	hose->mem_resources[i].flags);
3fd94c6b	357	bus->resource[i+1] = &hose->mem_resources[i];
50c9bc2f BH	358	}
	359	DBG("PCI: PHB MEM offset = %016lx\n", hose->pci_mem_offset);
	360	DBG("PCI: PHB IO offset = %08lx\n",
	361	(unsigned long)hose->io_base_virt - _IO_BASE);
4267292b	362
3fd94c6b	363	/* Get probe mode and perform scan */
4267292b	364	mode = PCI_PROBE_NORMAL;
1beb6a7d	365	if (node && ppc_md.pci_probe_mode)
4267292b	366	mode = ppc_md.pci_probe_mode(bus);
1beb6a7d	367	DBG(" probe mode: %d\n", mode);
4267292b PM	368	if (mode == PCI_PROBE_DEVTREE) {
	369	bus->subordinate = hose->last_busno;
	370	of_scan_bus(node, bus);
	371	}
99a565ba	372
4267292b PM	373	if (mode == PCI_PROBE_NORMAL)
4267292b PM	374	hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
4267292b PM	375	}
4267292b PM	376
1da177e4 LT	377	static int __init pcibios_init(void)
	378	{
	379	struct pci_controller hose, tmp;
1da177e4	380
3fd94c6b BH	381	printk(KERN_INFO "PCI: Probing PCI hardware\n");
3fd94c6b BH	382
1da177e4 LT	383	/* For now, override phys_mem_access_prot. If we need it,
	384	* later, we may move that initialization to each ppc_md
	385	*/
	386	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	387
3fd94c6b BH	388	if (pci_probe_only)
3fd94c6b BH	389	ppc_pci_flags \|= PPC_PCI_PROBE_ONLY;
1da177e4 LT	390
1da177e4 LT	391	/* Scan all of the recorded PCI controllers. */
92eb4602	392	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
4267292b	393	scan_phb(hose);
92eb4602 JR	394	pci_bus_add_devices(hose->bus);
92eb4602 JR	395	}
1da177e4	396
3fd94c6b BH	397	/* Call common code to handle resource allocation */
3fd94c6b BH	398	pcibios_resource_survey();
1da177e4	399
e884e9c5	400	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
1da177e4 LT	401
	402	return 0;
	403	}
	404
	405	subsys_initcall(pcibios_init);
	406
3d5134ee BH	407	#ifdef CONFIG_HOTPLUG
	408
	409	int pcibios_unmap_io_space(struct pci_bus *bus)
1da177e4	410	{
3d5134ee	411	struct pci_controller *hose;
1da177e4	412
3d5134ee	413	WARN_ON(bus == NULL);
de821204	414
3d5134ee BH	415	/* If this is not a PHB, we only flush the hash table over
	416	* the area mapped by this bridge. We don't play with the PTE
	417	* mappings since we might have to deal with sub-page alignemnts
	418	* so flushing the hash table is the only sane way to make sure
	419	* that no hash entries are covering that removed bridge area
	420	* while still allowing other busses overlapping those pages
	421	*/
	422	if (bus->self) {
	423	struct resource *res = bus->resource[0];
1da177e4	424
3d5134ee BH	425	DBG("IO unmapping for PCI-PCI bridge %s\n",
3d5134ee BH	426	pci_name(bus->self));
de821204	427
3d5134ee	428	__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
b30115ea	429	res->end + _IO_BASE + 1);
3d5134ee BH	430	return 0;
3d5134ee BH	431	}
1da177e4	432
3d5134ee BH	433	/* Get the host bridge */
3d5134ee BH	434	hose = pci_bus_to_host(bus);
1da177e4	435
3d5134ee BH	436	/* Check if we have IOs allocated */
	437	if (hose->io_base_alloc == 0)
	438	return 0;
de821204	439
44ef3390	440	DBG("IO unmapping for PHB %s\n", hose->dn->full_name);
3d5134ee	441	DBG(" alloc=0x%p\n", hose->io_base_alloc);
1da177e4	442
3d5134ee BH	443	/* This is a PHB, we fully unmap the IO area */
3d5134ee BH	444	vunmap(hose->io_base_alloc);
1da177e4	445
3d5134ee	446	return 0;
1da177e4	447	}
3d5134ee	448	EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
1da177e4	449
3d5134ee	450	#endif /* CONFIG_HOTPLUG */
1da177e4	451
3d5134ee	452	int __devinit pcibios_map_io_space(struct pci_bus *bus)
1da177e4	453	{
3d5134ee BH	454	struct vm_struct *area;
	455	unsigned long phys_page;
	456	unsigned long size_page;
	457	unsigned long io_virt_offset;
	458	struct pci_controller *hose;
de821204	459
3d5134ee	460	WARN_ON(bus == NULL);
31e92e0a	461
3d5134ee BH	462	/* If this not a PHB, nothing to do, page tables still exist and
	463	* thus HPTEs will be faulted in when needed
	464	*/
	465	if (bus->self) {
	466	DBG("IO mapping for PCI-PCI bridge %s\n",
	467	pci_name(bus->self));
	468	DBG(" virt=0x%016lx...0x%016lx\n",
	469	bus->resource[0]->start + _IO_BASE,
	470	bus->resource[0]->end + _IO_BASE);
	471	return 0;
1da177e4 LT	472	}
1da177e4 LT	473
3d5134ee BH	474	/* Get the host bridge */
	475	hose = pci_bus_to_host(bus);
	476	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	477	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
1da177e4	478
3d5134ee BH	479	/* Make sure IO area address is clear */
3d5134ee BH	480	hose->io_base_alloc = NULL;
1da177e4	481
3d5134ee BH	482	/* If there's no IO to map on that bus, get away too */
	483	if (hose->pci_io_size == 0 \|\| hose->io_base_phys == 0)
	484	return 0;
1da177e4	485
3d5134ee BH	486	/* Let's allocate some IO space for that guy. We don't pass
	487	* VM_IOREMAP because we don't care about alignment tricks that
	488	* the core does in that case. Maybe we should due to stupid card
	489	* with incomplete address decoding but I'd rather not deal with
	490	* those outside of the reserved 64K legacy region.
	491	*/
	492	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	493	if (area == NULL)
	494	return -ENOMEM;
	495	hose->io_base_alloc = area->addr;
	496	hose->io_base_virt = (void __iomem *)(area->addr +
	497	hose->io_base_phys - phys_page);
	498
44ef3390	499	DBG("IO mapping for PHB %s\n", hose->dn->full_name);
3d5134ee BH	500	DBG(" phys=0x%016lx, virt=0x%p (alloc=0x%p)\n",
	501	hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
	502	DBG(" size=0x%016lx (alloc=0x%016lx)\n",
	503	hose->pci_io_size, size_page);
	504
	505	/* Establish the mapping */
	506	if (__ioremap_at(phys_page, area->addr, size_page,
	507	_PAGE_NO_CACHE \| _PAGE_GUARDED) == NULL)
	508	return -ENOMEM;
	509
	510	/* Fixup hose IO resource */
	511	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	512	hose->io_resource.start += io_virt_offset;
	513	hose->io_resource.end += io_virt_offset;
	514
	515	DBG(" hose->io_resource=0x%016lx...0x%016lx\n",
	516	hose->io_resource.start, hose->io_resource.end);
1da177e4 LT	517
	518	return 0;
	519	}
3d5134ee	520	EXPORT_SYMBOL_GPL(pcibios_map_io_space);
1da177e4	521
bf5e2ba2	522	void __devinit pcibios_do_bus_setup(struct pci_bus *bus)
1da177e4	523	{
4267292b	524	struct pci_dev *dev;
1da177e4	525
12d04eef BH	526	if (ppc_md.pci_dma_bus_setup)
12d04eef BH	527	ppc_md.pci_dma_bus_setup(bus);
1da177e4	528
4267292b	529	list_for_each_entry(dev, &bus->devices, bus_list)
12d04eef	530	pcibios_setup_new_device(dev);
1da177e4	531	}
1da177e4	532
f2c4583a	533	unsigned long pci_address_to_pio(phys_addr_t address)
d4e4b352 SR	534	{
	535	struct pci_controller hose, tmp;
	536
	537	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
	538	if (address >= hose->io_base_phys &&
f2c4583a BH	539	address < (hose->io_base_phys + hose->pci_io_size)) {
f2c4583a BH	540	unsigned long base =
3d5134ee	541	(unsigned long)hose->io_base_virt - _IO_BASE;
f2c4583a BH	542	return base + (address - hose->io_base_phys);
f2c4583a BH	543	}
d4e4b352 SR	544	}
	545	return (unsigned int)-1;
	546	}
	547	EXPORT_SYMBOL_GPL(pci_address_to_pio);
	548
b2ad7b5e PM	549
	550	#define IOBASE_BRIDGE_NUMBER 0
	551	#define IOBASE_MEMORY 1
	552	#define IOBASE_IO 2
	553	#define IOBASE_ISA_IO 3
	554	#define IOBASE_ISA_MEM 4
	555
	556	long sys_pciconfig_iobase(long which, unsigned long in_bus,
	557	unsigned long in_devfn)
	558	{
	559	struct pci_controller* hose;
	560	struct list_head *ln;
	561	struct pci_bus *bus = NULL;
	562	struct device_node *hose_node;
	563
	564	/* Argh ! Please forgive me for that hack, but that's the
	565	* simplest way to get existing XFree to not lockup on some
	566	* G5 machines... So when something asks for bus 0 io base
	567	* (bus 0 is HT root), we return the AGP one instead.
	568	*/
799d6046	569	if (machine_is_compatible("MacRISC4"))
b2ad7b5e PM	570	if (in_bus == 0)
b2ad7b5e PM	571	in_bus = 0xf0;
b2ad7b5e PM	572
	573	/* That syscall isn't quite compatible with PCI domains, but it's
	574	* used on pre-domains setup. We return the first match
	575	*/
	576
	577	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
	578	bus = pci_bus_b(ln);
545da94f	579	if (in_bus >= bus->number && in_bus <= bus->subordinate)
b2ad7b5e PM	580	break;
	581	bus = NULL;
	582	}
	583	if (bus == NULL \|\| bus->sysdata == NULL)
	584	return -ENODEV;
	585
	586	hose_node = (struct device_node *)bus->sysdata;
	587	hose = PCI_DN(hose_node)->phb;
	588
	589	switch (which) {
	590	case IOBASE_BRIDGE_NUMBER:
	591	return (long)hose->first_busno;
	592	case IOBASE_MEMORY:
	593	return (long)hose->pci_mem_offset;
	594	case IOBASE_IO:
	595	return (long)hose->io_base_phys;
	596	case IOBASE_ISA_IO:
	597	return (long)isa_io_base;
	598	case IOBASE_ISA_MEM:
	599	return -EINVAL;
	600	}
	601
	602	return -EOPNOTSUPP;
	603	}
357518fa AB	604
	605	#ifdef CONFIG_NUMA
	606	int pcibus_to_node(struct pci_bus *bus)
	607	{
	608	struct pci_controller *phb = pci_bus_to_host(bus);
	609	return phb->node;
	610	}
	611	EXPORT_SYMBOL(pcibus_to_node);
	612	#endif