Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
16 | #include <linux/config.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/bootmem.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/list.h> | |
b2ad7b5e | 24 | #include <linux/syscalls.h> |
1da177e4 LT |
25 | |
26 | #include <asm/processor.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/prom.h> | |
29 | #include <asm/pci-bridge.h> | |
30 | #include <asm/byteorder.h> | |
31 | #include <asm/irq.h> | |
32 | #include <asm/machdep.h> | |
d387899f | 33 | #include <asm/ppc-pci.h> |
1da177e4 LT |
34 | |
35 | #ifdef DEBUG | |
f9e4ec57 | 36 | #include <asm/udbg.h> |
1beb6a7d | 37 | #define DBG(fmt...) printk(fmt) |
1da177e4 LT |
38 | #else |
39 | #define DBG(fmt...) | |
40 | #endif | |
41 | ||
42 | unsigned long pci_probe_only = 1; | |
f8ef2705 | 43 | int pci_assign_all_buses = 0; |
1da177e4 | 44 | |
4267292b PM |
45 | #ifdef CONFIG_PPC_MULTIPLATFORM |
46 | static void fixup_resource(struct resource *res, struct pci_dev *dev); | |
47 | static void do_bus_setup(struct pci_bus *bus); | |
9623b5d3 | 48 | static void phbs_remap_io(void); |
4267292b | 49 | #endif |
1da177e4 | 50 | |
1da177e4 LT |
51 | /* pci_io_base -- the base address from which io bars are offsets. |
52 | * This is the lowest I/O base address (so bar values are always positive), | |
53 | * and it *must* be the start of ISA space if an ISA bus exists because | |
54 | * ISA drivers use hard coded offsets. If no ISA bus exists a dummy | |
55 | * page is mapped and isa_io_limit prevents access to it. | |
56 | */ | |
57 | unsigned long isa_io_base; /* NULL if no ISA bus */ | |
58 | EXPORT_SYMBOL(isa_io_base); | |
59 | unsigned long pci_io_base; | |
60 | EXPORT_SYMBOL(pci_io_base); | |
61 | ||
62 | void iSeries_pcibios_init(void); | |
63 | ||
64 | LIST_HEAD(hose_list); | |
65 | ||
66 | struct dma_mapping_ops pci_dma_ops; | |
67 | EXPORT_SYMBOL(pci_dma_ops); | |
68 | ||
69 | int global_phb_number; /* Global phb counter */ | |
70 | ||
71 | /* Cached ISA bridge dev. */ | |
72 | struct pci_dev *ppc64_isabridge_dev = NULL; | |
b239cbe9 | 73 | EXPORT_SYMBOL_GPL(ppc64_isabridge_dev); |
1da177e4 LT |
74 | |
75 | static void fixup_broken_pcnet32(struct pci_dev* dev) | |
76 | { | |
77 | if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { | |
78 | dev->vendor = PCI_VENDOR_ID_AMD; | |
79 | pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD); | |
1da177e4 LT |
80 | } |
81 | } | |
82 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32); | |
83 | ||
84 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |
85 | struct resource *res) | |
86 | { | |
87 | unsigned long offset = 0; | |
88 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
89 | ||
90 | if (!hose) | |
91 | return; | |
92 | ||
93 | if (res->flags & IORESOURCE_IO) | |
94 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
95 | ||
96 | if (res->flags & IORESOURCE_MEM) | |
97 | offset = hose->pci_mem_offset; | |
98 | ||
99 | region->start = res->start - offset; | |
100 | region->end = res->end - offset; | |
101 | } | |
102 | ||
43c34735 DB |
103 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
104 | struct pci_bus_region *region) | |
105 | { | |
106 | unsigned long offset = 0; | |
107 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
108 | ||
109 | if (!hose) | |
110 | return; | |
111 | ||
112 | if (res->flags & IORESOURCE_IO) | |
113 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
114 | ||
115 | if (res->flags & IORESOURCE_MEM) | |
116 | offset = hose->pci_mem_offset; | |
117 | ||
118 | res->start = region->start + offset; | |
119 | res->end = region->end + offset; | |
120 | } | |
121 | ||
1da177e4 LT |
122 | #ifdef CONFIG_HOTPLUG |
123 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
43c34735 | 124 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
125 | #endif |
126 | ||
127 | /* | |
128 | * We need to avoid collisions with `mirrored' VGA ports | |
129 | * and other strange ISA hardware, so we always want the | |
130 | * addresses to be allocated in the 0x000-0x0ff region | |
131 | * modulo 0x400. | |
132 | * | |
133 | * Why? Because some silly external IO cards only decode | |
134 | * the low 10 bits of the IO address. The 0x00-0xff region | |
135 | * is reserved for motherboard devices that decode all 16 | |
136 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
137 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
138 | * which might have be mirrored at 0x0100-0x03ff.. | |
139 | */ | |
140 | void pcibios_align_resource(void *data, struct resource *res, | |
141 | unsigned long size, unsigned long align) | |
142 | { | |
143 | struct pci_dev *dev = data; | |
144 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
145 | unsigned long start = res->start; | |
146 | unsigned long alignto; | |
147 | ||
148 | if (res->flags & IORESOURCE_IO) { | |
149 | unsigned long offset = (unsigned long)hose->io_base_virt - | |
150 | pci_io_base; | |
151 | /* Make sure we start at our min on all hoses */ | |
152 | if (start - offset < PCIBIOS_MIN_IO) | |
153 | start = PCIBIOS_MIN_IO + offset; | |
154 | ||
155 | /* | |
156 | * Put everything into 0x00-0xff region modulo 0x400 | |
157 | */ | |
158 | if (start & 0x300) | |
159 | start = (start + 0x3ff) & ~0x3ff; | |
160 | ||
161 | } else if (res->flags & IORESOURCE_MEM) { | |
162 | /* Make sure we start at our min on all hoses */ | |
163 | if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM) | |
164 | start = PCIBIOS_MIN_MEM + hose->pci_mem_offset; | |
165 | ||
166 | /* Align to multiple of size of minimum base. */ | |
167 | alignto = max(0x1000UL, align); | |
168 | start = ALIGN(start, alignto); | |
169 | } | |
170 | ||
171 | res->start = start; | |
172 | } | |
173 | ||
174 | static DEFINE_SPINLOCK(hose_spinlock); | |
175 | ||
176 | /* | |
177 | * pci_controller(phb) initialized common variables. | |
178 | */ | |
b5166cc2 | 179 | static void __devinit pci_setup_pci_controller(struct pci_controller *hose) |
1da177e4 LT |
180 | { |
181 | memset(hose, 0, sizeof(struct pci_controller)); | |
182 | ||
183 | spin_lock(&hose_spinlock); | |
184 | hose->global_number = global_phb_number++; | |
185 | list_add_tail(&hose->list_node, &hose_list); | |
186 | spin_unlock(&hose_spinlock); | |
187 | } | |
188 | ||
b5166cc2 BH |
189 | static void add_linux_pci_domain(struct device_node *dev, |
190 | struct pci_controller *phb) | |
191 | { | |
192 | struct property *of_prop; | |
193 | unsigned int size; | |
194 | ||
195 | of_prop = (struct property *) | |
196 | get_property(dev, "linux,pci-domain", &size); | |
197 | if (of_prop != NULL) | |
198 | return; | |
199 | WARN_ON(of_prop && size < sizeof(int)); | |
200 | if (of_prop && size < sizeof(int)) | |
201 | of_prop = NULL; | |
202 | size = sizeof(struct property) + sizeof(int); | |
203 | if (of_prop == NULL) { | |
204 | if (mem_init_done) | |
205 | of_prop = kmalloc(size, GFP_KERNEL); | |
206 | else | |
207 | of_prop = alloc_bootmem(size); | |
208 | } | |
209 | memset(of_prop, 0, sizeof(struct property)); | |
210 | of_prop->name = "linux,pci-domain"; | |
211 | of_prop->length = sizeof(int); | |
212 | of_prop->value = (unsigned char *)&of_prop[1]; | |
213 | *((int *)of_prop->value) = phb->global_number; | |
214 | prom_add_property(dev, of_prop); | |
215 | } | |
216 | ||
217 | struct pci_controller * pcibios_alloc_controller(struct device_node *dev) | |
218 | { | |
219 | struct pci_controller *phb; | |
220 | ||
221 | if (mem_init_done) | |
222 | phb = kmalloc(sizeof(struct pci_controller), GFP_KERNEL); | |
223 | else | |
224 | phb = alloc_bootmem(sizeof (struct pci_controller)); | |
225 | if (phb == NULL) | |
226 | return NULL; | |
227 | pci_setup_pci_controller(phb); | |
228 | phb->arch_data = dev; | |
229 | phb->is_dynamic = mem_init_done; | |
357518fa AB |
230 | if (dev) { |
231 | PHB_SET_NODE(phb, of_node_to_nid(dev)); | |
b5166cc2 | 232 | add_linux_pci_domain(dev, phb); |
357518fa | 233 | } |
b5166cc2 BH |
234 | return phb; |
235 | } | |
236 | ||
237 | void pcibios_free_controller(struct pci_controller *phb) | |
238 | { | |
239 | if (phb->arch_data) { | |
240 | struct device_node *np = phb->arch_data; | |
241 | int *domain = (int *)get_property(np, | |
242 | "linux,pci-domain", NULL); | |
243 | if (domain) | |
244 | *domain = -1; | |
245 | } | |
246 | if (phb->is_dynamic) | |
247 | kfree(phb); | |
248 | } | |
249 | ||
9623b5d3 | 250 | #ifndef CONFIG_PPC_ISERIES |
facf0787 | 251 | void __devinit pcibios_claim_one_bus(struct pci_bus *b) |
1da177e4 LT |
252 | { |
253 | struct pci_dev *dev; | |
254 | struct pci_bus *child_bus; | |
255 | ||
256 | list_for_each_entry(dev, &b->devices, bus_list) { | |
257 | int i; | |
258 | ||
259 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
260 | struct resource *r = &dev->resource[i]; | |
261 | ||
262 | if (r->parent || !r->start || !r->flags) | |
263 | continue; | |
264 | pci_claim_resource(dev, i); | |
265 | } | |
266 | } | |
267 | ||
268 | list_for_each_entry(child_bus, &b->children, node) | |
269 | pcibios_claim_one_bus(child_bus); | |
270 | } | |
af9deabe | 271 | #ifdef CONFIG_HOTPLUG |
272 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
273 | #endif | |
1da177e4 | 274 | |
1da177e4 LT |
275 | static void __init pcibios_claim_of_setup(void) |
276 | { | |
277 | struct pci_bus *b; | |
278 | ||
279 | list_for_each_entry(b, &pci_root_buses, node) | |
280 | pcibios_claim_one_bus(b); | |
281 | } | |
282 | #endif | |
283 | ||
4267292b PM |
284 | #ifdef CONFIG_PPC_MULTIPLATFORM |
285 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) | |
286 | { | |
287 | u32 *prop; | |
288 | int len; | |
289 | ||
290 | prop = (u32 *) get_property(np, name, &len); | |
291 | if (prop && len >= 4) | |
292 | return *prop; | |
293 | return def; | |
294 | } | |
295 | ||
296 | static unsigned int pci_parse_of_flags(u32 addr0) | |
297 | { | |
298 | unsigned int flags = 0; | |
299 | ||
300 | if (addr0 & 0x02000000) { | |
d79e743e PM |
301 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; |
302 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
303 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
4267292b | 304 | if (addr0 & 0x40000000) |
d79e743e PM |
305 | flags |= IORESOURCE_PREFETCH |
306 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
4267292b | 307 | } else if (addr0 & 0x01000000) |
d79e743e | 308 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; |
4267292b PM |
309 | return flags; |
310 | } | |
311 | ||
312 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
313 | ||
314 | static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev) | |
315 | { | |
316 | u64 base, size; | |
317 | unsigned int flags; | |
318 | struct resource *res; | |
319 | u32 *addrs, i; | |
320 | int proplen; | |
321 | ||
322 | addrs = (u32 *) get_property(node, "assigned-addresses", &proplen); | |
323 | if (!addrs) | |
324 | return; | |
1beb6a7d | 325 | DBG(" parse addresses (%d bytes) @ %p\n", proplen, addrs); |
4267292b PM |
326 | for (; proplen >= 20; proplen -= 20, addrs += 5) { |
327 | flags = pci_parse_of_flags(addrs[0]); | |
328 | if (!flags) | |
329 | continue; | |
330 | base = GET_64BIT(addrs, 1); | |
331 | size = GET_64BIT(addrs, 3); | |
332 | if (!size) | |
333 | continue; | |
334 | i = addrs[0] & 0xff; | |
1beb6a7d BH |
335 | DBG(" base: %llx, size: %llx, i: %x\n", |
336 | (unsigned long long)base, (unsigned long long)size, i); | |
337 | ||
4267292b PM |
338 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { |
339 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
340 | } else if (i == dev->rom_base_reg) { | |
341 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
342 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
343 | } else { | |
344 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
345 | continue; | |
346 | } | |
347 | res->start = base; | |
348 | res->end = base + size - 1; | |
349 | res->flags = flags; | |
350 | res->name = pci_name(dev); | |
351 | fixup_resource(res, dev); | |
352 | } | |
353 | } | |
354 | ||
ead83717 JR |
355 | struct pci_dev *of_create_pci_dev(struct device_node *node, |
356 | struct pci_bus *bus, int devfn) | |
4267292b PM |
357 | { |
358 | struct pci_dev *dev; | |
359 | const char *type; | |
360 | ||
361 | dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
362 | if (!dev) | |
363 | return NULL; | |
364 | type = get_property(node, "device_type", NULL); | |
365 | if (type == NULL) | |
366 | type = ""; | |
367 | ||
1beb6a7d BH |
368 | DBG(" create device, devfn: %x, type: %s\n", devfn, type); |
369 | ||
4267292b PM |
370 | memset(dev, 0, sizeof(struct pci_dev)); |
371 | dev->bus = bus; | |
372 | dev->sysdata = node; | |
373 | dev->dev.parent = bus->bridge; | |
374 | dev->dev.bus = &pci_bus_type; | |
375 | dev->devfn = devfn; | |
376 | dev->multifunction = 0; /* maybe a lie? */ | |
377 | ||
378 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); | |
379 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
380 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
381 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
382 | ||
9d17a5c6 | 383 | dev->cfg_size = pci_cfg_space_size(dev); |
4267292b PM |
384 | |
385 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
386 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
387 | dev->class = get_int_prop(node, "class-code", 0); | |
388 | ||
1beb6a7d BH |
389 | DBG(" class: 0x%x\n", dev->class); |
390 | ||
4267292b PM |
391 | dev->current_state = 4; /* unknown power state */ |
392 | ||
bb53bb3d | 393 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
4267292b PM |
394 | /* a PCI-PCI bridge */ |
395 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
396 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
397 | } else if (!strcmp(type, "cardbus")) { | |
398 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
399 | } else { | |
400 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
401 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
402 | dev->irq = NO_IRQ; | |
403 | if (node->n_intrs > 0) { | |
404 | dev->irq = node->intrs[0].line; | |
405 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, | |
406 | dev->irq); | |
407 | } | |
408 | } | |
409 | ||
410 | pci_parse_of_addrs(node, dev); | |
411 | ||
1beb6a7d BH |
412 | DBG(" adding to system ...\n"); |
413 | ||
4267292b PM |
414 | pci_device_add(dev, bus); |
415 | ||
416 | /* XXX pci_scan_msi_device(dev); */ | |
417 | ||
418 | return dev; | |
419 | } | |
ead83717 | 420 | EXPORT_SYMBOL(of_create_pci_dev); |
4267292b | 421 | |
ead83717 | 422 | void __devinit of_scan_bus(struct device_node *node, |
4267292b PM |
423 | struct pci_bus *bus) |
424 | { | |
425 | struct device_node *child = NULL; | |
426 | u32 *reg; | |
427 | int reglen, devfn; | |
428 | struct pci_dev *dev; | |
429 | ||
1beb6a7d BH |
430 | DBG("of_scan_bus(%s) bus no %d... \n", node->full_name, bus->number); |
431 | ||
4267292b | 432 | while ((child = of_get_next_child(node, child)) != NULL) { |
1beb6a7d | 433 | DBG(" * %s\n", child->full_name); |
4267292b PM |
434 | reg = (u32 *) get_property(child, "reg", ®len); |
435 | if (reg == NULL || reglen < 20) | |
436 | continue; | |
437 | devfn = (reg[0] >> 8) & 0xff; | |
1beb6a7d | 438 | |
4267292b PM |
439 | /* create a new pci_dev for this device */ |
440 | dev = of_create_pci_dev(child, bus, devfn); | |
441 | if (!dev) | |
442 | continue; | |
1beb6a7d BH |
443 | DBG("dev header type: %x\n", dev->hdr_type); |
444 | ||
4267292b PM |
445 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
446 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
447 | of_scan_pci_bridge(child, dev); | |
448 | } | |
449 | ||
450 | do_bus_setup(bus); | |
451 | } | |
ead83717 | 452 | EXPORT_SYMBOL(of_scan_bus); |
4267292b | 453 | |
ead83717 JR |
454 | void __devinit of_scan_pci_bridge(struct device_node *node, |
455 | struct pci_dev *dev) | |
4267292b PM |
456 | { |
457 | struct pci_bus *bus; | |
458 | u32 *busrange, *ranges; | |
459 | int len, i, mode; | |
460 | struct resource *res; | |
461 | unsigned int flags; | |
462 | u64 size; | |
463 | ||
1beb6a7d BH |
464 | DBG("of_scan_pci_bridge(%s)\n", node->full_name); |
465 | ||
4267292b PM |
466 | /* parse bus-range property */ |
467 | busrange = (u32 *) get_property(node, "bus-range", &len); | |
468 | if (busrange == NULL || len != 8) { | |
1beb6a7d | 469 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", |
4267292b PM |
470 | node->full_name); |
471 | return; | |
472 | } | |
473 | ranges = (u32 *) get_property(node, "ranges", &len); | |
474 | if (ranges == NULL) { | |
1beb6a7d | 475 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", |
4267292b PM |
476 | node->full_name); |
477 | return; | |
478 | } | |
479 | ||
480 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
481 | if (!bus) { | |
482 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
483 | node->full_name); | |
484 | return; | |
485 | } | |
486 | ||
487 | bus->primary = dev->bus->number; | |
488 | bus->subordinate = busrange[1]; | |
489 | bus->bridge_ctl = 0; | |
490 | bus->sysdata = node; | |
491 | ||
492 | /* parse ranges property */ | |
493 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
494 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
495 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
496 | res->flags = 0; | |
497 | bus->resource[i] = res; | |
498 | ++res; | |
499 | } | |
500 | i = 1; | |
501 | for (; len >= 32; len -= 32, ranges += 8) { | |
502 | flags = pci_parse_of_flags(ranges[0]); | |
503 | size = GET_64BIT(ranges, 6); | |
504 | if (flags == 0 || size == 0) | |
505 | continue; | |
506 | if (flags & IORESOURCE_IO) { | |
507 | res = bus->resource[0]; | |
508 | if (res->flags) { | |
509 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
510 | " for bridge %s\n", node->full_name); | |
511 | continue; | |
512 | } | |
513 | } else { | |
514 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
515 | printk(KERN_ERR "PCI: too many memory ranges" | |
516 | " for bridge %s\n", node->full_name); | |
517 | continue; | |
518 | } | |
519 | res = bus->resource[i]; | |
520 | ++i; | |
521 | } | |
522 | res->start = GET_64BIT(ranges, 1); | |
523 | res->end = res->start + size - 1; | |
524 | res->flags = flags; | |
525 | fixup_resource(res, dev); | |
526 | } | |
527 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
528 | bus->number); | |
1beb6a7d | 529 | DBG(" bus name: %s\n", bus->name); |
4267292b PM |
530 | |
531 | mode = PCI_PROBE_NORMAL; | |
532 | if (ppc_md.pci_probe_mode) | |
533 | mode = ppc_md.pci_probe_mode(bus); | |
1beb6a7d BH |
534 | DBG(" probe mode: %d\n", mode); |
535 | ||
4267292b PM |
536 | if (mode == PCI_PROBE_DEVTREE) |
537 | of_scan_bus(node, bus); | |
538 | else if (mode == PCI_PROBE_NORMAL) | |
539 | pci_scan_child_bus(bus); | |
540 | } | |
ead83717 | 541 | EXPORT_SYMBOL(of_scan_pci_bridge); |
4267292b PM |
542 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
543 | ||
ead83717 | 544 | void __devinit scan_phb(struct pci_controller *hose) |
4267292b PM |
545 | { |
546 | struct pci_bus *bus; | |
547 | struct device_node *node = hose->arch_data; | |
548 | int i, mode; | |
549 | struct resource *res; | |
550 | ||
1beb6a7d BH |
551 | DBG("Scanning PHB %s\n", node ? node->full_name : "<NO NAME>"); |
552 | ||
4267292b PM |
553 | bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node); |
554 | if (bus == NULL) { | |
555 | printk(KERN_ERR "Failed to create bus for PCI domain %04x\n", | |
556 | hose->global_number); | |
557 | return; | |
558 | } | |
559 | bus->secondary = hose->first_busno; | |
560 | hose->bus = bus; | |
561 | ||
562 | bus->resource[0] = res = &hose->io_resource; | |
563 | if (res->flags && request_resource(&ioport_resource, res)) | |
564 | printk(KERN_ERR "Failed to request PCI IO region " | |
565 | "on PCI domain %04x\n", hose->global_number); | |
566 | ||
567 | for (i = 0; i < 3; ++i) { | |
568 | res = &hose->mem_resources[i]; | |
569 | bus->resource[i+1] = res; | |
570 | if (res->flags && request_resource(&iomem_resource, res)) | |
571 | printk(KERN_ERR "Failed to request PCI memory region " | |
572 | "on PCI domain %04x\n", hose->global_number); | |
573 | } | |
574 | ||
575 | mode = PCI_PROBE_NORMAL; | |
576 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1beb6a7d | 577 | if (node && ppc_md.pci_probe_mode) |
4267292b | 578 | mode = ppc_md.pci_probe_mode(bus); |
1beb6a7d | 579 | DBG(" probe mode: %d\n", mode); |
4267292b PM |
580 | if (mode == PCI_PROBE_DEVTREE) { |
581 | bus->subordinate = hose->last_busno; | |
582 | of_scan_bus(node, bus); | |
583 | } | |
584 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
585 | if (mode == PCI_PROBE_NORMAL) | |
586 | hose->last_busno = bus->subordinate = pci_scan_child_bus(bus); | |
4267292b PM |
587 | } |
588 | ||
1da177e4 LT |
589 | static int __init pcibios_init(void) |
590 | { | |
591 | struct pci_controller *hose, *tmp; | |
1da177e4 LT |
592 | |
593 | /* For now, override phys_mem_access_prot. If we need it, | |
594 | * later, we may move that initialization to each ppc_md | |
595 | */ | |
596 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
597 | ||
598 | #ifdef CONFIG_PPC_ISERIES | |
599 | iSeries_pcibios_init(); | |
600 | #endif | |
601 | ||
e884e9c5 | 602 | printk(KERN_DEBUG "PCI: Probing PCI hardware\n"); |
1da177e4 LT |
603 | |
604 | /* Scan all of the recorded PCI controllers. */ | |
92eb4602 | 605 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
4267292b | 606 | scan_phb(hose); |
92eb4602 JR |
607 | pci_bus_add_devices(hose->bus); |
608 | } | |
1da177e4 LT |
609 | |
610 | #ifndef CONFIG_PPC_ISERIES | |
611 | if (pci_probe_only) | |
612 | pcibios_claim_of_setup(); | |
613 | else | |
614 | /* FIXME: `else' will be removed when | |
615 | pci_assign_unassigned_resources() is able to work | |
616 | correctly with [partially] allocated PCI tree. */ | |
617 | pci_assign_unassigned_resources(); | |
618 | #endif /* !CONFIG_PPC_ISERIES */ | |
619 | ||
620 | /* Call machine dependent final fixup */ | |
621 | if (ppc_md.pcibios_fixup) | |
622 | ppc_md.pcibios_fixup(); | |
623 | ||
624 | /* Cache the location of the ISA bridge (if we have one) */ | |
625 | ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
626 | if (ppc64_isabridge_dev != NULL) | |
e884e9c5 | 627 | printk(KERN_DEBUG "ISA bridge at %s\n", pci_name(ppc64_isabridge_dev)); |
1da177e4 | 628 | |
fe360cdf | 629 | #ifdef CONFIG_PPC_MULTIPLATFORM |
0f34f490 BH |
630 | /* map in PCI I/O space */ |
631 | phbs_remap_io(); | |
fe360cdf | 632 | #endif |
0f34f490 | 633 | |
e884e9c5 | 634 | printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); |
1da177e4 LT |
635 | |
636 | return 0; | |
637 | } | |
638 | ||
639 | subsys_initcall(pcibios_init); | |
640 | ||
641 | char __init *pcibios_setup(char *str) | |
642 | { | |
643 | return str; | |
644 | } | |
645 | ||
646 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
647 | { | |
648 | u16 cmd, oldcmd; | |
649 | int i; | |
650 | ||
651 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
652 | oldcmd = cmd; | |
653 | ||
654 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
655 | struct resource *res = &dev->resource[i]; | |
656 | ||
657 | /* Only set up the requested stuff */ | |
658 | if (!(mask & (1<<i))) | |
659 | continue; | |
660 | ||
661 | if (res->flags & IORESOURCE_IO) | |
662 | cmd |= PCI_COMMAND_IO; | |
663 | if (res->flags & IORESOURCE_MEM) | |
664 | cmd |= PCI_COMMAND_MEMORY; | |
665 | } | |
666 | ||
667 | if (cmd != oldcmd) { | |
668 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
669 | pci_name(dev), cmd); | |
670 | /* Enable the appropriate bits in the PCI command register. */ | |
671 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
672 | } | |
673 | return 0; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Return the domain number for this bus. | |
678 | */ | |
679 | int pci_domain_nr(struct pci_bus *bus) | |
680 | { | |
681 | #ifdef CONFIG_PPC_ISERIES | |
682 | return 0; | |
683 | #else | |
684 | struct pci_controller *hose = pci_bus_to_host(bus); | |
685 | ||
686 | return hose->global_number; | |
687 | #endif | |
688 | } | |
689 | ||
690 | EXPORT_SYMBOL(pci_domain_nr); | |
691 | ||
692 | /* Decide whether to display the domain number in /proc */ | |
693 | int pci_proc_domain(struct pci_bus *bus) | |
694 | { | |
695 | #ifdef CONFIG_PPC_ISERIES | |
696 | return 0; | |
697 | #else | |
698 | struct pci_controller *hose = pci_bus_to_host(bus); | |
699 | return hose->buid; | |
700 | #endif | |
701 | } | |
702 | ||
703 | /* | |
704 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
705 | * modelled on the sparc64 implementation by Dave Miller. | |
706 | * -- paulus. | |
707 | */ | |
708 | ||
709 | /* | |
710 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
711 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
712 | * | |
713 | * Basically, the user finds the base address for his device which he wishes | |
714 | * to mmap. They read the 32-bit value from the config space base register, | |
715 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
716 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
717 | * | |
718 | * Returns negative error code on failure, zero on success. | |
719 | */ | |
720 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
721 | unsigned long *offset, | |
722 | enum pci_mmap_state mmap_state) | |
723 | { | |
724 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
725 | unsigned long io_offset = 0; | |
726 | int i, res_bit; | |
727 | ||
728 | if (hose == 0) | |
729 | return NULL; /* should never happen */ | |
730 | ||
731 | /* If memory, add on the PCI bridge address offset */ | |
732 | if (mmap_state == pci_mmap_mem) { | |
733 | *offset += hose->pci_mem_offset; | |
734 | res_bit = IORESOURCE_MEM; | |
735 | } else { | |
2311b1f2 | 736 | io_offset = (unsigned long)hose->io_base_virt - pci_io_base; |
1da177e4 LT |
737 | *offset += io_offset; |
738 | res_bit = IORESOURCE_IO; | |
739 | } | |
740 | ||
741 | /* | |
742 | * Check that the offset requested corresponds to one of the | |
743 | * resources of the device. | |
744 | */ | |
745 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
746 | struct resource *rp = &dev->resource[i]; | |
747 | int flags = rp->flags; | |
748 | ||
749 | /* treat ROM as memory (should be already) */ | |
750 | if (i == PCI_ROM_RESOURCE) | |
751 | flags |= IORESOURCE_MEM; | |
752 | ||
753 | /* Active and same type? */ | |
754 | if ((flags & res_bit) == 0) | |
755 | continue; | |
756 | ||
757 | /* In the range of this resource? */ | |
758 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
759 | continue; | |
760 | ||
761 | /* found it! construct the final physical address */ | |
762 | if (mmap_state == pci_mmap_io) | |
2311b1f2 | 763 | *offset += hose->io_base_phys - io_offset; |
1da177e4 LT |
764 | return rp; |
765 | } | |
766 | ||
767 | return NULL; | |
768 | } | |
769 | ||
770 | /* | |
771 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
772 | * device mapping. | |
773 | */ | |
774 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
775 | pgprot_t protection, | |
776 | enum pci_mmap_state mmap_state, | |
777 | int write_combine) | |
778 | { | |
779 | unsigned long prot = pgprot_val(protection); | |
780 | ||
781 | /* Write combine is always 0 on non-memory space mappings. On | |
782 | * memory space, if the user didn't pass 1, we check for a | |
783 | * "prefetchable" resource. This is a bit hackish, but we use | |
784 | * this to workaround the inability of /sysfs to provide a write | |
785 | * combine bit | |
786 | */ | |
787 | if (mmap_state != pci_mmap_mem) | |
788 | write_combine = 0; | |
789 | else if (write_combine == 0) { | |
790 | if (rp->flags & IORESOURCE_PREFETCH) | |
791 | write_combine = 1; | |
792 | } | |
793 | ||
794 | /* XXX would be nice to have a way to ask for write-through */ | |
795 | prot |= _PAGE_NO_CACHE; | |
796 | if (write_combine) | |
797 | prot &= ~_PAGE_GUARDED; | |
798 | else | |
799 | prot |= _PAGE_GUARDED; | |
800 | ||
e884e9c5 | 801 | printk(KERN_DEBUG "PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start, |
1da177e4 LT |
802 | prot); |
803 | ||
804 | return __pgprot(prot); | |
805 | } | |
806 | ||
807 | /* | |
808 | * This one is used by /dev/mem and fbdev who have no clue about the | |
809 | * PCI device, it tries to find the PCI device first and calls the | |
810 | * above routine | |
811 | */ | |
812 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 813 | unsigned long pfn, |
1da177e4 LT |
814 | unsigned long size, |
815 | pgprot_t protection) | |
816 | { | |
817 | struct pci_dev *pdev = NULL; | |
818 | struct resource *found = NULL; | |
819 | unsigned long prot = pgprot_val(protection); | |
8b150478 | 820 | unsigned long offset = pfn << PAGE_SHIFT; |
1da177e4 LT |
821 | int i; |
822 | ||
8b150478 | 823 | if (page_is_ram(pfn)) |
1f8d419e | 824 | return __pgprot(prot); |
1da177e4 LT |
825 | |
826 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
827 | ||
828 | for_each_pci_dev(pdev) { | |
829 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
830 | struct resource *rp = &pdev->resource[i]; | |
831 | int flags = rp->flags; | |
832 | ||
833 | /* Active and same type? */ | |
834 | if ((flags & IORESOURCE_MEM) == 0) | |
835 | continue; | |
836 | /* In the range of this resource? */ | |
837 | if (offset < (rp->start & PAGE_MASK) || | |
838 | offset > rp->end) | |
839 | continue; | |
840 | found = rp; | |
841 | break; | |
842 | } | |
843 | if (found) | |
844 | break; | |
845 | } | |
846 | if (found) { | |
847 | if (found->flags & IORESOURCE_PREFETCH) | |
848 | prot &= ~_PAGE_GUARDED; | |
849 | pci_dev_put(pdev); | |
850 | } | |
851 | ||
852 | DBG("non-PCI map for %lx, prot: %lx\n", offset, prot); | |
853 | ||
854 | return __pgprot(prot); | |
855 | } | |
856 | ||
857 | ||
858 | /* | |
859 | * Perform the actual remap of the pages for a PCI device mapping, as | |
860 | * appropriate for this architecture. The region in the process to map | |
861 | * is described by vm_start and vm_end members of VMA, the base physical | |
862 | * address is found in vm_pgoff. | |
863 | * The pci device structure is provided so that architectures may make mapping | |
864 | * decisions on a per-device or per-bus basis. | |
865 | * | |
866 | * Returns a negative error code on failure, zero on success. | |
867 | */ | |
868 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1beb6a7d | 869 | enum pci_mmap_state mmap_state, int write_combine) |
1da177e4 LT |
870 | { |
871 | unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; | |
872 | struct resource *rp; | |
873 | int ret; | |
874 | ||
875 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
876 | if (rp == NULL) | |
877 | return -EINVAL; | |
878 | ||
879 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
1da177e4 LT |
880 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, |
881 | vma->vm_page_prot, | |
882 | mmap_state, write_combine); | |
883 | ||
884 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
885 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
886 | ||
887 | return ret; | |
888 | } | |
889 | ||
efbd3869 SR |
890 | static ssize_t pci_show_devspec(struct device *dev, |
891 | struct device_attribute *attr, char *buf) | |
1da177e4 LT |
892 | { |
893 | struct pci_dev *pdev; | |
894 | struct device_node *np; | |
895 | ||
896 | pdev = to_pci_dev (dev); | |
897 | np = pci_device_to_OF_node(pdev); | |
898 | if (np == NULL || np->full_name == NULL) | |
899 | return 0; | |
900 | return sprintf(buf, "%s", np->full_name); | |
901 | } | |
902 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
1da177e4 LT |
903 | |
904 | void pcibios_add_platform_entries(struct pci_dev *pdev) | |
905 | { | |
1da177e4 | 906 | device_create_file(&pdev->dev, &dev_attr_devspec); |
1da177e4 LT |
907 | } |
908 | ||
909 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
910 | ||
911 | #define ISA_SPACE_MASK 0x1 | |
912 | #define ISA_SPACE_IO 0x1 | |
913 | ||
914 | static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node, | |
915 | unsigned long phb_io_base_phys, | |
916 | void __iomem * phb_io_base_virt) | |
917 | { | |
cc5d0189 BH |
918 | /* Remove these asap */ |
919 | ||
920 | struct pci_address { | |
921 | u32 a_hi; | |
922 | u32 a_mid; | |
923 | u32 a_lo; | |
924 | }; | |
925 | ||
926 | struct isa_address { | |
927 | u32 a_hi; | |
928 | u32 a_lo; | |
929 | }; | |
930 | ||
931 | struct isa_range { | |
932 | struct isa_address isa_addr; | |
933 | struct pci_address pci_addr; | |
934 | unsigned int size; | |
935 | }; | |
936 | ||
1da177e4 LT |
937 | struct isa_range *range; |
938 | unsigned long pci_addr; | |
939 | unsigned int isa_addr; | |
940 | unsigned int size; | |
941 | int rlen = 0; | |
942 | ||
943 | range = (struct isa_range *) get_property(isa_node, "ranges", &rlen); | |
944 | if (range == NULL || (rlen < sizeof(struct isa_range))) { | |
945 | printk(KERN_ERR "no ISA ranges or unexpected isa range size," | |
946 | "mapping 64k\n"); | |
dfbacdc1 BH |
947 | __ioremap_explicit(phb_io_base_phys, |
948 | (unsigned long)phb_io_base_virt, | |
949 | 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED); | |
1da177e4 LT |
950 | return; |
951 | } | |
952 | ||
953 | /* From "ISA Binding to 1275" | |
954 | * The ranges property is laid out as an array of elements, | |
955 | * each of which comprises: | |
956 | * cells 0 - 1: an ISA address | |
957 | * cells 2 - 4: a PCI address | |
958 | * (size depending on dev->n_addr_cells) | |
959 | * cell 5: the size of the range | |
960 | */ | |
961 | if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) { | |
962 | isa_addr = range->isa_addr.a_lo; | |
963 | pci_addr = (unsigned long) range->pci_addr.a_mid << 32 | | |
964 | range->pci_addr.a_lo; | |
965 | ||
966 | /* Assume these are both zero */ | |
967 | if ((pci_addr != 0) || (isa_addr != 0)) { | |
968 | printk(KERN_ERR "unexpected isa to pci mapping: %s\n", | |
969 | __FUNCTION__); | |
970 | return; | |
971 | } | |
972 | ||
973 | size = PAGE_ALIGN(range->size); | |
974 | ||
975 | __ioremap_explicit(phb_io_base_phys, | |
976 | (unsigned long) phb_io_base_virt, | |
dfbacdc1 | 977 | size, _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
978 | } |
979 | } | |
980 | ||
981 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
f7abbc19 | 982 | struct device_node *dev, int prim) |
1da177e4 | 983 | { |
f7abbc19 | 984 | unsigned int *ranges, pci_space; |
1da177e4 LT |
985 | unsigned long size; |
986 | int rlen = 0; | |
987 | int memno = 0; | |
988 | struct resource *res; | |
989 | int np, na = prom_n_addr_cells(dev); | |
990 | unsigned long pci_addr, cpu_phys_addr; | |
991 | ||
992 | np = na + 5; | |
993 | ||
994 | /* From "PCI Binding to 1275" | |
995 | * The ranges property is laid out as an array of elements, | |
996 | * each of which comprises: | |
997 | * cells 0 - 2: a PCI address | |
998 | * cells 3 or 3+4: a CPU physical address | |
999 | * (size depending on dev->n_addr_cells) | |
1000 | * cells 4+5 or 5+6: the size of the range | |
1001 | */ | |
1da177e4 | 1002 | ranges = (unsigned int *) get_property(dev, "ranges", &rlen); |
b5166cc2 BH |
1003 | if (ranges == NULL) |
1004 | return; | |
1005 | hose->io_base_phys = 0; | |
1da177e4 LT |
1006 | while ((rlen -= np * sizeof(unsigned int)) >= 0) { |
1007 | res = NULL; | |
f7abbc19 PM |
1008 | pci_space = ranges[0]; |
1009 | pci_addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
1da177e4 LT |
1010 | |
1011 | cpu_phys_addr = ranges[3]; | |
f7abbc19 PM |
1012 | if (na >= 2) |
1013 | cpu_phys_addr = (cpu_phys_addr << 32) | ranges[4]; | |
1da177e4 | 1014 | |
f7abbc19 PM |
1015 | size = ((unsigned long)ranges[na+3] << 32) | ranges[na+4]; |
1016 | ranges += np; | |
1da177e4 LT |
1017 | if (size == 0) |
1018 | continue; | |
f7abbc19 PM |
1019 | |
1020 | /* Now consume following elements while they are contiguous */ | |
1021 | while (rlen >= np * sizeof(unsigned int)) { | |
1022 | unsigned long addr, phys; | |
1023 | ||
1024 | if (ranges[0] != pci_space) | |
1025 | break; | |
1026 | addr = ((unsigned long)ranges[1] << 32) | ranges[2]; | |
1027 | phys = ranges[3]; | |
1028 | if (na >= 2) | |
1029 | phys = (phys << 32) | ranges[4]; | |
1030 | if (addr != pci_addr + size || | |
1031 | phys != cpu_phys_addr + size) | |
1032 | break; | |
1033 | ||
1034 | size += ((unsigned long)ranges[na+3] << 32) | |
1035 | | ranges[na+4]; | |
1036 | ranges += np; | |
1037 | rlen -= np * sizeof(unsigned int); | |
1038 | } | |
1039 | ||
1040 | switch ((pci_space >> 24) & 0x3) { | |
1da177e4 LT |
1041 | case 1: /* I/O space */ |
1042 | hose->io_base_phys = cpu_phys_addr; | |
1043 | hose->pci_io_size = size; | |
1044 | ||
1045 | res = &hose->io_resource; | |
1046 | res->flags = IORESOURCE_IO; | |
1047 | res->start = pci_addr; | |
1048 | DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number, | |
1049 | res->start, res->start + size - 1); | |
1050 | break; | |
1051 | case 2: /* memory space */ | |
1052 | memno = 0; | |
1053 | while (memno < 3 && hose->mem_resources[memno].flags) | |
1054 | ++memno; | |
1055 | ||
1056 | if (memno == 0) | |
1057 | hose->pci_mem_offset = cpu_phys_addr - pci_addr; | |
1058 | if (memno < 3) { | |
1059 | res = &hose->mem_resources[memno]; | |
1060 | res->flags = IORESOURCE_MEM; | |
1061 | res->start = cpu_phys_addr; | |
1062 | DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number, | |
1063 | res->start, res->start + size - 1); | |
1064 | } | |
1065 | break; | |
1066 | } | |
1067 | if (res != NULL) { | |
1068 | res->name = dev->full_name; | |
1069 | res->end = res->start + size - 1; | |
1070 | res->parent = NULL; | |
1071 | res->sibling = NULL; | |
1072 | res->child = NULL; | |
1073 | } | |
1da177e4 LT |
1074 | } |
1075 | } | |
1076 | ||
1077 | void __init pci_setup_phb_io(struct pci_controller *hose, int primary) | |
1078 | { | |
1079 | unsigned long size = hose->pci_io_size; | |
1080 | unsigned long io_virt_offset; | |
1081 | struct resource *res; | |
1082 | struct device_node *isa_dn; | |
1083 | ||
1084 | hose->io_base_virt = reserve_phb_iospace(size); | |
1085 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", | |
1086 | hose->global_number, hose->io_base_phys, | |
1087 | (unsigned long) hose->io_base_virt); | |
1088 | ||
1089 | if (primary) { | |
1090 | pci_io_base = (unsigned long)hose->io_base_virt; | |
1091 | isa_dn = of_find_node_by_type(NULL, "isa"); | |
1092 | if (isa_dn) { | |
1093 | isa_io_base = pci_io_base; | |
1094 | pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys, | |
1095 | hose->io_base_virt); | |
1096 | of_node_put(isa_dn); | |
1da177e4 LT |
1097 | } |
1098 | } | |
1099 | ||
1100 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1101 | res = &hose->io_resource; | |
1102 | res->start += io_virt_offset; | |
1103 | res->end += io_virt_offset; | |
1104 | } | |
1105 | ||
1106 | void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose, | |
1107 | int primary) | |
1108 | { | |
1109 | unsigned long size = hose->pci_io_size; | |
1110 | unsigned long io_virt_offset; | |
1111 | struct resource *res; | |
1112 | ||
1113 | hose->io_base_virt = __ioremap(hose->io_base_phys, size, | |
dfbacdc1 | 1114 | _PAGE_NO_CACHE | _PAGE_GUARDED); |
1da177e4 LT |
1115 | DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n", |
1116 | hose->global_number, hose->io_base_phys, | |
1117 | (unsigned long) hose->io_base_virt); | |
1118 | ||
1119 | if (primary) | |
1120 | pci_io_base = (unsigned long)hose->io_base_virt; | |
1121 | ||
1122 | io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1123 | res = &hose->io_resource; | |
1124 | res->start += io_virt_offset; | |
1125 | res->end += io_virt_offset; | |
1126 | } | |
1127 | ||
1128 | ||
1129 | static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys, | |
1130 | unsigned long *start_virt, unsigned long *size) | |
1131 | { | |
1132 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1133 | struct pci_bus_region region; | |
1134 | struct resource *res; | |
1135 | ||
1136 | if (bus->self) { | |
1137 | res = bus->resource[0]; | |
1138 | pcibios_resource_to_bus(bus->self, ®ion, res); | |
1139 | *start_phys = hose->io_base_phys + region.start; | |
1140 | *start_virt = (unsigned long) hose->io_base_virt + | |
1141 | region.start; | |
1142 | if (region.end > region.start) | |
1143 | *size = region.end - region.start + 1; | |
1144 | else { | |
1145 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1146 | __FUNCTION__, region.start, region.end); | |
1147 | return 1; | |
1148 | } | |
1149 | ||
1150 | } else { | |
1151 | /* Root Bus */ | |
1152 | res = &hose->io_resource; | |
1153 | *start_phys = hose->io_base_phys; | |
1154 | *start_virt = (unsigned long) hose->io_base_virt; | |
1155 | if (res->end > res->start) | |
1156 | *size = res->end - res->start + 1; | |
1157 | else { | |
1158 | printk("%s(): unexpected region 0x%lx->0x%lx\n", | |
1159 | __FUNCTION__, res->start, res->end); | |
1160 | return 1; | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | int unmap_bus_range(struct pci_bus *bus) | |
1168 | { | |
1169 | unsigned long start_phys; | |
1170 | unsigned long start_virt; | |
1171 | unsigned long size; | |
1172 | ||
1173 | if (!bus) { | |
1174 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1175 | return 1; | |
1176 | } | |
1177 | ||
1178 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1179 | return 1; | |
1180 | if (iounmap_explicit((void __iomem *) start_virt, size)) | |
1181 | return 1; | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | EXPORT_SYMBOL(unmap_bus_range); | |
1186 | ||
1187 | int remap_bus_range(struct pci_bus *bus) | |
1188 | { | |
1189 | unsigned long start_phys; | |
1190 | unsigned long start_virt; | |
1191 | unsigned long size; | |
1192 | ||
1193 | if (!bus) { | |
1194 | printk(KERN_ERR "%s() expected bus\n", __FUNCTION__); | |
1195 | return 1; | |
1196 | } | |
1197 | ||
1198 | ||
1199 | if (get_bus_io_range(bus, &start_phys, &start_virt, &size)) | |
1200 | return 1; | |
b5166cc2 BH |
1201 | if (start_phys == 0) |
1202 | return 1; | |
e884e9c5 | 1203 | printk(KERN_DEBUG "mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size); |
dfbacdc1 BH |
1204 | if (__ioremap_explicit(start_phys, start_virt, size, |
1205 | _PAGE_NO_CACHE | _PAGE_GUARDED)) | |
1da177e4 LT |
1206 | return 1; |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | EXPORT_SYMBOL(remap_bus_range); | |
1211 | ||
9623b5d3 | 1212 | static void phbs_remap_io(void) |
1da177e4 LT |
1213 | { |
1214 | struct pci_controller *hose, *tmp; | |
1215 | ||
1216 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1217 | remap_bus_range(hose->bus); | |
1218 | } | |
1219 | ||
4267292b PM |
1220 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) |
1221 | { | |
1222 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
c256f4b9 | 1223 | unsigned long offset; |
1da177e4 | 1224 | |
4267292b PM |
1225 | if (res->flags & IORESOURCE_IO) { |
1226 | offset = (unsigned long)hose->io_base_virt - pci_io_base; | |
1da177e4 | 1227 | |
c256f4b9 AB |
1228 | res->start += offset; |
1229 | res->end += offset; | |
4267292b PM |
1230 | } else if (res->flags & IORESOURCE_MEM) { |
1231 | res->start += hose->pci_mem_offset; | |
1232 | res->end += hose->pci_mem_offset; | |
1233 | } | |
1234 | } | |
1da177e4 LT |
1235 | |
1236 | void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, | |
4267292b | 1237 | struct pci_bus *bus) |
1da177e4 LT |
1238 | { |
1239 | /* Update device resources. */ | |
1da177e4 LT |
1240 | int i; |
1241 | ||
4267292b PM |
1242 | for (i = 0; i < PCI_NUM_RESOURCES; i++) |
1243 | if (dev->resource[i].flags) | |
1244 | fixup_resource(&dev->resource[i], dev); | |
1da177e4 LT |
1245 | } |
1246 | EXPORT_SYMBOL(pcibios_fixup_device_resources); | |
1247 | ||
463ce0e1 | 1248 | |
4267292b | 1249 | static void __devinit do_bus_setup(struct pci_bus *bus) |
1da177e4 | 1250 | { |
4267292b | 1251 | struct pci_dev *dev; |
1da177e4 | 1252 | |
4267292b | 1253 | ppc_md.iommu_bus_setup(bus); |
1da177e4 | 1254 | |
4267292b PM |
1255 | list_for_each_entry(dev, &bus->devices, bus_list) |
1256 | ppc_md.iommu_dev_setup(dev); | |
1da177e4 | 1257 | |
4267292b PM |
1258 | if (ppc_md.irq_bus_setup) |
1259 | ppc_md.irq_bus_setup(bus); | |
1260 | } | |
1da177e4 | 1261 | |
4267292b PM |
1262 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) |
1263 | { | |
1264 | struct pci_dev *dev = bus->self; | |
1265 | ||
1266 | if (dev && pci_probe_only && | |
1267 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1da177e4 LT |
1268 | /* This is a subordinate bridge */ |
1269 | ||
1270 | pci_read_bridge_bases(bus); | |
1271 | pcibios_fixup_device_resources(dev, bus); | |
1272 | } | |
1273 | ||
4267292b | 1274 | do_bus_setup(bus); |
dad32bbf | 1275 | |
1da177e4 LT |
1276 | if (!pci_probe_only) |
1277 | return; | |
1278 | ||
4267292b | 1279 | list_for_each_entry(dev, &bus->devices, bus_list) |
1da177e4 LT |
1280 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) |
1281 | pcibios_fixup_device_resources(dev, bus); | |
1da177e4 LT |
1282 | } |
1283 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
1284 | ||
1285 | /* | |
1286 | * Reads the interrupt pin to determine if interrupt is use by card. | |
1287 | * If the interrupt is used, then gets the interrupt line from the | |
1288 | * openfirmware and sets it in the pci_dev and pci_config line. | |
1289 | */ | |
1290 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
1291 | { | |
1292 | u8 intpin; | |
1293 | struct device_node *node; | |
1294 | ||
1295 | pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin); | |
1296 | if (intpin == 0) | |
1297 | return 0; | |
1298 | ||
1299 | node = pci_device_to_OF_node(pci_dev); | |
1300 | if (node == NULL) | |
1301 | return -1; | |
1302 | ||
1303 | if (node->n_intrs == 0) | |
1304 | return -1; | |
1305 | ||
1306 | pci_dev->irq = node->intrs[0].line; | |
1307 | ||
1308 | pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq); | |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | EXPORT_SYMBOL(pci_read_irq_line); | |
1313 | ||
2311b1f2 ME |
1314 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
1315 | const struct resource *rsrc, | |
1316 | u64 *start, u64 *end) | |
1317 | { | |
1318 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
1319 | unsigned long offset = 0; | |
1320 | ||
1321 | if (hose == NULL) | |
1322 | return; | |
1323 | ||
1324 | if (rsrc->flags & IORESOURCE_IO) | |
1325 | offset = pci_io_base - (unsigned long)hose->io_base_virt + | |
1326 | hose->io_base_phys; | |
1327 | ||
1328 | *start = rsrc->start + offset; | |
1329 | *end = rsrc->end + offset; | |
1330 | } | |
1331 | ||
463ce0e1 BH |
1332 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) |
1333 | { | |
1334 | if (!have_of) | |
1335 | return NULL; | |
1336 | while(node) { | |
1337 | struct pci_controller *hose, *tmp; | |
1338 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
1339 | if (hose->arch_data == node) | |
1340 | return hose; | |
1341 | node = node->parent; | |
1342 | } | |
1343 | return NULL; | |
1344 | } | |
1345 | ||
1da177e4 | 1346 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
b2ad7b5e | 1347 | |
f2c4583a | 1348 | unsigned long pci_address_to_pio(phys_addr_t address) |
d4e4b352 SR |
1349 | { |
1350 | struct pci_controller *hose, *tmp; | |
1351 | ||
1352 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { | |
1353 | if (address >= hose->io_base_phys && | |
f2c4583a BH |
1354 | address < (hose->io_base_phys + hose->pci_io_size)) { |
1355 | unsigned long base = | |
1356 | (unsigned long)hose->io_base_virt - pci_io_base; | |
1357 | return base + (address - hose->io_base_phys); | |
1358 | } | |
d4e4b352 SR |
1359 | } |
1360 | return (unsigned int)-1; | |
1361 | } | |
1362 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
1363 | ||
b2ad7b5e PM |
1364 | |
1365 | #define IOBASE_BRIDGE_NUMBER 0 | |
1366 | #define IOBASE_MEMORY 1 | |
1367 | #define IOBASE_IO 2 | |
1368 | #define IOBASE_ISA_IO 3 | |
1369 | #define IOBASE_ISA_MEM 4 | |
1370 | ||
1371 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
1372 | unsigned long in_devfn) | |
1373 | { | |
1374 | struct pci_controller* hose; | |
1375 | struct list_head *ln; | |
1376 | struct pci_bus *bus = NULL; | |
1377 | struct device_node *hose_node; | |
1378 | ||
1379 | /* Argh ! Please forgive me for that hack, but that's the | |
1380 | * simplest way to get existing XFree to not lockup on some | |
1381 | * G5 machines... So when something asks for bus 0 io base | |
1382 | * (bus 0 is HT root), we return the AGP one instead. | |
1383 | */ | |
799d6046 | 1384 | if (machine_is_compatible("MacRISC4")) |
b2ad7b5e PM |
1385 | if (in_bus == 0) |
1386 | in_bus = 0xf0; | |
b2ad7b5e PM |
1387 | |
1388 | /* That syscall isn't quite compatible with PCI domains, but it's | |
1389 | * used on pre-domains setup. We return the first match | |
1390 | */ | |
1391 | ||
1392 | for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { | |
1393 | bus = pci_bus_b(ln); | |
1394 | if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate)) | |
1395 | break; | |
1396 | bus = NULL; | |
1397 | } | |
1398 | if (bus == NULL || bus->sysdata == NULL) | |
1399 | return -ENODEV; | |
1400 | ||
1401 | hose_node = (struct device_node *)bus->sysdata; | |
1402 | hose = PCI_DN(hose_node)->phb; | |
1403 | ||
1404 | switch (which) { | |
1405 | case IOBASE_BRIDGE_NUMBER: | |
1406 | return (long)hose->first_busno; | |
1407 | case IOBASE_MEMORY: | |
1408 | return (long)hose->pci_mem_offset; | |
1409 | case IOBASE_IO: | |
1410 | return (long)hose->io_base_phys; | |
1411 | case IOBASE_ISA_IO: | |
1412 | return (long)isa_io_base; | |
1413 | case IOBASE_ISA_MEM: | |
1414 | return -EINVAL; | |
1415 | } | |
1416 | ||
1417 | return -EOPNOTSUPP; | |
1418 | } | |
357518fa AB |
1419 | |
1420 | #ifdef CONFIG_NUMA | |
1421 | int pcibus_to_node(struct pci_bus *bus) | |
1422 | { | |
1423 | struct pci_controller *phb = pci_bus_to_host(bus); | |
1424 | return phb->node; | |
1425 | } | |
1426 | EXPORT_SYMBOL(pcibus_to_node); | |
1427 | #endif |