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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
cdd6c482 IM |
22 | struct cpu_hw_events { |
23 | int n_events; | |
4574910e PM |
24 | int n_percpu; |
25 | int disabled; | |
26 | int n_added; | |
ab7ef2e5 PM |
27 | int n_limited; |
28 | u8 pmcs_enabled; | |
cdd6c482 IM |
29 | struct perf_event *event[MAX_HWEVENTS]; |
30 | u64 events[MAX_HWEVENTS]; | |
31 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 32 | unsigned long mmcr[3]; |
a8f90e90 PM |
33 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
34 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
35 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
36 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
37 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
38 | |
39 | unsigned int group_flag; | |
40 | int n_txn_start; | |
4574910e | 41 | }; |
cdd6c482 | 42 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
43 | |
44 | struct power_pmu *ppmu; | |
45 | ||
d095cd46 | 46 | /* |
57c0c15b | 47 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
48 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
49 | * hypervisor bit set in the MSR, or if we are running on a processor | |
50 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
51 | * then we need to use the FCHV bit to ignore kernel events. | |
52 | */ | |
cdd6c482 | 53 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 54 | |
98fb1807 PM |
55 | /* |
56 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
57 | * and a few other names are different. | |
58 | */ | |
59 | #ifdef CONFIG_PPC32 | |
60 | ||
61 | #define MMCR0_FCHV 0 | |
62 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
63 | ||
64 | #define SPRN_MMCRA SPRN_MMCR2 | |
65 | #define MMCRA_SAMPLE_ENABLE 0 | |
66 | ||
67 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
68 | { | |
69 | return 0; | |
70 | } | |
98fb1807 PM |
71 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
72 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
73 | { | |
74 | return 0; | |
75 | } | |
76 | static inline void perf_read_regs(struct pt_regs *regs) { } | |
77 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
78 | { | |
79 | return 0; | |
80 | } | |
81 | ||
82 | #endif /* CONFIG_PPC32 */ | |
83 | ||
84 | /* | |
85 | * Things that are specific to 64-bit implementations. | |
86 | */ | |
87 | #ifdef CONFIG_PPC64 | |
88 | ||
89 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
90 | { | |
91 | unsigned long mmcra = regs->dsisr; | |
92 | ||
93 | if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { | |
94 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; | |
95 | if (slot > 1) | |
96 | return 4 * (slot - 1); | |
97 | } | |
98 | return 0; | |
99 | } | |
100 | ||
98fb1807 PM |
101 | /* |
102 | * The user wants a data address recorded. | |
103 | * If we're not doing instruction sampling, give them the SDAR | |
104 | * (sampled data address). If we are doing instruction sampling, then | |
105 | * only give them the SDAR if it corresponds to the instruction | |
106 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC | |
107 | * bit in MMCRA. | |
108 | */ | |
109 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
110 | { | |
111 | unsigned long mmcra = regs->dsisr; | |
112 | unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? | |
113 | POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; | |
114 | ||
115 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
116 | *addrp = mfspr(SPRN_SDAR); | |
117 | } | |
118 | ||
119 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
120 | { | |
121 | unsigned long mmcra = regs->dsisr; | |
7abb840b MN |
122 | unsigned long sihv = MMCRA_SIHV; |
123 | unsigned long sipr = MMCRA_SIPR; | |
98fb1807 PM |
124 | |
125 | if (TRAP(regs) != 0xf00) | |
126 | return 0; /* not a PMU interrupt */ | |
127 | ||
128 | if (ppmu->flags & PPMU_ALT_SIPR) { | |
7abb840b MN |
129 | sihv = POWER6_MMCRA_SIHV; |
130 | sipr = POWER6_MMCRA_SIPR; | |
98fb1807 | 131 | } |
7abb840b MN |
132 | |
133 | /* PR has priority over HV, so order below is important */ | |
134 | if (mmcra & sipr) | |
135 | return PERF_RECORD_MISC_USER; | |
136 | if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 137 | return PERF_RECORD_MISC_HYPERVISOR; |
7abb840b | 138 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
139 | } |
140 | ||
141 | /* | |
142 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
143 | * on each interrupt. | |
144 | */ | |
145 | static inline void perf_read_regs(struct pt_regs *regs) | |
146 | { | |
147 | regs->dsisr = mfspr(SPRN_MMCRA); | |
148 | } | |
149 | ||
150 | /* | |
151 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
152 | * it as an NMI. | |
153 | */ | |
154 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
155 | { | |
156 | return !regs->softe; | |
157 | } | |
158 | ||
159 | #endif /* CONFIG_PPC64 */ | |
160 | ||
cdd6c482 | 161 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 162 | |
cdd6c482 | 163 | void perf_event_print_debug(void) |
4574910e PM |
164 | { |
165 | } | |
166 | ||
4574910e | 167 | /* |
57c0c15b | 168 | * Read one performance monitor counter (PMC). |
4574910e PM |
169 | */ |
170 | static unsigned long read_pmc(int idx) | |
171 | { | |
172 | unsigned long val; | |
173 | ||
174 | switch (idx) { | |
175 | case 1: | |
176 | val = mfspr(SPRN_PMC1); | |
177 | break; | |
178 | case 2: | |
179 | val = mfspr(SPRN_PMC2); | |
180 | break; | |
181 | case 3: | |
182 | val = mfspr(SPRN_PMC3); | |
183 | break; | |
184 | case 4: | |
185 | val = mfspr(SPRN_PMC4); | |
186 | break; | |
187 | case 5: | |
188 | val = mfspr(SPRN_PMC5); | |
189 | break; | |
190 | case 6: | |
191 | val = mfspr(SPRN_PMC6); | |
192 | break; | |
98fb1807 | 193 | #ifdef CONFIG_PPC64 |
4574910e PM |
194 | case 7: |
195 | val = mfspr(SPRN_PMC7); | |
196 | break; | |
197 | case 8: | |
198 | val = mfspr(SPRN_PMC8); | |
199 | break; | |
98fb1807 | 200 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
201 | default: |
202 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
203 | val = 0; | |
204 | } | |
205 | return val; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Write one PMC. | |
210 | */ | |
211 | static void write_pmc(int idx, unsigned long val) | |
212 | { | |
213 | switch (idx) { | |
214 | case 1: | |
215 | mtspr(SPRN_PMC1, val); | |
216 | break; | |
217 | case 2: | |
218 | mtspr(SPRN_PMC2, val); | |
219 | break; | |
220 | case 3: | |
221 | mtspr(SPRN_PMC3, val); | |
222 | break; | |
223 | case 4: | |
224 | mtspr(SPRN_PMC4, val); | |
225 | break; | |
226 | case 5: | |
227 | mtspr(SPRN_PMC5, val); | |
228 | break; | |
229 | case 6: | |
230 | mtspr(SPRN_PMC6, val); | |
231 | break; | |
98fb1807 | 232 | #ifdef CONFIG_PPC64 |
4574910e PM |
233 | case 7: |
234 | mtspr(SPRN_PMC7, val); | |
235 | break; | |
236 | case 8: | |
237 | mtspr(SPRN_PMC8, val); | |
238 | break; | |
98fb1807 | 239 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
240 | default: |
241 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
242 | } | |
243 | } | |
244 | ||
245 | /* | |
246 | * Check if a set of events can all go on the PMU at once. | |
247 | * If they can't, this will look at alternative codes for the events | |
248 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 249 | * The feasible set is returned in event_id[]. |
4574910e | 250 | */ |
cdd6c482 IM |
251 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
252 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 253 | int n_ev) |
4574910e | 254 | { |
448d64f8 | 255 | unsigned long mask, value, nv; |
cdd6c482 IM |
256 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
257 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 258 | int i, j; |
448d64f8 PM |
259 | unsigned long addf = ppmu->add_fields; |
260 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 261 | |
a8f90e90 | 262 | if (n_ev > ppmu->n_counter) |
4574910e PM |
263 | return -1; |
264 | ||
265 | /* First see if the events will go on as-is */ | |
266 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 267 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
268 | && !ppmu->limited_pmc_event(event_id[i])) { |
269 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 270 | cpuhw->alternatives[i]); |
cdd6c482 | 271 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 272 | } |
cdd6c482 | 273 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 274 | &cpuhw->avalues[i][0])) |
4574910e | 275 | return -1; |
4574910e PM |
276 | } |
277 | value = mask = 0; | |
278 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
279 | nv = (value | cpuhw->avalues[i][0]) + |
280 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 281 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
282 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
283 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
284 | break; |
285 | value = nv; | |
e51ee31e | 286 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
287 | } |
288 | if (i == n_ev) | |
289 | return 0; /* all OK */ | |
290 | ||
291 | /* doesn't work, gather alternatives... */ | |
292 | if (!ppmu->get_alternatives) | |
293 | return -1; | |
294 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 295 | choice[i] = 0; |
cdd6c482 | 296 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 297 | cpuhw->alternatives[i]); |
4574910e | 298 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
299 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
300 | &cpuhw->amasks[i][j], | |
301 | &cpuhw->avalues[i][j]); | |
4574910e PM |
302 | } |
303 | ||
304 | /* enumerate all possibilities and see if any will work */ | |
305 | i = 0; | |
306 | j = -1; | |
307 | value = mask = nv = 0; | |
308 | while (i < n_ev) { | |
309 | if (j >= 0) { | |
310 | /* we're backtracking, restore context */ | |
311 | value = svalues[i]; | |
312 | mask = smasks[i]; | |
313 | j = choice[i]; | |
314 | } | |
315 | /* | |
cdd6c482 | 316 | * See if any alternative k for event_id i, |
4574910e PM |
317 | * where k > j, will satisfy the constraints. |
318 | */ | |
319 | while (++j < n_alt[i]) { | |
e51ee31e PM |
320 | nv = (value | cpuhw->avalues[i][j]) + |
321 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 322 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
323 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
324 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
325 | break; |
326 | } | |
327 | if (j >= n_alt[i]) { | |
328 | /* | |
329 | * No feasible alternative, backtrack | |
cdd6c482 | 330 | * to event_id i-1 and continue enumerating its |
4574910e PM |
331 | * alternatives from where we got up to. |
332 | */ | |
333 | if (--i < 0) | |
334 | return -1; | |
335 | } else { | |
336 | /* | |
cdd6c482 IM |
337 | * Found a feasible alternative for event_id i, |
338 | * remember where we got up to with this event_id, | |
339 | * go on to the next event_id, and start with | |
4574910e PM |
340 | * the first alternative for it. |
341 | */ | |
342 | choice[i] = j; | |
343 | svalues[i] = value; | |
344 | smasks[i] = mask; | |
345 | value = nv; | |
e51ee31e | 346 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
347 | ++i; |
348 | j = -1; | |
349 | } | |
350 | } | |
351 | ||
352 | /* OK, we have a feasible combination, tell the caller the solution */ | |
353 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 354 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
355 | return 0; |
356 | } | |
357 | ||
0475f9ea | 358 | /* |
cdd6c482 | 359 | * Check if newly-added events have consistent settings for |
0475f9ea | 360 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 361 | * added events. |
0475f9ea | 362 | */ |
cdd6c482 | 363 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 364 | int n_prev, int n_new) |
0475f9ea | 365 | { |
ab7ef2e5 PM |
366 | int eu = 0, ek = 0, eh = 0; |
367 | int i, n, first; | |
cdd6c482 | 368 | struct perf_event *event; |
0475f9ea PM |
369 | |
370 | n = n_prev + n_new; | |
371 | if (n <= 1) | |
372 | return 0; | |
373 | ||
ab7ef2e5 PM |
374 | first = 1; |
375 | for (i = 0; i < n; ++i) { | |
376 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
377 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
378 | continue; | |
379 | } | |
cdd6c482 | 380 | event = ctrs[i]; |
ab7ef2e5 | 381 | if (first) { |
cdd6c482 IM |
382 | eu = event->attr.exclude_user; |
383 | ek = event->attr.exclude_kernel; | |
384 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 385 | first = 0; |
cdd6c482 IM |
386 | } else if (event->attr.exclude_user != eu || |
387 | event->attr.exclude_kernel != ek || | |
388 | event->attr.exclude_hv != eh) { | |
0475f9ea | 389 | return -EAGAIN; |
ab7ef2e5 | 390 | } |
0475f9ea | 391 | } |
ab7ef2e5 PM |
392 | |
393 | if (eu || ek || eh) | |
394 | for (i = 0; i < n; ++i) | |
395 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
396 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
397 | ||
0475f9ea PM |
398 | return 0; |
399 | } | |
400 | ||
cdd6c482 | 401 | static void power_pmu_read(struct perf_event *event) |
4574910e | 402 | { |
98fb1807 | 403 | s64 val, delta, prev; |
4574910e | 404 | |
cdd6c482 | 405 | if (!event->hw.idx) |
4574910e PM |
406 | return; |
407 | /* | |
408 | * Performance monitor interrupts come even when interrupts | |
409 | * are soft-disabled, as long as interrupts are hard-enabled. | |
410 | * Therefore we treat them like NMIs. | |
411 | */ | |
412 | do { | |
e7850595 | 413 | prev = local64_read(&event->hw.prev_count); |
4574910e | 414 | barrier(); |
cdd6c482 | 415 | val = read_pmc(event->hw.idx); |
e7850595 | 416 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 417 | |
57c0c15b | 418 | /* The counters are only 32 bits wide */ |
4574910e | 419 | delta = (val - prev) & 0xfffffffful; |
e7850595 PZ |
420 | local64_add(delta, &event->count); |
421 | local64_sub(delta, &event->hw.period_left); | |
4574910e PM |
422 | } |
423 | ||
ab7ef2e5 PM |
424 | /* |
425 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
426 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 427 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
428 | */ |
429 | static int is_limited_pmc(int pmcnum) | |
430 | { | |
0bbd0d4b PM |
431 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
432 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
433 | } |
434 | ||
a8f90e90 | 435 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
436 | unsigned long pmc5, unsigned long pmc6) |
437 | { | |
cdd6c482 | 438 | struct perf_event *event; |
ab7ef2e5 PM |
439 | u64 val, prev, delta; |
440 | int i; | |
441 | ||
442 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 443 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 444 | if (!event->hw.idx) |
ab7ef2e5 | 445 | continue; |
cdd6c482 | 446 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 447 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 448 | event->hw.idx = 0; |
ab7ef2e5 | 449 | delta = (val - prev) & 0xfffffffful; |
e7850595 | 450 | local64_add(delta, &event->count); |
ab7ef2e5 PM |
451 | } |
452 | } | |
453 | ||
a8f90e90 | 454 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
455 | unsigned long pmc5, unsigned long pmc6) |
456 | { | |
cdd6c482 | 457 | struct perf_event *event; |
ab7ef2e5 PM |
458 | u64 val; |
459 | int i; | |
460 | ||
461 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 462 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
463 | event->hw.idx = cpuhw->limited_hwidx[i]; |
464 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
e7850595 | 465 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 466 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
467 | } |
468 | } | |
469 | ||
470 | /* | |
cdd6c482 | 471 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 472 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
473 | * other events. We try to keep the values from the limited |
474 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 475 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
476 | * the limited events as small and consistent as possible. |
477 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
478 | * both, and always in the same order, to minimize variability, |
479 | * and do it inside the same asm that writes MMCR0. | |
480 | */ | |
cdd6c482 | 481 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
482 | { |
483 | unsigned long pmc5, pmc6; | |
484 | ||
485 | if (!cpuhw->n_limited) { | |
486 | mtspr(SPRN_MMCR0, mmcr0); | |
487 | return; | |
488 | } | |
489 | ||
490 | /* | |
491 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
492 | * To ensure we don't get a performance monitor interrupt |
493 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 494 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 495 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
496 | */ |
497 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
498 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
499 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
500 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
501 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
502 | ||
503 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 504 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 505 | else |
a8f90e90 | 506 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
507 | |
508 | /* | |
cdd6c482 | 509 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
510 | * enable bits, if necessary. |
511 | */ | |
512 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
513 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
514 | } |
515 | ||
4574910e | 516 | /* |
cdd6c482 IM |
517 | * Disable all events to prevent PMU interrupts and to allow |
518 | * events to be added or removed. | |
4574910e | 519 | */ |
9e35ad38 | 520 | void hw_perf_disable(void) |
4574910e | 521 | { |
cdd6c482 | 522 | struct cpu_hw_events *cpuhw; |
4574910e PM |
523 | unsigned long flags; |
524 | ||
f36a1a13 PM |
525 | if (!ppmu) |
526 | return; | |
4574910e | 527 | local_irq_save(flags); |
cdd6c482 | 528 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 529 | |
448d64f8 | 530 | if (!cpuhw->disabled) { |
4574910e PM |
531 | cpuhw->disabled = 1; |
532 | cpuhw->n_added = 0; | |
533 | ||
01d0287f PM |
534 | /* |
535 | * Check if we ever enabled the PMU on this cpu. | |
536 | */ | |
537 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 538 | ppc_enable_pmcs(); |
01d0287f PM |
539 | cpuhw->pmcs_enabled = 1; |
540 | } | |
541 | ||
f708223d PM |
542 | /* |
543 | * Disable instruction sampling if it was enabled | |
544 | */ | |
545 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
546 | mtspr(SPRN_MMCRA, | |
547 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
548 | mb(); | |
549 | } | |
550 | ||
4574910e | 551 | /* |
57c0c15b | 552 | * Set the 'freeze counters' bit. |
4574910e | 553 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 554 | * executed and the PMU has frozen the events |
4574910e PM |
555 | * before we return. |
556 | */ | |
ab7ef2e5 | 557 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
558 | mb(); |
559 | } | |
560 | local_irq_restore(flags); | |
4574910e PM |
561 | } |
562 | ||
563 | /* | |
cdd6c482 IM |
564 | * Re-enable all events if disable == 0. |
565 | * If we were previously disabled and events were added, then | |
4574910e PM |
566 | * put the new config on the PMU. |
567 | */ | |
9e35ad38 | 568 | void hw_perf_enable(void) |
4574910e | 569 | { |
cdd6c482 IM |
570 | struct perf_event *event; |
571 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
572 | unsigned long flags; |
573 | long i; | |
574 | unsigned long val; | |
575 | s64 left; | |
cdd6c482 | 576 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
577 | int n_lim; |
578 | int idx; | |
4574910e | 579 | |
f36a1a13 PM |
580 | if (!ppmu) |
581 | return; | |
4574910e | 582 | local_irq_save(flags); |
cdd6c482 | 583 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
584 | if (!cpuhw->disabled) { |
585 | local_irq_restore(flags); | |
586 | return; | |
587 | } | |
4574910e PM |
588 | cpuhw->disabled = 0; |
589 | ||
590 | /* | |
cdd6c482 | 591 | * If we didn't change anything, or only removed events, |
4574910e PM |
592 | * no need to recalculate MMCR* settings and reset the PMCs. |
593 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 594 | * (possibly updated for removal of events). |
4574910e PM |
595 | */ |
596 | if (!cpuhw->n_added) { | |
f708223d | 597 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 598 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 599 | if (cpuhw->n_events == 0) |
a6dbf93a | 600 | ppc_set_pmu_inuse(0); |
f708223d | 601 | goto out_enable; |
4574910e PM |
602 | } |
603 | ||
604 | /* | |
cdd6c482 | 605 | * Compute MMCR* values for the new set of events |
4574910e | 606 | */ |
cdd6c482 | 607 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
608 | cpuhw->mmcr)) { |
609 | /* shouldn't ever get here */ | |
610 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
611 | goto out; | |
612 | } | |
613 | ||
0475f9ea PM |
614 | /* |
615 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
616 | * attr.exclude_* bits for the first event. |
617 | * We have already checked that all events have the | |
618 | * same values for these bits as the first event. | |
0475f9ea | 619 | */ |
cdd6c482 IM |
620 | event = cpuhw->event[0]; |
621 | if (event->attr.exclude_user) | |
0475f9ea | 622 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
623 | if (event->attr.exclude_kernel) |
624 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
625 | if (event->attr.exclude_hv) | |
0475f9ea PM |
626 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
627 | ||
4574910e PM |
628 | /* |
629 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
630 | * bit set and set the hardware events to their initial values. |
631 | * Then unfreeze the events. | |
4574910e | 632 | */ |
a6dbf93a | 633 | ppc_set_pmu_inuse(1); |
f708223d | 634 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
635 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
636 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
637 | | MMCR0_FC); | |
638 | ||
639 | /* | |
cdd6c482 | 640 | * Read off any pre-existing events that need to move |
4574910e PM |
641 | * to another PMC. |
642 | */ | |
cdd6c482 IM |
643 | for (i = 0; i < cpuhw->n_events; ++i) { |
644 | event = cpuhw->event[i]; | |
645 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
646 | power_pmu_read(event); | |
647 | write_pmc(event->hw.idx, 0); | |
648 | event->hw.idx = 0; | |
4574910e PM |
649 | } |
650 | } | |
651 | ||
652 | /* | |
cdd6c482 | 653 | * Initialize the PMCs for all the new and moved events. |
4574910e | 654 | */ |
ab7ef2e5 | 655 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
656 | for (i = 0; i < cpuhw->n_events; ++i) { |
657 | event = cpuhw->event[i]; | |
658 | if (event->hw.idx) | |
4574910e | 659 | continue; |
ab7ef2e5 PM |
660 | idx = hwc_index[i] + 1; |
661 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 662 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
663 | cpuhw->limited_hwidx[n_lim] = idx; |
664 | ++n_lim; | |
665 | continue; | |
666 | } | |
4574910e | 667 | val = 0; |
cdd6c482 | 668 | if (event->hw.sample_period) { |
e7850595 | 669 | left = local64_read(&event->hw.period_left); |
4574910e PM |
670 | if (left < 0x80000000L) |
671 | val = 0x80000000L - left; | |
672 | } | |
e7850595 | 673 | local64_set(&event->hw.prev_count, val); |
cdd6c482 | 674 | event->hw.idx = idx; |
ab7ef2e5 | 675 | write_pmc(idx, val); |
cdd6c482 | 676 | perf_event_update_userpage(event); |
4574910e | 677 | } |
ab7ef2e5 | 678 | cpuhw->n_limited = n_lim; |
4574910e | 679 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
680 | |
681 | out_enable: | |
682 | mb(); | |
ab7ef2e5 | 683 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 684 | |
f708223d PM |
685 | /* |
686 | * Enable instruction sampling if necessary | |
687 | */ | |
688 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
689 | mb(); | |
690 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
691 | } | |
692 | ||
4574910e PM |
693 | out: |
694 | local_irq_restore(flags); | |
695 | } | |
696 | ||
cdd6c482 IM |
697 | static int collect_events(struct perf_event *group, int max_count, |
698 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 699 | unsigned int *flags) |
4574910e PM |
700 | { |
701 | int n = 0; | |
cdd6c482 | 702 | struct perf_event *event; |
4574910e | 703 | |
cdd6c482 | 704 | if (!is_software_event(group)) { |
4574910e PM |
705 | if (n >= max_count) |
706 | return -1; | |
707 | ctrs[n] = group; | |
cdd6c482 | 708 | flags[n] = group->hw.event_base; |
4574910e PM |
709 | events[n++] = group->hw.config; |
710 | } | |
a8f90e90 | 711 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
712 | if (!is_software_event(event) && |
713 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
714 | if (n >= max_count) |
715 | return -1; | |
cdd6c482 IM |
716 | ctrs[n] = event; |
717 | flags[n] = event->hw.event_base; | |
718 | events[n++] = event->hw.config; | |
4574910e PM |
719 | } |
720 | } | |
721 | return n; | |
722 | } | |
723 | ||
4574910e | 724 | /* |
cdd6c482 IM |
725 | * Add a event to the PMU. |
726 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 727 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
728 | * actual work of reconfiguring the PMU. |
729 | */ | |
cdd6c482 | 730 | static int power_pmu_enable(struct perf_event *event) |
4574910e | 731 | { |
cdd6c482 | 732 | struct cpu_hw_events *cpuhw; |
4574910e | 733 | unsigned long flags; |
4574910e PM |
734 | int n0; |
735 | int ret = -EAGAIN; | |
736 | ||
737 | local_irq_save(flags); | |
9e35ad38 | 738 | perf_disable(); |
4574910e PM |
739 | |
740 | /* | |
cdd6c482 | 741 | * Add the event to the list (if there is room) |
4574910e PM |
742 | * and check whether the total set is still feasible. |
743 | */ | |
cdd6c482 IM |
744 | cpuhw = &__get_cpu_var(cpu_hw_events); |
745 | n0 = cpuhw->n_events; | |
a8f90e90 | 746 | if (n0 >= ppmu->n_counter) |
4574910e | 747 | goto out; |
cdd6c482 IM |
748 | cpuhw->event[n0] = event; |
749 | cpuhw->events[n0] = event->hw.config; | |
750 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 LM |
751 | |
752 | /* | |
753 | * If group events scheduling transaction was started, | |
754 | * skip the schedulability test here, it will be peformed | |
755 | * at commit time(->commit_txn) as a whole | |
756 | */ | |
8d2cacbb | 757 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
758 | goto nocheck; |
759 | ||
cdd6c482 | 760 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 761 | goto out; |
e51ee31e | 762 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 763 | goto out; |
cdd6c482 | 764 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
765 | |
766 | nocheck: | |
cdd6c482 | 767 | ++cpuhw->n_events; |
4574910e PM |
768 | ++cpuhw->n_added; |
769 | ||
770 | ret = 0; | |
771 | out: | |
9e35ad38 | 772 | perf_enable(); |
4574910e PM |
773 | local_irq_restore(flags); |
774 | return ret; | |
775 | } | |
776 | ||
777 | /* | |
cdd6c482 | 778 | * Remove a event from the PMU. |
4574910e | 779 | */ |
cdd6c482 | 780 | static void power_pmu_disable(struct perf_event *event) |
4574910e | 781 | { |
cdd6c482 | 782 | struct cpu_hw_events *cpuhw; |
4574910e | 783 | long i; |
4574910e PM |
784 | unsigned long flags; |
785 | ||
786 | local_irq_save(flags); | |
9e35ad38 | 787 | perf_disable(); |
4574910e | 788 | |
cdd6c482 IM |
789 | power_pmu_read(event); |
790 | ||
791 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
792 | for (i = 0; i < cpuhw->n_events; ++i) { | |
793 | if (event == cpuhw->event[i]) { | |
219a92a4 | 794 | while (++i < cpuhw->n_events) { |
cdd6c482 | 795 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
796 | cpuhw->events[i-1] = cpuhw->events[i]; |
797 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
798 | } | |
cdd6c482 IM |
799 | --cpuhw->n_events; |
800 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
801 | if (event->hw.idx) { | |
802 | write_pmc(event->hw.idx, 0); | |
803 | event->hw.idx = 0; | |
ab7ef2e5 | 804 | } |
cdd6c482 | 805 | perf_event_update_userpage(event); |
4574910e PM |
806 | break; |
807 | } | |
808 | } | |
ab7ef2e5 | 809 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 810 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
811 | break; |
812 | if (i < cpuhw->n_limited) { | |
813 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 814 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
815 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
816 | } | |
817 | --cpuhw->n_limited; | |
818 | } | |
cdd6c482 IM |
819 | if (cpuhw->n_events == 0) { |
820 | /* disable exceptions if no events are running */ | |
4574910e PM |
821 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
822 | } | |
823 | ||
9e35ad38 | 824 | perf_enable(); |
4574910e PM |
825 | local_irq_restore(flags); |
826 | } | |
827 | ||
8a7b8cb9 | 828 | /* |
cdd6c482 | 829 | * Re-enable interrupts on a event after they were throttled |
8a7b8cb9 PM |
830 | * because they were coming too fast. |
831 | */ | |
cdd6c482 | 832 | static void power_pmu_unthrottle(struct perf_event *event) |
8a7b8cb9 PM |
833 | { |
834 | s64 val, left; | |
835 | unsigned long flags; | |
836 | ||
cdd6c482 | 837 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 PM |
838 | return; |
839 | local_irq_save(flags); | |
840 | perf_disable(); | |
cdd6c482 IM |
841 | power_pmu_read(event); |
842 | left = event->hw.sample_period; | |
843 | event->hw.last_period = left; | |
8a7b8cb9 PM |
844 | val = 0; |
845 | if (left < 0x80000000L) | |
846 | val = 0x80000000L - left; | |
cdd6c482 | 847 | write_pmc(event->hw.idx, val); |
e7850595 PZ |
848 | local64_set(&event->hw.prev_count, val); |
849 | local64_set(&event->hw.period_left, left); | |
cdd6c482 | 850 | perf_event_update_userpage(event); |
8a7b8cb9 PM |
851 | perf_enable(); |
852 | local_irq_restore(flags); | |
853 | } | |
854 | ||
8e6d5573 LM |
855 | /* |
856 | * Start group events scheduling transaction | |
857 | * Set the flag to make pmu::enable() not perform the | |
858 | * schedulability test, it will be performed at commit time | |
859 | */ | |
51b0fe39 | 860 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
861 | { |
862 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
863 | ||
8d2cacbb | 864 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
865 | cpuhw->n_txn_start = cpuhw->n_events; |
866 | } | |
867 | ||
868 | /* | |
869 | * Stop group events scheduling transaction | |
870 | * Clear the flag and pmu::enable() will perform the | |
871 | * schedulability test. | |
872 | */ | |
51b0fe39 | 873 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
874 | { |
875 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
876 | ||
8d2cacbb | 877 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
8e6d5573 LM |
878 | } |
879 | ||
880 | /* | |
881 | * Commit group events scheduling transaction | |
882 | * Perform the group schedulability test as a whole | |
883 | * Return 0 if success | |
884 | */ | |
51b0fe39 | 885 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
886 | { |
887 | struct cpu_hw_events *cpuhw; | |
888 | long i, n; | |
889 | ||
890 | if (!ppmu) | |
891 | return -EAGAIN; | |
892 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
893 | n = cpuhw->n_events; | |
894 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
895 | return -EAGAIN; | |
896 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
897 | if (i < 0) | |
898 | return -EAGAIN; | |
899 | ||
900 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
901 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
902 | ||
8d2cacbb | 903 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
8e6d5573 LM |
904 | return 0; |
905 | } | |
906 | ||
4aeb0b42 RR |
907 | struct pmu power_pmu = { |
908 | .enable = power_pmu_enable, | |
909 | .disable = power_pmu_disable, | |
910 | .read = power_pmu_read, | |
8a7b8cb9 | 911 | .unthrottle = power_pmu_unthrottle, |
8e6d5573 LM |
912 | .start_txn = power_pmu_start_txn, |
913 | .cancel_txn = power_pmu_cancel_txn, | |
914 | .commit_txn = power_pmu_commit_txn, | |
4574910e PM |
915 | }; |
916 | ||
ab7ef2e5 | 917 | /* |
cdd6c482 | 918 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 919 | * or 0 if not. |
cdd6c482 | 920 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
921 | * that a limited PMC can count, doesn't require interrupts, and |
922 | * doesn't exclude any processor mode. | |
923 | */ | |
cdd6c482 | 924 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
925 | unsigned int flags) |
926 | { | |
927 | int n; | |
ef923214 | 928 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 929 | |
cdd6c482 IM |
930 | if (event->attr.exclude_user |
931 | || event->attr.exclude_kernel | |
932 | || event->attr.exclude_hv | |
933 | || event->attr.sample_period) | |
ab7ef2e5 PM |
934 | return 0; |
935 | ||
936 | if (ppmu->limited_pmc_event(ev)) | |
937 | return 1; | |
938 | ||
939 | /* | |
cdd6c482 | 940 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
941 | * see if any alternative code goes on a limited PMC. |
942 | */ | |
943 | if (!ppmu->get_alternatives) | |
944 | return 0; | |
945 | ||
946 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
947 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 948 | |
ef923214 | 949 | return n > 0; |
ab7ef2e5 PM |
950 | } |
951 | ||
952 | /* | |
cdd6c482 IM |
953 | * Find an alternative event_id that goes on a normal PMC, if possible, |
954 | * and return the event_id code, or 0 if there is no such alternative. | |
955 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 956 | */ |
ef923214 | 957 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 958 | { |
ef923214 | 959 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
960 | int n; |
961 | ||
962 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
963 | n = ppmu->get_alternatives(ev, flags, alt); | |
964 | if (!n) | |
965 | return 0; | |
966 | return alt[0]; | |
967 | } | |
968 | ||
cdd6c482 IM |
969 | /* Number of perf_events counting hardware events */ |
970 | static atomic_t num_events; | |
7595d63b PM |
971 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
972 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
973 | ||
974 | /* | |
cdd6c482 | 975 | * Release the PMU if this is the last perf_event. |
7595d63b | 976 | */ |
cdd6c482 | 977 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 978 | { |
cdd6c482 | 979 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 980 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 981 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
982 | release_pmc_hardware(); |
983 | mutex_unlock(&pmc_reserve_mutex); | |
984 | } | |
985 | } | |
986 | ||
106b506c | 987 | /* |
cdd6c482 | 988 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
989 | */ |
990 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
991 | { | |
992 | unsigned long type, op, result; | |
993 | int ev; | |
994 | ||
995 | if (!ppmu->cache_events) | |
996 | return -EINVAL; | |
997 | ||
998 | /* unpack config */ | |
999 | type = config & 0xff; | |
1000 | op = (config >> 8) & 0xff; | |
1001 | result = (config >> 16) & 0xff; | |
1002 | ||
1003 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1004 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1005 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1006 | return -EINVAL; | |
1007 | ||
1008 | ev = (*ppmu->cache_events)[type][op][result]; | |
1009 | if (ev == 0) | |
1010 | return -EOPNOTSUPP; | |
1011 | if (ev == -1) | |
1012 | return -EINVAL; | |
1013 | *eventp = ev; | |
1014 | return 0; | |
1015 | } | |
1016 | ||
51b0fe39 | 1017 | struct pmu *hw_perf_event_init(struct perf_event *event) |
4574910e | 1018 | { |
ef923214 PM |
1019 | u64 ev; |
1020 | unsigned long flags; | |
cdd6c482 IM |
1021 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1022 | u64 events[MAX_HWEVENTS]; | |
1023 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1024 | int n; |
7595d63b | 1025 | int err; |
cdd6c482 | 1026 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1027 | |
1028 | if (!ppmu) | |
d5d2bc0d | 1029 | return ERR_PTR(-ENXIO); |
cdd6c482 | 1030 | switch (event->attr.type) { |
106b506c | 1031 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1032 | ev = event->attr.config; |
9aaa131a | 1033 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
d5d2bc0d | 1034 | return ERR_PTR(-EOPNOTSUPP); |
4574910e | 1035 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1036 | break; |
1037 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1038 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c PM |
1039 | if (err) |
1040 | return ERR_PTR(err); | |
1041 | break; | |
1042 | case PERF_TYPE_RAW: | |
cdd6c482 | 1043 | ev = event->attr.config; |
106b506c | 1044 | break; |
90c8f954 PM |
1045 | default: |
1046 | return ERR_PTR(-EINVAL); | |
4574910e | 1047 | } |
cdd6c482 IM |
1048 | event->hw.config_base = ev; |
1049 | event->hw.idx = 0; | |
4574910e | 1050 | |
0475f9ea PM |
1051 | /* |
1052 | * If we are not running on a hypervisor, force the | |
1053 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1054 | * the user set it to. |
0475f9ea PM |
1055 | */ |
1056 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1057 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1058 | |
1059 | /* | |
cdd6c482 | 1060 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1061 | * PM_RUN_* events interchangeably with their non RUN_* |
1062 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1063 | * XXX we should check if the task is an idle task. | |
1064 | */ | |
1065 | flags = 0; | |
cdd6c482 | 1066 | if (event->ctx->task) |
ab7ef2e5 PM |
1067 | flags |= PPMU_ONLY_COUNT_RUN; |
1068 | ||
1069 | /* | |
cdd6c482 IM |
1070 | * If this machine has limited events, check whether this |
1071 | * event_id could go on a limited event. | |
ab7ef2e5 | 1072 | */ |
0bbd0d4b | 1073 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1074 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1075 | flags |= PPMU_LIMITED_PMC_OK; |
1076 | } else if (ppmu->limited_pmc_event(ev)) { | |
1077 | /* | |
cdd6c482 | 1078 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1079 | * but we can't use a limited PMC; see if any |
1080 | * alternative goes on a normal PMC. | |
1081 | */ | |
1082 | ev = normal_pmc_alternative(ev, flags); | |
1083 | if (!ev) | |
1084 | return ERR_PTR(-EINVAL); | |
1085 | } | |
1086 | } | |
1087 | ||
4574910e PM |
1088 | /* |
1089 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1090 | * other hardware events in the group. We assume the event |
4574910e PM |
1091 | * hasn't been linked into its leader's sibling list at this point. |
1092 | */ | |
1093 | n = 0; | |
cdd6c482 | 1094 | if (event->group_leader != event) { |
a8f90e90 | 1095 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1096 | ctrs, events, cflags); |
4574910e | 1097 | if (n < 0) |
d5d2bc0d | 1098 | return ERR_PTR(-EINVAL); |
4574910e | 1099 | } |
0475f9ea | 1100 | events[n] = ev; |
cdd6c482 | 1101 | ctrs[n] = event; |
ab7ef2e5 PM |
1102 | cflags[n] = flags; |
1103 | if (check_excludes(ctrs, cflags, n, 1)) | |
d5d2bc0d | 1104 | return ERR_PTR(-EINVAL); |
e51ee31e | 1105 | |
cdd6c482 | 1106 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1107 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
cdd6c482 | 1108 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1109 | if (err) |
d5d2bc0d | 1110 | return ERR_PTR(-EINVAL); |
4574910e | 1111 | |
cdd6c482 IM |
1112 | event->hw.config = events[n]; |
1113 | event->hw.event_base = cflags[n]; | |
1114 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1115 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b PM |
1116 | |
1117 | /* | |
1118 | * See if we need to reserve the PMU. | |
cdd6c482 | 1119 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1120 | * mutex to ensure that we don't race with another task doing |
1121 | * reserve_pmc_hardware or release_pmc_hardware. | |
1122 | */ | |
1123 | err = 0; | |
cdd6c482 | 1124 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1125 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1126 | if (atomic_read(&num_events) == 0 && |
1127 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1128 | err = -EBUSY; |
1129 | else | |
cdd6c482 | 1130 | atomic_inc(&num_events); |
7595d63b PM |
1131 | mutex_unlock(&pmc_reserve_mutex); |
1132 | } | |
cdd6c482 | 1133 | event->destroy = hw_perf_event_destroy; |
7595d63b PM |
1134 | |
1135 | if (err) | |
d5d2bc0d | 1136 | return ERR_PTR(err); |
4aeb0b42 | 1137 | return &power_pmu; |
4574910e PM |
1138 | } |
1139 | ||
4574910e | 1140 | /* |
57c0c15b | 1141 | * A counter has overflowed; update its count and record |
4574910e PM |
1142 | * things if requested. Note that interrupts are hard-disabled |
1143 | * here so there is no possibility of being interrupted. | |
1144 | */ | |
cdd6c482 | 1145 | static void record_and_restart(struct perf_event *event, unsigned long val, |
ca8f2d7f | 1146 | struct pt_regs *regs, int nmi) |
4574910e | 1147 | { |
cdd6c482 | 1148 | u64 period = event->hw.sample_period; |
4574910e PM |
1149 | s64 prev, delta, left; |
1150 | int record = 0; | |
1151 | ||
1152 | /* we don't have to worry about interrupts here */ | |
e7850595 | 1153 | prev = local64_read(&event->hw.prev_count); |
4574910e | 1154 | delta = (val - prev) & 0xfffffffful; |
e7850595 | 1155 | local64_add(delta, &event->count); |
4574910e PM |
1156 | |
1157 | /* | |
cdd6c482 | 1158 | * See if the total period for this event has expired, |
4574910e PM |
1159 | * and update for the next period. |
1160 | */ | |
1161 | val = 0; | |
e7850595 | 1162 | left = local64_read(&event->hw.period_left) - delta; |
60db5e09 | 1163 | if (period) { |
4574910e | 1164 | if (left <= 0) { |
60db5e09 | 1165 | left += period; |
4574910e | 1166 | if (left <= 0) |
60db5e09 | 1167 | left = period; |
4574910e PM |
1168 | record = 1; |
1169 | } | |
98fb1807 PM |
1170 | if (left < 0x80000000LL) |
1171 | val = 0x80000000LL - left; | |
4574910e | 1172 | } |
4574910e PM |
1173 | |
1174 | /* | |
1175 | * Finally record data if requested. | |
1176 | */ | |
0bbd0d4b | 1177 | if (record) { |
dc1d628a PZ |
1178 | struct perf_sample_data data; |
1179 | ||
1180 | perf_sample_data_init(&data, ~0ULL); | |
1181 | data.period = event->hw.last_period; | |
df1a132b | 1182 | |
cdd6c482 | 1183 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1184 | perf_get_data_addr(regs, &data.addr); |
1185 | ||
cdd6c482 | 1186 | if (perf_event_overflow(event, nmi, &data, regs)) { |
8a7b8cb9 PM |
1187 | /* |
1188 | * Interrupts are coming too fast - throttle them | |
cdd6c482 | 1189 | * by setting the event to 0, so it will be |
8a7b8cb9 | 1190 | * at least 2^30 cycles until the next interrupt |
cdd6c482 | 1191 | * (assuming each event counts at most 2 counts |
8a7b8cb9 PM |
1192 | * per cycle). |
1193 | */ | |
1194 | val = 0; | |
1195 | left = ~0ULL >> 1; | |
1196 | } | |
0bbd0d4b | 1197 | } |
8a7b8cb9 | 1198 | |
cdd6c482 | 1199 | write_pmc(event->hw.idx, val); |
e7850595 PZ |
1200 | local64_set(&event->hw.prev_count, val); |
1201 | local64_set(&event->hw.period_left, left); | |
cdd6c482 | 1202 | perf_event_update_userpage(event); |
0bbd0d4b PM |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1207 | * for an event_id. |
0bbd0d4b PM |
1208 | */ |
1209 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1210 | { | |
98fb1807 | 1211 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1212 | |
98fb1807 PM |
1213 | if (flags) |
1214 | return flags; | |
cdd6c482 IM |
1215 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1216 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1217 | } |
1218 | ||
1219 | /* | |
1220 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1221 | * for an event_id. |
0bbd0d4b PM |
1222 | */ |
1223 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1224 | { | |
0bbd0d4b | 1225 | unsigned long ip; |
0bbd0d4b PM |
1226 | |
1227 | if (TRAP(regs) != 0xf00) | |
1228 | return regs->nip; /* not a PMU interrupt */ | |
1229 | ||
98fb1807 | 1230 | ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
0bbd0d4b | 1231 | return ip; |
4574910e PM |
1232 | } |
1233 | ||
1234 | /* | |
1235 | * Performance monitor interrupt stuff | |
1236 | */ | |
cdd6c482 | 1237 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e PM |
1238 | { |
1239 | int i; | |
cdd6c482 IM |
1240 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1241 | struct perf_event *event; | |
98fb1807 | 1242 | unsigned long val; |
925d519a | 1243 | int found = 0; |
ca8f2d7f PM |
1244 | int nmi; |
1245 | ||
ab7ef2e5 | 1246 | if (cpuhw->n_limited) |
a8f90e90 | 1247 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1248 | mfspr(SPRN_PMC6)); |
1249 | ||
98fb1807 | 1250 | perf_read_regs(regs); |
0bbd0d4b | 1251 | |
98fb1807 | 1252 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1253 | if (nmi) |
1254 | nmi_enter(); | |
1255 | else | |
1256 | irq_enter(); | |
4574910e | 1257 | |
cdd6c482 IM |
1258 | for (i = 0; i < cpuhw->n_events; ++i) { |
1259 | event = cpuhw->event[i]; | |
1260 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1261 | continue; |
cdd6c482 | 1262 | val = read_pmc(event->hw.idx); |
4574910e | 1263 | if ((int)val < 0) { |
cdd6c482 | 1264 | /* event has overflowed */ |
4574910e | 1265 | found = 1; |
cdd6c482 | 1266 | record_and_restart(event, val, regs, nmi); |
4574910e PM |
1267 | } |
1268 | } | |
1269 | ||
1270 | /* | |
cdd6c482 IM |
1271 | * In case we didn't find and reset the event that caused |
1272 | * the interrupt, scan all events and reset any that are | |
4574910e PM |
1273 | * negative, to avoid getting continual interrupts. |
1274 | * Any that we processed in the previous loop will not be negative. | |
1275 | */ | |
1276 | if (!found) { | |
a8f90e90 | 1277 | for (i = 0; i < ppmu->n_counter; ++i) { |
ab7ef2e5 PM |
1278 | if (is_limited_pmc(i + 1)) |
1279 | continue; | |
4574910e PM |
1280 | val = read_pmc(i + 1); |
1281 | if ((int)val < 0) | |
1282 | write_pmc(i + 1, 0); | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | /* | |
1287 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 1288 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 1289 | * and thus allow interrupts to occur again. |
cdd6c482 | 1290 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1291 | * we get back out of this interrupt. |
1292 | */ | |
ab7ef2e5 | 1293 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1294 | |
ca8f2d7f PM |
1295 | if (nmi) |
1296 | nmi_exit(); | |
1297 | else | |
db4fb5ac | 1298 | irq_exit(); |
4574910e PM |
1299 | } |
1300 | ||
3f6da390 | 1301 | static void power_pmu_setup(int cpu) |
01d0287f | 1302 | { |
cdd6c482 | 1303 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1304 | |
f36a1a13 PM |
1305 | if (!ppmu) |
1306 | return; | |
01d0287f PM |
1307 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1308 | cpuhw->mmcr[0] = MMCR0_FC; | |
1309 | } | |
1310 | ||
3f6da390 | 1311 | static int __cpuinit |
85cfabbc | 1312 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
1313 | { |
1314 | unsigned int cpu = (long)hcpu; | |
1315 | ||
1316 | switch (action & ~CPU_TASKS_FROZEN) { | |
1317 | case CPU_UP_PREPARE: | |
1318 | power_pmu_setup(cpu); | |
1319 | break; | |
1320 | ||
1321 | default: | |
1322 | break; | |
1323 | } | |
1324 | ||
1325 | return NOTIFY_OK; | |
1326 | } | |
1327 | ||
079b3c56 | 1328 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1329 | { |
079b3c56 PM |
1330 | if (ppmu) |
1331 | return -EBUSY; /* something's already registered */ | |
1332 | ||
1333 | ppmu = pmu; | |
1334 | pr_info("%s performance monitor hardware support registered\n", | |
1335 | pmu->name); | |
d095cd46 | 1336 | |
98fb1807 | 1337 | #ifdef MSR_HV |
d095cd46 PM |
1338 | /* |
1339 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1340 | */ | |
1341 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1342 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1343 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1344 | |
3f6da390 PZ |
1345 | perf_cpu_notifier(power_pmu_notifier); |
1346 | ||
4574910e PM |
1347 | return 0; |
1348 | } |