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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
16 | #include <asm/reg.h> | |
17 | #include <asm/pmc.h> | |
01d0287f | 18 | #include <asm/machdep.h> |
0475f9ea | 19 | #include <asm/firmware.h> |
0bbd0d4b | 20 | #include <asm/ptrace.h> |
4574910e | 21 | |
cdd6c482 IM |
22 | struct cpu_hw_events { |
23 | int n_events; | |
4574910e PM |
24 | int n_percpu; |
25 | int disabled; | |
26 | int n_added; | |
ab7ef2e5 PM |
27 | int n_limited; |
28 | u8 pmcs_enabled; | |
cdd6c482 IM |
29 | struct perf_event *event[MAX_HWEVENTS]; |
30 | u64 events[MAX_HWEVENTS]; | |
31 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 32 | unsigned long mmcr[3]; |
cdd6c482 IM |
33 | struct perf_event *limited_event[MAX_LIMITED_HWEVENTS]; |
34 | u8 limited_hwidx[MAX_LIMITED_HWEVENTS]; | |
35 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
36 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
37 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
4574910e | 38 | }; |
cdd6c482 | 39 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
40 | |
41 | struct power_pmu *ppmu; | |
42 | ||
d095cd46 | 43 | /* |
cdd6c482 | 44 | * Normally, to ignore kernel events we set the FCS (freeze events |
d095cd46 PM |
45 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
46 | * hypervisor bit set in the MSR, or if we are running on a processor | |
47 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
48 | * then we need to use the FCHV bit to ignore kernel events. | |
49 | */ | |
cdd6c482 | 50 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 51 | |
98fb1807 PM |
52 | /* |
53 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
54 | * and a few other names are different. | |
55 | */ | |
56 | #ifdef CONFIG_PPC32 | |
57 | ||
58 | #define MMCR0_FCHV 0 | |
59 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
60 | ||
61 | #define SPRN_MMCRA SPRN_MMCR2 | |
62 | #define MMCRA_SAMPLE_ENABLE 0 | |
63 | ||
64 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
65 | { | |
66 | return 0; | |
67 | } | |
98fb1807 PM |
68 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
69 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
70 | { | |
71 | return 0; | |
72 | } | |
73 | static inline void perf_read_regs(struct pt_regs *regs) { } | |
74 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
75 | { | |
76 | return 0; | |
77 | } | |
78 | ||
79 | #endif /* CONFIG_PPC32 */ | |
80 | ||
81 | /* | |
82 | * Things that are specific to 64-bit implementations. | |
83 | */ | |
84 | #ifdef CONFIG_PPC64 | |
85 | ||
86 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
87 | { | |
88 | unsigned long mmcra = regs->dsisr; | |
89 | ||
90 | if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { | |
91 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; | |
92 | if (slot > 1) | |
93 | return 4 * (slot - 1); | |
94 | } | |
95 | return 0; | |
96 | } | |
97 | ||
98fb1807 PM |
98 | /* |
99 | * The user wants a data address recorded. | |
100 | * If we're not doing instruction sampling, give them the SDAR | |
101 | * (sampled data address). If we are doing instruction sampling, then | |
102 | * only give them the SDAR if it corresponds to the instruction | |
103 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC | |
104 | * bit in MMCRA. | |
105 | */ | |
106 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
107 | { | |
108 | unsigned long mmcra = regs->dsisr; | |
109 | unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? | |
110 | POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; | |
111 | ||
112 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) | |
113 | *addrp = mfspr(SPRN_SDAR); | |
114 | } | |
115 | ||
116 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
117 | { | |
118 | unsigned long mmcra = regs->dsisr; | |
119 | ||
120 | if (TRAP(regs) != 0xf00) | |
121 | return 0; /* not a PMU interrupt */ | |
122 | ||
123 | if (ppmu->flags & PPMU_ALT_SIPR) { | |
124 | if (mmcra & POWER6_MMCRA_SIHV) | |
cdd6c482 | 125 | return PERF_RECORD_MISC_HYPERVISOR; |
98fb1807 | 126 | return (mmcra & POWER6_MMCRA_SIPR) ? |
cdd6c482 | 127 | PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
128 | } |
129 | if (mmcra & MMCRA_SIHV) | |
cdd6c482 IM |
130 | return PERF_RECORD_MISC_HYPERVISOR; |
131 | return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER : | |
132 | PERF_RECORD_MISC_KERNEL; | |
98fb1807 PM |
133 | } |
134 | ||
135 | /* | |
136 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
137 | * on each interrupt. | |
138 | */ | |
139 | static inline void perf_read_regs(struct pt_regs *regs) | |
140 | { | |
141 | regs->dsisr = mfspr(SPRN_MMCRA); | |
142 | } | |
143 | ||
144 | /* | |
145 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
146 | * it as an NMI. | |
147 | */ | |
148 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
149 | { | |
150 | return !regs->softe; | |
151 | } | |
152 | ||
153 | #endif /* CONFIG_PPC64 */ | |
154 | ||
cdd6c482 | 155 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 156 | |
cdd6c482 | 157 | void perf_event_print_debug(void) |
4574910e PM |
158 | { |
159 | } | |
160 | ||
4574910e | 161 | /* |
cdd6c482 | 162 | * Read one performance monitor event (PMC). |
4574910e PM |
163 | */ |
164 | static unsigned long read_pmc(int idx) | |
165 | { | |
166 | unsigned long val; | |
167 | ||
168 | switch (idx) { | |
169 | case 1: | |
170 | val = mfspr(SPRN_PMC1); | |
171 | break; | |
172 | case 2: | |
173 | val = mfspr(SPRN_PMC2); | |
174 | break; | |
175 | case 3: | |
176 | val = mfspr(SPRN_PMC3); | |
177 | break; | |
178 | case 4: | |
179 | val = mfspr(SPRN_PMC4); | |
180 | break; | |
181 | case 5: | |
182 | val = mfspr(SPRN_PMC5); | |
183 | break; | |
184 | case 6: | |
185 | val = mfspr(SPRN_PMC6); | |
186 | break; | |
98fb1807 | 187 | #ifdef CONFIG_PPC64 |
4574910e PM |
188 | case 7: |
189 | val = mfspr(SPRN_PMC7); | |
190 | break; | |
191 | case 8: | |
192 | val = mfspr(SPRN_PMC8); | |
193 | break; | |
98fb1807 | 194 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
195 | default: |
196 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
197 | val = 0; | |
198 | } | |
199 | return val; | |
200 | } | |
201 | ||
202 | /* | |
203 | * Write one PMC. | |
204 | */ | |
205 | static void write_pmc(int idx, unsigned long val) | |
206 | { | |
207 | switch (idx) { | |
208 | case 1: | |
209 | mtspr(SPRN_PMC1, val); | |
210 | break; | |
211 | case 2: | |
212 | mtspr(SPRN_PMC2, val); | |
213 | break; | |
214 | case 3: | |
215 | mtspr(SPRN_PMC3, val); | |
216 | break; | |
217 | case 4: | |
218 | mtspr(SPRN_PMC4, val); | |
219 | break; | |
220 | case 5: | |
221 | mtspr(SPRN_PMC5, val); | |
222 | break; | |
223 | case 6: | |
224 | mtspr(SPRN_PMC6, val); | |
225 | break; | |
98fb1807 | 226 | #ifdef CONFIG_PPC64 |
4574910e PM |
227 | case 7: |
228 | mtspr(SPRN_PMC7, val); | |
229 | break; | |
230 | case 8: | |
231 | mtspr(SPRN_PMC8, val); | |
232 | break; | |
98fb1807 | 233 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
234 | default: |
235 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
236 | } | |
237 | } | |
238 | ||
239 | /* | |
240 | * Check if a set of events can all go on the PMU at once. | |
241 | * If they can't, this will look at alternative codes for the events | |
242 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 243 | * The feasible set is returned in event_id[]. |
4574910e | 244 | */ |
cdd6c482 IM |
245 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
246 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 247 | int n_ev) |
4574910e | 248 | { |
448d64f8 | 249 | unsigned long mask, value, nv; |
cdd6c482 IM |
250 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
251 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 252 | int i, j; |
448d64f8 PM |
253 | unsigned long addf = ppmu->add_fields; |
254 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 255 | |
cdd6c482 | 256 | if (n_ev > ppmu->n_event) |
4574910e PM |
257 | return -1; |
258 | ||
259 | /* First see if the events will go on as-is */ | |
260 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 261 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
262 | && !ppmu->limited_pmc_event(event_id[i])) { |
263 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 264 | cpuhw->alternatives[i]); |
cdd6c482 | 265 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 266 | } |
cdd6c482 | 267 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 268 | &cpuhw->avalues[i][0])) |
4574910e | 269 | return -1; |
4574910e PM |
270 | } |
271 | value = mask = 0; | |
272 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
273 | nv = (value | cpuhw->avalues[i][0]) + |
274 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 275 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
276 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
277 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
278 | break; |
279 | value = nv; | |
e51ee31e | 280 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
281 | } |
282 | if (i == n_ev) | |
283 | return 0; /* all OK */ | |
284 | ||
285 | /* doesn't work, gather alternatives... */ | |
286 | if (!ppmu->get_alternatives) | |
287 | return -1; | |
288 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 289 | choice[i] = 0; |
cdd6c482 | 290 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 291 | cpuhw->alternatives[i]); |
4574910e | 292 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
293 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
294 | &cpuhw->amasks[i][j], | |
295 | &cpuhw->avalues[i][j]); | |
4574910e PM |
296 | } |
297 | ||
298 | /* enumerate all possibilities and see if any will work */ | |
299 | i = 0; | |
300 | j = -1; | |
301 | value = mask = nv = 0; | |
302 | while (i < n_ev) { | |
303 | if (j >= 0) { | |
304 | /* we're backtracking, restore context */ | |
305 | value = svalues[i]; | |
306 | mask = smasks[i]; | |
307 | j = choice[i]; | |
308 | } | |
309 | /* | |
cdd6c482 | 310 | * See if any alternative k for event_id i, |
4574910e PM |
311 | * where k > j, will satisfy the constraints. |
312 | */ | |
313 | while (++j < n_alt[i]) { | |
e51ee31e PM |
314 | nv = (value | cpuhw->avalues[i][j]) + |
315 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 316 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
317 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
318 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
319 | break; |
320 | } | |
321 | if (j >= n_alt[i]) { | |
322 | /* | |
323 | * No feasible alternative, backtrack | |
cdd6c482 | 324 | * to event_id i-1 and continue enumerating its |
4574910e PM |
325 | * alternatives from where we got up to. |
326 | */ | |
327 | if (--i < 0) | |
328 | return -1; | |
329 | } else { | |
330 | /* | |
cdd6c482 IM |
331 | * Found a feasible alternative for event_id i, |
332 | * remember where we got up to with this event_id, | |
333 | * go on to the next event_id, and start with | |
4574910e PM |
334 | * the first alternative for it. |
335 | */ | |
336 | choice[i] = j; | |
337 | svalues[i] = value; | |
338 | smasks[i] = mask; | |
339 | value = nv; | |
e51ee31e | 340 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
341 | ++i; |
342 | j = -1; | |
343 | } | |
344 | } | |
345 | ||
346 | /* OK, we have a feasible combination, tell the caller the solution */ | |
347 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 348 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
349 | return 0; |
350 | } | |
351 | ||
0475f9ea | 352 | /* |
cdd6c482 | 353 | * Check if newly-added events have consistent settings for |
0475f9ea | 354 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 355 | * added events. |
0475f9ea | 356 | */ |
cdd6c482 | 357 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 358 | int n_prev, int n_new) |
0475f9ea | 359 | { |
ab7ef2e5 PM |
360 | int eu = 0, ek = 0, eh = 0; |
361 | int i, n, first; | |
cdd6c482 | 362 | struct perf_event *event; |
0475f9ea PM |
363 | |
364 | n = n_prev + n_new; | |
365 | if (n <= 1) | |
366 | return 0; | |
367 | ||
ab7ef2e5 PM |
368 | first = 1; |
369 | for (i = 0; i < n; ++i) { | |
370 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
371 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
372 | continue; | |
373 | } | |
cdd6c482 | 374 | event = ctrs[i]; |
ab7ef2e5 | 375 | if (first) { |
cdd6c482 IM |
376 | eu = event->attr.exclude_user; |
377 | ek = event->attr.exclude_kernel; | |
378 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 379 | first = 0; |
cdd6c482 IM |
380 | } else if (event->attr.exclude_user != eu || |
381 | event->attr.exclude_kernel != ek || | |
382 | event->attr.exclude_hv != eh) { | |
0475f9ea | 383 | return -EAGAIN; |
ab7ef2e5 | 384 | } |
0475f9ea | 385 | } |
ab7ef2e5 PM |
386 | |
387 | if (eu || ek || eh) | |
388 | for (i = 0; i < n; ++i) | |
389 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
390 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
391 | ||
0475f9ea PM |
392 | return 0; |
393 | } | |
394 | ||
cdd6c482 | 395 | static void power_pmu_read(struct perf_event *event) |
4574910e | 396 | { |
98fb1807 | 397 | s64 val, delta, prev; |
4574910e | 398 | |
cdd6c482 | 399 | if (!event->hw.idx) |
4574910e PM |
400 | return; |
401 | /* | |
402 | * Performance monitor interrupts come even when interrupts | |
403 | * are soft-disabled, as long as interrupts are hard-enabled. | |
404 | * Therefore we treat them like NMIs. | |
405 | */ | |
406 | do { | |
cdd6c482 | 407 | prev = atomic64_read(&event->hw.prev_count); |
4574910e | 408 | barrier(); |
cdd6c482 IM |
409 | val = read_pmc(event->hw.idx); |
410 | } while (atomic64_cmpxchg(&event->hw.prev_count, prev, val) != prev); | |
4574910e | 411 | |
cdd6c482 | 412 | /* The events are only 32 bits wide */ |
4574910e | 413 | delta = (val - prev) & 0xfffffffful; |
cdd6c482 IM |
414 | atomic64_add(delta, &event->count); |
415 | atomic64_sub(delta, &event->hw.period_left); | |
4574910e PM |
416 | } |
417 | ||
ab7ef2e5 PM |
418 | /* |
419 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
420 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 421 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
422 | */ |
423 | static int is_limited_pmc(int pmcnum) | |
424 | { | |
0bbd0d4b PM |
425 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
426 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
427 | } |
428 | ||
cdd6c482 | 429 | static void freeze_limited_events(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
430 | unsigned long pmc5, unsigned long pmc6) |
431 | { | |
cdd6c482 | 432 | struct perf_event *event; |
ab7ef2e5 PM |
433 | u64 val, prev, delta; |
434 | int i; | |
435 | ||
436 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
cdd6c482 IM |
437 | event = cpuhw->limited_event[i]; |
438 | if (!event->hw.idx) | |
ab7ef2e5 | 439 | continue; |
cdd6c482 IM |
440 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
441 | prev = atomic64_read(&event->hw.prev_count); | |
442 | event->hw.idx = 0; | |
ab7ef2e5 | 443 | delta = (val - prev) & 0xfffffffful; |
cdd6c482 | 444 | atomic64_add(delta, &event->count); |
ab7ef2e5 PM |
445 | } |
446 | } | |
447 | ||
cdd6c482 | 448 | static void thaw_limited_events(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
449 | unsigned long pmc5, unsigned long pmc6) |
450 | { | |
cdd6c482 | 451 | struct perf_event *event; |
ab7ef2e5 PM |
452 | u64 val; |
453 | int i; | |
454 | ||
455 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
cdd6c482 IM |
456 | event = cpuhw->limited_event[i]; |
457 | event->hw.idx = cpuhw->limited_hwidx[i]; | |
458 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
459 | atomic64_set(&event->hw.prev_count, val); | |
460 | perf_event_update_userpage(event); | |
ab7ef2e5 PM |
461 | } |
462 | } | |
463 | ||
464 | /* | |
cdd6c482 | 465 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 466 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
467 | * other events. We try to keep the values from the limited |
468 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 469 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
470 | * the limited events as small and consistent as possible. |
471 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
472 | * both, and always in the same order, to minimize variability, |
473 | * and do it inside the same asm that writes MMCR0. | |
474 | */ | |
cdd6c482 | 475 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
476 | { |
477 | unsigned long pmc5, pmc6; | |
478 | ||
479 | if (!cpuhw->n_limited) { | |
480 | mtspr(SPRN_MMCR0, mmcr0); | |
481 | return; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
486 | * To ensure we don't get a performance monitor interrupt |
487 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 488 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 489 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
490 | */ |
491 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
492 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
493 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
494 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
495 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
496 | ||
497 | if (mmcr0 & MMCR0_FC) | |
cdd6c482 | 498 | freeze_limited_events(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 499 | else |
cdd6c482 | 500 | thaw_limited_events(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
501 | |
502 | /* | |
cdd6c482 | 503 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
504 | * enable bits, if necessary. |
505 | */ | |
506 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
507 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
508 | } |
509 | ||
4574910e | 510 | /* |
cdd6c482 IM |
511 | * Disable all events to prevent PMU interrupts and to allow |
512 | * events to be added or removed. | |
4574910e | 513 | */ |
9e35ad38 | 514 | void hw_perf_disable(void) |
4574910e | 515 | { |
cdd6c482 | 516 | struct cpu_hw_events *cpuhw; |
4574910e PM |
517 | unsigned long flags; |
518 | ||
f36a1a13 PM |
519 | if (!ppmu) |
520 | return; | |
4574910e | 521 | local_irq_save(flags); |
cdd6c482 | 522 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 523 | |
448d64f8 | 524 | if (!cpuhw->disabled) { |
4574910e PM |
525 | cpuhw->disabled = 1; |
526 | cpuhw->n_added = 0; | |
527 | ||
01d0287f PM |
528 | /* |
529 | * Check if we ever enabled the PMU on this cpu. | |
530 | */ | |
531 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 532 | ppc_enable_pmcs(); |
01d0287f PM |
533 | cpuhw->pmcs_enabled = 1; |
534 | } | |
535 | ||
f708223d PM |
536 | /* |
537 | * Disable instruction sampling if it was enabled | |
538 | */ | |
539 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
540 | mtspr(SPRN_MMCRA, | |
541 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
542 | mb(); | |
543 | } | |
544 | ||
4574910e | 545 | /* |
cdd6c482 | 546 | * Set the 'freeze events' bit. |
4574910e | 547 | * The barrier is to make sure the mtspr has been |
cdd6c482 | 548 | * executed and the PMU has frozen the events |
4574910e PM |
549 | * before we return. |
550 | */ | |
ab7ef2e5 | 551 | write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); |
4574910e PM |
552 | mb(); |
553 | } | |
554 | local_irq_restore(flags); | |
4574910e PM |
555 | } |
556 | ||
557 | /* | |
cdd6c482 IM |
558 | * Re-enable all events if disable == 0. |
559 | * If we were previously disabled and events were added, then | |
4574910e PM |
560 | * put the new config on the PMU. |
561 | */ | |
9e35ad38 | 562 | void hw_perf_enable(void) |
4574910e | 563 | { |
cdd6c482 IM |
564 | struct perf_event *event; |
565 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
566 | unsigned long flags; |
567 | long i; | |
568 | unsigned long val; | |
569 | s64 left; | |
cdd6c482 | 570 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
571 | int n_lim; |
572 | int idx; | |
4574910e | 573 | |
f36a1a13 PM |
574 | if (!ppmu) |
575 | return; | |
4574910e | 576 | local_irq_save(flags); |
cdd6c482 | 577 | cpuhw = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
578 | if (!cpuhw->disabled) { |
579 | local_irq_restore(flags); | |
580 | return; | |
581 | } | |
4574910e PM |
582 | cpuhw->disabled = 0; |
583 | ||
584 | /* | |
cdd6c482 | 585 | * If we didn't change anything, or only removed events, |
4574910e PM |
586 | * no need to recalculate MMCR* settings and reset the PMCs. |
587 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 588 | * (possibly updated for removal of events). |
4574910e PM |
589 | */ |
590 | if (!cpuhw->n_added) { | |
f708223d | 591 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 592 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
cdd6c482 | 593 | if (cpuhw->n_events == 0) |
a6dbf93a | 594 | ppc_set_pmu_inuse(0); |
f708223d | 595 | goto out_enable; |
4574910e PM |
596 | } |
597 | ||
598 | /* | |
cdd6c482 | 599 | * Compute MMCR* values for the new set of events |
4574910e | 600 | */ |
cdd6c482 | 601 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
602 | cpuhw->mmcr)) { |
603 | /* shouldn't ever get here */ | |
604 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
605 | goto out; | |
606 | } | |
607 | ||
0475f9ea PM |
608 | /* |
609 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
610 | * attr.exclude_* bits for the first event. |
611 | * We have already checked that all events have the | |
612 | * same values for these bits as the first event. | |
0475f9ea | 613 | */ |
cdd6c482 IM |
614 | event = cpuhw->event[0]; |
615 | if (event->attr.exclude_user) | |
0475f9ea | 616 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
617 | if (event->attr.exclude_kernel) |
618 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
619 | if (event->attr.exclude_hv) | |
0475f9ea PM |
620 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
621 | ||
4574910e PM |
622 | /* |
623 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
624 | * bit set and set the hardware events to their initial values. |
625 | * Then unfreeze the events. | |
4574910e | 626 | */ |
a6dbf93a | 627 | ppc_set_pmu_inuse(1); |
f708223d | 628 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
629 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
630 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
631 | | MMCR0_FC); | |
632 | ||
633 | /* | |
cdd6c482 | 634 | * Read off any pre-existing events that need to move |
4574910e PM |
635 | * to another PMC. |
636 | */ | |
cdd6c482 IM |
637 | for (i = 0; i < cpuhw->n_events; ++i) { |
638 | event = cpuhw->event[i]; | |
639 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
640 | power_pmu_read(event); | |
641 | write_pmc(event->hw.idx, 0); | |
642 | event->hw.idx = 0; | |
4574910e PM |
643 | } |
644 | } | |
645 | ||
646 | /* | |
cdd6c482 | 647 | * Initialize the PMCs for all the new and moved events. |
4574910e | 648 | */ |
ab7ef2e5 | 649 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
650 | for (i = 0; i < cpuhw->n_events; ++i) { |
651 | event = cpuhw->event[i]; | |
652 | if (event->hw.idx) | |
4574910e | 653 | continue; |
ab7ef2e5 PM |
654 | idx = hwc_index[i] + 1; |
655 | if (is_limited_pmc(idx)) { | |
cdd6c482 | 656 | cpuhw->limited_event[n_lim] = event; |
ab7ef2e5 PM |
657 | cpuhw->limited_hwidx[n_lim] = idx; |
658 | ++n_lim; | |
659 | continue; | |
660 | } | |
4574910e | 661 | val = 0; |
cdd6c482 IM |
662 | if (event->hw.sample_period) { |
663 | left = atomic64_read(&event->hw.period_left); | |
4574910e PM |
664 | if (left < 0x80000000L) |
665 | val = 0x80000000L - left; | |
666 | } | |
cdd6c482 IM |
667 | atomic64_set(&event->hw.prev_count, val); |
668 | event->hw.idx = idx; | |
ab7ef2e5 | 669 | write_pmc(idx, val); |
cdd6c482 | 670 | perf_event_update_userpage(event); |
4574910e | 671 | } |
ab7ef2e5 | 672 | cpuhw->n_limited = n_lim; |
4574910e | 673 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
674 | |
675 | out_enable: | |
676 | mb(); | |
ab7ef2e5 | 677 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 678 | |
f708223d PM |
679 | /* |
680 | * Enable instruction sampling if necessary | |
681 | */ | |
682 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
683 | mb(); | |
684 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
685 | } | |
686 | ||
4574910e PM |
687 | out: |
688 | local_irq_restore(flags); | |
689 | } | |
690 | ||
cdd6c482 IM |
691 | static int collect_events(struct perf_event *group, int max_count, |
692 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 693 | unsigned int *flags) |
4574910e PM |
694 | { |
695 | int n = 0; | |
cdd6c482 | 696 | struct perf_event *event; |
4574910e | 697 | |
cdd6c482 | 698 | if (!is_software_event(group)) { |
4574910e PM |
699 | if (n >= max_count) |
700 | return -1; | |
701 | ctrs[n] = group; | |
cdd6c482 | 702 | flags[n] = group->hw.event_base; |
4574910e PM |
703 | events[n++] = group->hw.config; |
704 | } | |
cdd6c482 IM |
705 | list_for_each_entry(event, &group->sibling_list, list_entry) { |
706 | if (!is_software_event(event) && | |
707 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
708 | if (n >= max_count) |
709 | return -1; | |
cdd6c482 IM |
710 | ctrs[n] = event; |
711 | flags[n] = event->hw.event_base; | |
712 | events[n++] = event->hw.config; | |
4574910e PM |
713 | } |
714 | } | |
715 | return n; | |
716 | } | |
717 | ||
cdd6c482 | 718 | static void event_sched_in(struct perf_event *event, int cpu) |
4574910e | 719 | { |
cdd6c482 IM |
720 | event->state = PERF_EVENT_STATE_ACTIVE; |
721 | event->oncpu = cpu; | |
722 | event->tstamp_running += event->ctx->time - event->tstamp_stopped; | |
723 | if (is_software_event(event)) | |
724 | event->pmu->enable(event); | |
4574910e PM |
725 | } |
726 | ||
727 | /* | |
cdd6c482 | 728 | * Called to enable a whole group of events. |
4574910e PM |
729 | * Returns 1 if the group was enabled, or -EAGAIN if it could not be. |
730 | * Assumes the caller has disabled interrupts and has | |
731 | * frozen the PMU with hw_perf_save_disable. | |
732 | */ | |
cdd6c482 | 733 | int hw_perf_group_sched_in(struct perf_event *group_leader, |
4574910e | 734 | struct perf_cpu_context *cpuctx, |
cdd6c482 | 735 | struct perf_event_context *ctx, int cpu) |
4574910e | 736 | { |
cdd6c482 | 737 | struct cpu_hw_events *cpuhw; |
4574910e | 738 | long i, n, n0; |
cdd6c482 | 739 | struct perf_event *sub; |
4574910e | 740 | |
f36a1a13 PM |
741 | if (!ppmu) |
742 | return 0; | |
cdd6c482 IM |
743 | cpuhw = &__get_cpu_var(cpu_hw_events); |
744 | n0 = cpuhw->n_events; | |
745 | n = collect_events(group_leader, ppmu->n_event - n0, | |
746 | &cpuhw->event[n0], &cpuhw->events[n0], | |
ab7ef2e5 | 747 | &cpuhw->flags[n0]); |
4574910e PM |
748 | if (n < 0) |
749 | return -EAGAIN; | |
cdd6c482 | 750 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, n)) |
0475f9ea | 751 | return -EAGAIN; |
e51ee31e | 752 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0); |
ab7ef2e5 | 753 | if (i < 0) |
4574910e | 754 | return -EAGAIN; |
cdd6c482 | 755 | cpuhw->n_events = n0 + n; |
4574910e PM |
756 | cpuhw->n_added += n; |
757 | ||
758 | /* | |
cdd6c482 IM |
759 | * OK, this group can go on; update event states etc., |
760 | * and enable any software events | |
4574910e PM |
761 | */ |
762 | for (i = n0; i < n0 + n; ++i) | |
cdd6c482 | 763 | cpuhw->event[i]->hw.config = cpuhw->events[i]; |
3b6f9e5c | 764 | cpuctx->active_oncpu += n; |
4574910e | 765 | n = 1; |
cdd6c482 | 766 | event_sched_in(group_leader, cpu); |
4574910e | 767 | list_for_each_entry(sub, &group_leader->sibling_list, list_entry) { |
cdd6c482 IM |
768 | if (sub->state != PERF_EVENT_STATE_OFF) { |
769 | event_sched_in(sub, cpu); | |
4574910e PM |
770 | ++n; |
771 | } | |
772 | } | |
4574910e PM |
773 | ctx->nr_active += n; |
774 | ||
775 | return 1; | |
776 | } | |
777 | ||
778 | /* | |
cdd6c482 IM |
779 | * Add a event to the PMU. |
780 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 781 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
782 | * actual work of reconfiguring the PMU. |
783 | */ | |
cdd6c482 | 784 | static int power_pmu_enable(struct perf_event *event) |
4574910e | 785 | { |
cdd6c482 | 786 | struct cpu_hw_events *cpuhw; |
4574910e | 787 | unsigned long flags; |
4574910e PM |
788 | int n0; |
789 | int ret = -EAGAIN; | |
790 | ||
791 | local_irq_save(flags); | |
9e35ad38 | 792 | perf_disable(); |
4574910e PM |
793 | |
794 | /* | |
cdd6c482 | 795 | * Add the event to the list (if there is room) |
4574910e PM |
796 | * and check whether the total set is still feasible. |
797 | */ | |
cdd6c482 IM |
798 | cpuhw = &__get_cpu_var(cpu_hw_events); |
799 | n0 = cpuhw->n_events; | |
800 | if (n0 >= ppmu->n_event) | |
4574910e | 801 | goto out; |
cdd6c482 IM |
802 | cpuhw->event[n0] = event; |
803 | cpuhw->events[n0] = event->hw.config; | |
804 | cpuhw->flags[n0] = event->hw.event_base; | |
805 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) | |
0475f9ea | 806 | goto out; |
e51ee31e | 807 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e PM |
808 | goto out; |
809 | ||
cdd6c482 IM |
810 | event->hw.config = cpuhw->events[n0]; |
811 | ++cpuhw->n_events; | |
4574910e PM |
812 | ++cpuhw->n_added; |
813 | ||
814 | ret = 0; | |
815 | out: | |
9e35ad38 | 816 | perf_enable(); |
4574910e PM |
817 | local_irq_restore(flags); |
818 | return ret; | |
819 | } | |
820 | ||
821 | /* | |
cdd6c482 | 822 | * Remove a event from the PMU. |
4574910e | 823 | */ |
cdd6c482 | 824 | static void power_pmu_disable(struct perf_event *event) |
4574910e | 825 | { |
cdd6c482 | 826 | struct cpu_hw_events *cpuhw; |
4574910e | 827 | long i; |
4574910e PM |
828 | unsigned long flags; |
829 | ||
830 | local_irq_save(flags); | |
9e35ad38 | 831 | perf_disable(); |
4574910e | 832 | |
cdd6c482 IM |
833 | power_pmu_read(event); |
834 | ||
835 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
836 | for (i = 0; i < cpuhw->n_events; ++i) { | |
837 | if (event == cpuhw->event[i]) { | |
838 | while (++i < cpuhw->n_events) | |
839 | cpuhw->event[i-1] = cpuhw->event[i]; | |
840 | --cpuhw->n_events; | |
841 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
842 | if (event->hw.idx) { | |
843 | write_pmc(event->hw.idx, 0); | |
844 | event->hw.idx = 0; | |
ab7ef2e5 | 845 | } |
cdd6c482 | 846 | perf_event_update_userpage(event); |
4574910e PM |
847 | break; |
848 | } | |
849 | } | |
ab7ef2e5 | 850 | for (i = 0; i < cpuhw->n_limited; ++i) |
cdd6c482 | 851 | if (event == cpuhw->limited_event[i]) |
ab7ef2e5 PM |
852 | break; |
853 | if (i < cpuhw->n_limited) { | |
854 | while (++i < cpuhw->n_limited) { | |
cdd6c482 | 855 | cpuhw->limited_event[i-1] = cpuhw->limited_event[i]; |
ab7ef2e5 PM |
856 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
857 | } | |
858 | --cpuhw->n_limited; | |
859 | } | |
cdd6c482 IM |
860 | if (cpuhw->n_events == 0) { |
861 | /* disable exceptions if no events are running */ | |
4574910e PM |
862 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
863 | } | |
864 | ||
9e35ad38 | 865 | perf_enable(); |
4574910e PM |
866 | local_irq_restore(flags); |
867 | } | |
868 | ||
8a7b8cb9 | 869 | /* |
cdd6c482 | 870 | * Re-enable interrupts on a event after they were throttled |
8a7b8cb9 PM |
871 | * because they were coming too fast. |
872 | */ | |
cdd6c482 | 873 | static void power_pmu_unthrottle(struct perf_event *event) |
8a7b8cb9 PM |
874 | { |
875 | s64 val, left; | |
876 | unsigned long flags; | |
877 | ||
cdd6c482 | 878 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 PM |
879 | return; |
880 | local_irq_save(flags); | |
881 | perf_disable(); | |
cdd6c482 IM |
882 | power_pmu_read(event); |
883 | left = event->hw.sample_period; | |
884 | event->hw.last_period = left; | |
8a7b8cb9 PM |
885 | val = 0; |
886 | if (left < 0x80000000L) | |
887 | val = 0x80000000L - left; | |
cdd6c482 IM |
888 | write_pmc(event->hw.idx, val); |
889 | atomic64_set(&event->hw.prev_count, val); | |
890 | atomic64_set(&event->hw.period_left, left); | |
891 | perf_event_update_userpage(event); | |
8a7b8cb9 PM |
892 | perf_enable(); |
893 | local_irq_restore(flags); | |
894 | } | |
895 | ||
4aeb0b42 RR |
896 | struct pmu power_pmu = { |
897 | .enable = power_pmu_enable, | |
898 | .disable = power_pmu_disable, | |
899 | .read = power_pmu_read, | |
8a7b8cb9 | 900 | .unthrottle = power_pmu_unthrottle, |
4574910e PM |
901 | }; |
902 | ||
ab7ef2e5 | 903 | /* |
cdd6c482 | 904 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 905 | * or 0 if not. |
cdd6c482 | 906 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
907 | * that a limited PMC can count, doesn't require interrupts, and |
908 | * doesn't exclude any processor mode. | |
909 | */ | |
cdd6c482 | 910 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
911 | unsigned int flags) |
912 | { | |
913 | int n; | |
ef923214 | 914 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 915 | |
cdd6c482 IM |
916 | if (event->attr.exclude_user |
917 | || event->attr.exclude_kernel | |
918 | || event->attr.exclude_hv | |
919 | || event->attr.sample_period) | |
ab7ef2e5 PM |
920 | return 0; |
921 | ||
922 | if (ppmu->limited_pmc_event(ev)) | |
923 | return 1; | |
924 | ||
925 | /* | |
cdd6c482 | 926 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
927 | * see if any alternative code goes on a limited PMC. |
928 | */ | |
929 | if (!ppmu->get_alternatives) | |
930 | return 0; | |
931 | ||
932 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
933 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 934 | |
ef923214 | 935 | return n > 0; |
ab7ef2e5 PM |
936 | } |
937 | ||
938 | /* | |
cdd6c482 IM |
939 | * Find an alternative event_id that goes on a normal PMC, if possible, |
940 | * and return the event_id code, or 0 if there is no such alternative. | |
941 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 942 | */ |
ef923214 | 943 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 944 | { |
ef923214 | 945 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
946 | int n; |
947 | ||
948 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
949 | n = ppmu->get_alternatives(ev, flags, alt); | |
950 | if (!n) | |
951 | return 0; | |
952 | return alt[0]; | |
953 | } | |
954 | ||
cdd6c482 IM |
955 | /* Number of perf_events counting hardware events */ |
956 | static atomic_t num_events; | |
7595d63b PM |
957 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
958 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
959 | ||
960 | /* | |
cdd6c482 | 961 | * Release the PMU if this is the last perf_event. |
7595d63b | 962 | */ |
cdd6c482 | 963 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 964 | { |
cdd6c482 | 965 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 966 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 967 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
968 | release_pmc_hardware(); |
969 | mutex_unlock(&pmc_reserve_mutex); | |
970 | } | |
971 | } | |
972 | ||
106b506c | 973 | /* |
cdd6c482 | 974 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
975 | */ |
976 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
977 | { | |
978 | unsigned long type, op, result; | |
979 | int ev; | |
980 | ||
981 | if (!ppmu->cache_events) | |
982 | return -EINVAL; | |
983 | ||
984 | /* unpack config */ | |
985 | type = config & 0xff; | |
986 | op = (config >> 8) & 0xff; | |
987 | result = (config >> 16) & 0xff; | |
988 | ||
989 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
990 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
991 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
992 | return -EINVAL; | |
993 | ||
994 | ev = (*ppmu->cache_events)[type][op][result]; | |
995 | if (ev == 0) | |
996 | return -EOPNOTSUPP; | |
997 | if (ev == -1) | |
998 | return -EINVAL; | |
999 | *eventp = ev; | |
1000 | return 0; | |
1001 | } | |
1002 | ||
cdd6c482 | 1003 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
4574910e | 1004 | { |
ef923214 PM |
1005 | u64 ev; |
1006 | unsigned long flags; | |
cdd6c482 IM |
1007 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1008 | u64 events[MAX_HWEVENTS]; | |
1009 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1010 | int n; |
7595d63b | 1011 | int err; |
cdd6c482 | 1012 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1013 | |
1014 | if (!ppmu) | |
d5d2bc0d | 1015 | return ERR_PTR(-ENXIO); |
cdd6c482 | 1016 | switch (event->attr.type) { |
106b506c | 1017 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1018 | ev = event->attr.config; |
9aaa131a | 1019 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
d5d2bc0d | 1020 | return ERR_PTR(-EOPNOTSUPP); |
4574910e | 1021 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1022 | break; |
1023 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1024 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c PM |
1025 | if (err) |
1026 | return ERR_PTR(err); | |
1027 | break; | |
1028 | case PERF_TYPE_RAW: | |
cdd6c482 | 1029 | ev = event->attr.config; |
106b506c | 1030 | break; |
90c8f954 PM |
1031 | default: |
1032 | return ERR_PTR(-EINVAL); | |
4574910e | 1033 | } |
cdd6c482 IM |
1034 | event->hw.config_base = ev; |
1035 | event->hw.idx = 0; | |
4574910e | 1036 | |
0475f9ea PM |
1037 | /* |
1038 | * If we are not running on a hypervisor, force the | |
1039 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1040 | * the user set it to. |
0475f9ea PM |
1041 | */ |
1042 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1043 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1044 | |
1045 | /* | |
cdd6c482 | 1046 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1047 | * PM_RUN_* events interchangeably with their non RUN_* |
1048 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1049 | * XXX we should check if the task is an idle task. | |
1050 | */ | |
1051 | flags = 0; | |
cdd6c482 | 1052 | if (event->ctx->task) |
ab7ef2e5 PM |
1053 | flags |= PPMU_ONLY_COUNT_RUN; |
1054 | ||
1055 | /* | |
cdd6c482 IM |
1056 | * If this machine has limited events, check whether this |
1057 | * event_id could go on a limited event. | |
ab7ef2e5 | 1058 | */ |
0bbd0d4b | 1059 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1060 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1061 | flags |= PPMU_LIMITED_PMC_OK; |
1062 | } else if (ppmu->limited_pmc_event(ev)) { | |
1063 | /* | |
cdd6c482 | 1064 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1065 | * but we can't use a limited PMC; see if any |
1066 | * alternative goes on a normal PMC. | |
1067 | */ | |
1068 | ev = normal_pmc_alternative(ev, flags); | |
1069 | if (!ev) | |
1070 | return ERR_PTR(-EINVAL); | |
1071 | } | |
1072 | } | |
1073 | ||
4574910e PM |
1074 | /* |
1075 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1076 | * other hardware events in the group. We assume the event |
4574910e PM |
1077 | * hasn't been linked into its leader's sibling list at this point. |
1078 | */ | |
1079 | n = 0; | |
cdd6c482 IM |
1080 | if (event->group_leader != event) { |
1081 | n = collect_events(event->group_leader, ppmu->n_event - 1, | |
ab7ef2e5 | 1082 | ctrs, events, cflags); |
4574910e | 1083 | if (n < 0) |
d5d2bc0d | 1084 | return ERR_PTR(-EINVAL); |
4574910e | 1085 | } |
0475f9ea | 1086 | events[n] = ev; |
cdd6c482 | 1087 | ctrs[n] = event; |
ab7ef2e5 PM |
1088 | cflags[n] = flags; |
1089 | if (check_excludes(ctrs, cflags, n, 1)) | |
d5d2bc0d | 1090 | return ERR_PTR(-EINVAL); |
e51ee31e | 1091 | |
cdd6c482 | 1092 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1093 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
cdd6c482 | 1094 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1095 | if (err) |
d5d2bc0d | 1096 | return ERR_PTR(-EINVAL); |
4574910e | 1097 | |
cdd6c482 IM |
1098 | event->hw.config = events[n]; |
1099 | event->hw.event_base = cflags[n]; | |
1100 | event->hw.last_period = event->hw.sample_period; | |
1101 | atomic64_set(&event->hw.period_left, event->hw.last_period); | |
7595d63b PM |
1102 | |
1103 | /* | |
1104 | * See if we need to reserve the PMU. | |
cdd6c482 | 1105 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1106 | * mutex to ensure that we don't race with another task doing |
1107 | * reserve_pmc_hardware or release_pmc_hardware. | |
1108 | */ | |
1109 | err = 0; | |
cdd6c482 | 1110 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1111 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1112 | if (atomic_read(&num_events) == 0 && |
1113 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1114 | err = -EBUSY; |
1115 | else | |
cdd6c482 | 1116 | atomic_inc(&num_events); |
7595d63b PM |
1117 | mutex_unlock(&pmc_reserve_mutex); |
1118 | } | |
cdd6c482 | 1119 | event->destroy = hw_perf_event_destroy; |
7595d63b PM |
1120 | |
1121 | if (err) | |
d5d2bc0d | 1122 | return ERR_PTR(err); |
4aeb0b42 | 1123 | return &power_pmu; |
4574910e PM |
1124 | } |
1125 | ||
4574910e | 1126 | /* |
cdd6c482 | 1127 | * A event has overflowed; update its count and record |
4574910e PM |
1128 | * things if requested. Note that interrupts are hard-disabled |
1129 | * here so there is no possibility of being interrupted. | |
1130 | */ | |
cdd6c482 | 1131 | static void record_and_restart(struct perf_event *event, unsigned long val, |
ca8f2d7f | 1132 | struct pt_regs *regs, int nmi) |
4574910e | 1133 | { |
cdd6c482 | 1134 | u64 period = event->hw.sample_period; |
4574910e PM |
1135 | s64 prev, delta, left; |
1136 | int record = 0; | |
1137 | ||
1138 | /* we don't have to worry about interrupts here */ | |
cdd6c482 | 1139 | prev = atomic64_read(&event->hw.prev_count); |
4574910e | 1140 | delta = (val - prev) & 0xfffffffful; |
cdd6c482 | 1141 | atomic64_add(delta, &event->count); |
4574910e PM |
1142 | |
1143 | /* | |
cdd6c482 | 1144 | * See if the total period for this event has expired, |
4574910e PM |
1145 | * and update for the next period. |
1146 | */ | |
1147 | val = 0; | |
cdd6c482 | 1148 | left = atomic64_read(&event->hw.period_left) - delta; |
60db5e09 | 1149 | if (period) { |
4574910e | 1150 | if (left <= 0) { |
60db5e09 | 1151 | left += period; |
4574910e | 1152 | if (left <= 0) |
60db5e09 | 1153 | left = period; |
4574910e PM |
1154 | record = 1; |
1155 | } | |
98fb1807 PM |
1156 | if (left < 0x80000000LL) |
1157 | val = 0x80000000LL - left; | |
4574910e | 1158 | } |
4574910e PM |
1159 | |
1160 | /* | |
1161 | * Finally record data if requested. | |
1162 | */ | |
0bbd0d4b | 1163 | if (record) { |
df1a132b | 1164 | struct perf_sample_data data = { |
9e350de3 | 1165 | .addr = 0, |
cdd6c482 | 1166 | .period = event->hw.last_period, |
df1a132b PZ |
1167 | }; |
1168 | ||
cdd6c482 | 1169 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1170 | perf_get_data_addr(regs, &data.addr); |
1171 | ||
cdd6c482 | 1172 | if (perf_event_overflow(event, nmi, &data, regs)) { |
8a7b8cb9 PM |
1173 | /* |
1174 | * Interrupts are coming too fast - throttle them | |
cdd6c482 | 1175 | * by setting the event to 0, so it will be |
8a7b8cb9 | 1176 | * at least 2^30 cycles until the next interrupt |
cdd6c482 | 1177 | * (assuming each event counts at most 2 counts |
8a7b8cb9 PM |
1178 | * per cycle). |
1179 | */ | |
1180 | val = 0; | |
1181 | left = ~0ULL >> 1; | |
1182 | } | |
0bbd0d4b | 1183 | } |
8a7b8cb9 | 1184 | |
cdd6c482 IM |
1185 | write_pmc(event->hw.idx, val); |
1186 | atomic64_set(&event->hw.prev_count, val); | |
1187 | atomic64_set(&event->hw.period_left, left); | |
1188 | perf_event_update_userpage(event); | |
0bbd0d4b PM |
1189 | } |
1190 | ||
1191 | /* | |
1192 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1193 | * for an event_id. |
0bbd0d4b PM |
1194 | */ |
1195 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1196 | { | |
98fb1807 | 1197 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1198 | |
98fb1807 PM |
1199 | if (flags) |
1200 | return flags; | |
cdd6c482 IM |
1201 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1202 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1203 | } |
1204 | ||
1205 | /* | |
1206 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1207 | * for an event_id. |
0bbd0d4b PM |
1208 | */ |
1209 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1210 | { | |
0bbd0d4b | 1211 | unsigned long ip; |
0bbd0d4b PM |
1212 | |
1213 | if (TRAP(regs) != 0xf00) | |
1214 | return regs->nip; /* not a PMU interrupt */ | |
1215 | ||
98fb1807 | 1216 | ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
0bbd0d4b | 1217 | return ip; |
4574910e PM |
1218 | } |
1219 | ||
1220 | /* | |
1221 | * Performance monitor interrupt stuff | |
1222 | */ | |
cdd6c482 | 1223 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e PM |
1224 | { |
1225 | int i; | |
cdd6c482 IM |
1226 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
1227 | struct perf_event *event; | |
98fb1807 | 1228 | unsigned long val; |
925d519a | 1229 | int found = 0; |
ca8f2d7f PM |
1230 | int nmi; |
1231 | ||
ab7ef2e5 | 1232 | if (cpuhw->n_limited) |
cdd6c482 | 1233 | freeze_limited_events(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
1234 | mfspr(SPRN_PMC6)); |
1235 | ||
98fb1807 | 1236 | perf_read_regs(regs); |
0bbd0d4b | 1237 | |
98fb1807 | 1238 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
1239 | if (nmi) |
1240 | nmi_enter(); | |
1241 | else | |
1242 | irq_enter(); | |
4574910e | 1243 | |
cdd6c482 IM |
1244 | for (i = 0; i < cpuhw->n_events; ++i) { |
1245 | event = cpuhw->event[i]; | |
1246 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 1247 | continue; |
cdd6c482 | 1248 | val = read_pmc(event->hw.idx); |
4574910e | 1249 | if ((int)val < 0) { |
cdd6c482 | 1250 | /* event has overflowed */ |
4574910e | 1251 | found = 1; |
cdd6c482 | 1252 | record_and_restart(event, val, regs, nmi); |
4574910e PM |
1253 | } |
1254 | } | |
1255 | ||
1256 | /* | |
cdd6c482 IM |
1257 | * In case we didn't find and reset the event that caused |
1258 | * the interrupt, scan all events and reset any that are | |
4574910e PM |
1259 | * negative, to avoid getting continual interrupts. |
1260 | * Any that we processed in the previous loop will not be negative. | |
1261 | */ | |
1262 | if (!found) { | |
cdd6c482 | 1263 | for (i = 0; i < ppmu->n_event; ++i) { |
ab7ef2e5 PM |
1264 | if (is_limited_pmc(i + 1)) |
1265 | continue; | |
4574910e PM |
1266 | val = read_pmc(i + 1); |
1267 | if ((int)val < 0) | |
1268 | write_pmc(i + 1, 0); | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* | |
1273 | * Reset MMCR0 to its normal value. This will set PMXE and | |
cdd6c482 | 1274 | * clear FC (freeze events) and PMAO (perf mon alert occurred) |
4574910e | 1275 | * and thus allow interrupts to occur again. |
cdd6c482 | 1276 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
1277 | * we get back out of this interrupt. |
1278 | */ | |
ab7ef2e5 | 1279 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 1280 | |
ca8f2d7f PM |
1281 | if (nmi) |
1282 | nmi_exit(); | |
1283 | else | |
db4fb5ac | 1284 | irq_exit(); |
4574910e PM |
1285 | } |
1286 | ||
cdd6c482 | 1287 | void hw_perf_event_setup(int cpu) |
01d0287f | 1288 | { |
cdd6c482 | 1289 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 1290 | |
f36a1a13 PM |
1291 | if (!ppmu) |
1292 | return; | |
01d0287f PM |
1293 | memset(cpuhw, 0, sizeof(*cpuhw)); |
1294 | cpuhw->mmcr[0] = MMCR0_FC; | |
1295 | } | |
1296 | ||
079b3c56 | 1297 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 1298 | { |
079b3c56 PM |
1299 | if (ppmu) |
1300 | return -EBUSY; /* something's already registered */ | |
1301 | ||
1302 | ppmu = pmu; | |
1303 | pr_info("%s performance monitor hardware support registered\n", | |
1304 | pmu->name); | |
d095cd46 | 1305 | |
98fb1807 | 1306 | #ifdef MSR_HV |
d095cd46 PM |
1307 | /* |
1308 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
1309 | */ | |
1310 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 1311 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 1312 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 1313 | |
4574910e PM |
1314 | return 0; |
1315 | } |