Commit | Line | Data |
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1da177e4 | 1 | /* |
f7f6f4fe | 2 | * arch/powerpc/kernel/pmc.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2004 David Gibson, IBM Corporation. | |
f7f6f4fe DG |
5 | * Includes code formerly from arch/ppc/kernel/perfmon.c: |
6 | * Author: Andy Fleming | |
7 | * Copyright (c) 2004 Freescale Semiconductor, Inc | |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/spinlock.h> | |
17 | #include <linux/module.h> | |
18 | ||
19 | #include <asm/processor.h> | |
6529c13d | 20 | #include <asm/cputable.h> |
1da177e4 LT |
21 | #include <asm/pmc.h> |
22 | ||
177e9ea4 AB |
23 | #ifndef MMCR0_PMAO |
24 | #define MMCR0_PMAO 0 | |
f7f6f4fe DG |
25 | #endif |
26 | ||
1da177e4 LT |
27 | static void dummy_perf(struct pt_regs *regs) |
28 | { | |
39aef685 | 29 | #if defined(CONFIG_FSL_EMB_PERFMON) |
1bd2e5ae OJ |
30 | mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE); |
31 | #elif defined(CONFIG_PPC64) || defined(CONFIG_6xx) | |
6529c13d | 32 | if (cur_cpu_spec->pmc_type == PPC_PMC_IBM) |
177e9ea4 | 33 | mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO)); |
f7f6f4fe | 34 | #else |
1bd2e5ae | 35 | mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE); |
f7f6f4fe | 36 | #endif |
1bd2e5ae OJ |
37 | } |
38 | ||
1da177e4 | 39 | |
a9f6a0dd | 40 | static DEFINE_SPINLOCK(pmc_owner_lock); |
1da177e4 LT |
41 | static void *pmc_owner_caller; /* mostly for debugging */ |
42 | perf_irq_t perf_irq = dummy_perf; | |
43 | ||
44 | int reserve_pmc_hardware(perf_irq_t new_perf_irq) | |
45 | { | |
46 | int err = 0; | |
47 | ||
48 | spin_lock(&pmc_owner_lock); | |
49 | ||
50 | if (pmc_owner_caller) { | |
51 | printk(KERN_WARNING "reserve_pmc_hardware: " | |
52 | "PMC hardware busy (reserved by caller %p)\n", | |
53 | pmc_owner_caller); | |
54 | err = -EBUSY; | |
55 | goto out; | |
56 | } | |
57 | ||
58 | pmc_owner_caller = __builtin_return_address(0); | |
dd6c89f6 | 59 | perf_irq = new_perf_irq ? new_perf_irq : dummy_perf; |
1da177e4 LT |
60 | |
61 | out: | |
62 | spin_unlock(&pmc_owner_lock); | |
63 | return err; | |
64 | } | |
65 | EXPORT_SYMBOL_GPL(reserve_pmc_hardware); | |
66 | ||
67 | void release_pmc_hardware(void) | |
68 | { | |
69 | spin_lock(&pmc_owner_lock); | |
70 | ||
71 | WARN_ON(! pmc_owner_caller); | |
72 | ||
73 | pmc_owner_caller = NULL; | |
74 | perf_irq = dummy_perf; | |
75 | ||
76 | spin_unlock(&pmc_owner_lock); | |
77 | } | |
78 | EXPORT_SYMBOL_GPL(release_pmc_hardware); | |
180a3362 | 79 | |
f7f6f4fe | 80 | #ifdef CONFIG_PPC64 |
180a3362 ME |
81 | void power4_enable_pmcs(void) |
82 | { | |
83 | unsigned long hid0; | |
84 | ||
b5bbeb23 | 85 | hid0 = mfspr(SPRN_HID0); |
180a3362 ME |
86 | hid0 |= 1UL << (63 - 20); |
87 | ||
88 | /* POWER4 requires the following sequence */ | |
89 | asm volatile( | |
90 | "sync\n" | |
91 | "mtspr %1, %0\n" | |
92 | "mfspr %0, %1\n" | |
93 | "mfspr %0, %1\n" | |
94 | "mfspr %0, %1\n" | |
95 | "mfspr %0, %1\n" | |
96 | "mfspr %0, %1\n" | |
97 | "mfspr %0, %1\n" | |
b5bbeb23 | 98 | "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0): |
180a3362 ME |
99 | "memory"); |
100 | } | |
f7f6f4fe | 101 | #endif /* CONFIG_PPC64 */ |