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perf_counter: powerpc: set sample enable bit for marked instruction events
[deliverable/linux.git] / arch / powerpc / kernel / power5+-pmu.c
CommitLineData
aabbaa60 1/*
f708223d 2 * Performance counter support for POWER5+/++ (not POWER5) processors.
aabbaa60
PM		 3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#include <linux/kernel.h>
12#include <linux/perf_counter.h>
13#include <asm/reg.h>
14
15/*
16 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
17 */
18#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
19#define PM_PMC_MSK 0xf
20#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21#define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
22#define PM_UNIT_MSK 0xf
23#define PM_BYTE_SH 12 /* Byte number of event bus to use */
24#define PM_BYTE_MSK 7
25#define PM_GRS_SH 8 /* Storage subsystem mux select */
26#define PM_GRS_MSK 7
27#define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
28#define PM_PMCSEL_MSK 0x7f
29
30/* Values in PM_UNIT field */
31#define PM_FPU 0
32#define PM_ISU0 1
33#define PM_IFU 2
34#define PM_ISU1 3
35#define PM_IDU 4
36#define PM_ISU0_ALT 6
37#define PM_GRS 7
38#define PM_LSU0 8
39#define PM_LSU1 0xc
40#define PM_LASTUNIT 0xc
41
42/*
43 * Bits in MMCR1 for POWER5+
44 */
45#define MMCR1_TTM0SEL_SH 62
46#define MMCR1_TTM1SEL_SH 60
47#define MMCR1_TTM2SEL_SH 58
48#define MMCR1_TTM3SEL_SH 56
49#define MMCR1_TTMSEL_MSK 3
50#define MMCR1_TD_CP_DBG0SEL_SH 54
51#define MMCR1_TD_CP_DBG1SEL_SH 52
52#define MMCR1_TD_CP_DBG2SEL_SH 50
53#define MMCR1_TD_CP_DBG3SEL_SH 48
54#define MMCR1_GRS_L2SEL_SH 46
55#define MMCR1_GRS_L2SEL_MSK 3
56#define MMCR1_GRS_L3SEL_SH 44
57#define MMCR1_GRS_L3SEL_MSK 3
58#define MMCR1_GRS_MCSEL_SH 41
59#define MMCR1_GRS_MCSEL_MSK 7
60#define MMCR1_GRS_FABSEL_SH 39
61#define MMCR1_GRS_FABSEL_MSK 3
62#define MMCR1_PMC1_ADDER_SEL_SH 35
63#define MMCR1_PMC2_ADDER_SEL_SH 34
64#define MMCR1_PMC3_ADDER_SEL_SH 33
65#define MMCR1_PMC4_ADDER_SEL_SH 32
66#define MMCR1_PMC1SEL_SH 25
67#define MMCR1_PMC2SEL_SH 17
68#define MMCR1_PMC3SEL_SH 9
69#define MMCR1_PMC4SEL_SH 1
70#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
71#define MMCR1_PMCSEL_MSK 0x7f
72
73/*
74 * Bits in MMCRA
75 */
76
77/*
78 * Layout of constraint bits:
79 * 6666555555555544444444443333333333222222222211111111110000000000
80 * 3210987654321098765432109876543210987654321098765432109876543210
81 * [ ><><>< ><> <><>[ > < >< >< >< ><><><><>
82 * NC G0G1G2 G3 T0T1 UC B0 B1 B2 B3 P4P3P2P1
83 *
84 * NC - number of counters
85 * 51: NC error 0x0008_0000_0000_0000
86 * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
87 *
88 * G0..G3 - GRS mux constraints
89 * 46-47: GRS_L2SEL value
90 * 44-45: GRS_L3SEL value
91 * 41-44: GRS_MCSEL value
92 * 39-40: GRS_FABSEL value
93 * Note that these match up with their bit positions in MMCR1
94 *
95 * T0 - TTM0 constraint
96 * 36-37: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0x30_0000_0000
97 *
98 * T1 - TTM1 constraint
99 * 34-35: TTM1SEL value (0=IDU, 3=GRS) 0x0c_0000_0000
100 *
101 * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
102 * 33: UC3 error 0x02_0000_0000
103 * 32: FPU|IFU|ISU1 events needed 0x01_0000_0000
104 * 31: ISU0 events needed 0x01_8000_0000
105 * 30: IDU|GRS events needed 0x00_4000_0000
106 *
107 * B0
108 * 20-23: Byte 0 event source 0x00f0_0000
109 * Encoding as for the event code
110 *
111 * B1, B2, B3
112 * 16-19, 12-15, 8-11: Byte 1, 2, 3 event sources
113 *
114 * P4
115 * 7: P1 error 0x80
116 * 6-7: Count of events needing PMC4
117 *
118 * P1..P3
119 * 0-6: Count of events needing PMC1..PMC3
120 */
121
122static const int grsel_shift[8] = {
123 MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
124 MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
125 MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
126};
127
128/* Masks and values for using events from the various units */
129static u64 unit_cons[PM_LASTUNIT+1][2] = {
130 [PM_FPU] = { 0x3200000000ull, 0x0100000000ull },
131 [PM_ISU0] = { 0x0200000000ull, 0x0080000000ull },
132 [PM_ISU1] = { 0x3200000000ull, 0x3100000000ull },
133 [PM_IFU] = { 0x3200000000ull, 0x2100000000ull },
134 [PM_IDU] = { 0x0e00000000ull, 0x0040000000ull },
135 [PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull },
136};
137
138static int power5p_get_constraint(unsigned int event, u64 *maskp, u64 *valp)
139{
140 int pmc, byte, unit, sh;
141 int bit, fmask;
142 u64 mask = 0, value = 0;
143
144 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
145 if (pmc) {
146 if (pmc > 4)
147 return -1;
148 sh = (pmc - 1) * 2;
149 mask |= 2 << sh;
150 value |= 1 << sh;
151 }
152 if (event & PM_BUSEVENT_MSK) {
153 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
154 if (unit > PM_LASTUNIT)
155 return -1;
156 if (unit == PM_ISU0_ALT)
157 unit = PM_ISU0;
158 mask |= unit_cons[unit][0];
159 value |= unit_cons[unit][1];
160 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
161 if (byte >= 4) {
162 if (unit != PM_LSU1)
163 return -1;
164 /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
165 ++unit;
166 byte &= 3;
167 }
168 if (unit == PM_GRS) {
169 bit = event & 7;
170 fmask = (bit == 6)? 7: 3;
171 sh = grsel_shift[bit];
172 mask |= (u64)fmask << sh;
173 value |= (u64)((event >> PM_GRS_SH) & fmask) << sh;
174 }
175 /* Set byte lane select field */
176 mask |= 0xfULL << (20 - 4 * byte);
177 value |= (u64)unit << (20 - 4 * byte);
178 }
179 mask |= 0x8000000000000ull;
180 value |= 0x1000000000000ull;
181 *maskp = mask;
182 *valp = value;
183 return 0;
184}
185
186#define MAX_ALT 3 /* at most 3 alternatives for any event */
187
188static const unsigned int event_alternatives[][MAX_ALT] = {
189 { 0x100c0, 0x40001f }, /* PM_GCT_FULL_CYC */
190 { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
191 { 0x230e2, 0x323087 }, /* PM_BR_PRED_CR */
192 { 0x230e3, 0x223087, 0x3230a0 }, /* PM_BR_PRED_TA */
193 { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
194 { 0x800c4, 0xc20e0 }, /* PM_DTLB_MISS */
195 { 0xc50c6, 0xc60e0 }, /* PM_MRK_DTLB_MISS */
196 { 0x100009, 0x200009 }, /* PM_INST_CMPL */
197 { 0x200015, 0x300015 }, /* PM_LSU_LMQ_SRQ_EMPTY_CYC */
198 { 0x300009, 0x400009 }, /* PM_INST_DISP */
199};
200
201/*
202 * Scan the alternatives table for a match and return the
203 * index into the alternatives table if found, else -1.
204 */
205static int find_alternative(unsigned int event)
206{
207 int i, j;
208
209 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
210 if (event < event_alternatives[i][0])
211 break;
212 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
213 if (event == event_alternatives[i][j])
214 return i;
215 }
216 return -1;
217}
218
219static const unsigned char bytedecode_alternatives[4][4] = {
220 /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
221 /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
222 /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
223 /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
224};
225
226/*
227 * Some direct events for decodes of event bus byte 3 have alternative
228 * PMCSEL values on other counters. This returns the alternative
229 * event code for those that do, or -1 otherwise. This also handles
230 * alternative PCMSEL values for add events.
231 */
232static int find_alternative_bdecode(unsigned int event)
233{
234 int pmc, altpmc, pp, j;
235
236 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
237 if (pmc == 0 || pmc > 4)
238 return -1;
239 altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
240 pp = event & PM_PMCSEL_MSK;
241 for (j = 0; j < 4; ++j) {
242 if (bytedecode_alternatives[pmc - 1][j] == pp) {
243 return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
244 (altpmc << PM_PMC_SH) |
245 bytedecode_alternatives[altpmc - 1][j];
246 }
247 }
248
249 /* new decode alternatives for power5+ */
250 if (pmc == 1 && (pp == 0x0d || pp == 0x0e))
251 return event + (2 << PM_PMC_SH) + (0x2e - 0x0d);
252 if (pmc == 3 && (pp == 0x2e || pp == 0x2f))
253 return event - (2 << PM_PMC_SH) - (0x2e - 0x0d);
254
255 /* alternative add event encodings */
256 if (pp == 0x10 || pp == 0x28)
257 return ((event ^ (0x10 ^ 0x28)) & ~PM_PMC_MSKS) |
258 (altpmc << PM_PMC_SH);
259
260 return -1;
261}
262
263static int power5p_get_alternatives(unsigned int event, unsigned int alt[])
264{
265 int i, j, ae, nalt = 1;
266
267 alt[0] = event;
268 nalt = 1;
269 i = find_alternative(event);
270 if (i >= 0) {
271 for (j = 0; j < MAX_ALT; ++j) {
272 ae = event_alternatives[i][j];
273 if (ae && ae != event)
274 alt[nalt++] = ae;
275 }
276 } else {
277 ae = find_alternative_bdecode(event);
278 if (ae > 0)
279 alt[nalt++] = ae;
280 }
281 return nalt;
282}
283
f708223d
PM		 284/*
285 * Map of which direct events on which PMCs are marked instruction events.
286 * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
287 * Bit 0 is set if it is marked for all PMCs.
288 * The 0x80 bit indicates a byte decode PMCSEL value.
289 */
290static unsigned char direct_event_is_marked[0x28] = {
291 0, /* 00 */
292 0x1f, /* 01 PM_IOPS_CMPL */
293 0x2, /* 02 PM_MRK_GRP_DISP */
294 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
295 0, /* 04 */
296 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
297 0x80, /* 06 */
298 0x80, /* 07 */
299 0, 0, 0,/* 08 - 0a */
300 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
301 0, /* 0c */
302 0x80, /* 0d */
303 0x80, /* 0e */
304 0, /* 0f */
305 0, /* 10 */
306 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
307 0, /* 12 */
308 0x10, /* 13 PM_MRK_GRP_CMPL */
309 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
310 0x2, /* 15 PM_MRK_GRP_ISSUED */
311 0x80, /* 16 */
312 0x80, /* 17 */
313 0, 0, 0, 0, 0,
314 0x80, /* 1d */
315 0x80, /* 1e */
316 0, /* 1f */
317 0x80, /* 20 */
318 0x80, /* 21 */
319 0x80, /* 22 */
320 0x80, /* 23 */
321 0x80, /* 24 */
322 0x80, /* 25 */
323 0x80, /* 26 */
324 0x80, /* 27 */
325};
326
327/*
328 * Returns 1 if event counts things relating to marked instructions
329 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
330 */
331static int power5p_marked_instr_event(unsigned int event)
332{
333 int pmc, psel;
334 int bit, byte, unit;
335 u32 mask;
336
337 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
338 psel = event & PM_PMCSEL_MSK;
339 if (pmc >= 5)
340 return 0;
341
342 bit = -1;
343 if (psel < sizeof(direct_event_is_marked)) {
344 if (direct_event_is_marked[psel] & (1 << pmc))
345 return 1;
346 if (direct_event_is_marked[psel] & 0x80)
347 bit = 4;
348 else if (psel == 0x08)
349 bit = pmc - 1;
350 else if (psel == 0x10)
351 bit = 4 - pmc;
352 else if (psel == 0x1b && (pmc == 1 || pmc == 3))
353 bit = 4;
354 } else if ((psel & 0x48) == 0x40) {
355 bit = psel & 7;
356 } else if (psel == 0x28) {
357 bit = pmc - 1;
358 } else if (pmc == 3 && (psel == 0x2e || psel == 0x2f)) {
359 bit = 4;
360 }
361
362 if (!(event & PM_BUSEVENT_MSK) || bit == -1)
363 return 0;
364
365 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
366 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
367 if (unit == PM_LSU0) {
368 /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
369 mask = 0x5dff00;
370 } else if (unit == PM_LSU1 && byte >= 4) {
371 byte -= 4;
372 /* byte 5 bits 6-7, byte 6 bits 0,4, byte 7 bits 0-4,6 */
373 mask = 0x5f11c000;
374 } else
375 return 0;
376
377 return (mask >> (byte * 8 + bit)) & 1;
378}
379
aabbaa60
PM		 380static int power5p_compute_mmcr(unsigned int event[], int n_ev,
381 unsigned int hwc[], u64 mmcr[])
382{
383 u64 mmcr1 = 0;
f708223d 384 u64 mmcra = 0;
aabbaa60
PM		 385 unsigned int pmc, unit, byte, psel;
386 unsigned int ttm;
387 int i, isbus, bit, grsel;
388 unsigned int pmc_inuse = 0;
389 unsigned char busbyte[4];
390 unsigned char unituse[16];
391 int ttmuse;
392
393 if (n_ev > 4)
394 return -1;
395
396 /* First pass to count resource use */
397 memset(busbyte, 0, sizeof(busbyte));
398 memset(unituse, 0, sizeof(unituse));
399 for (i = 0; i < n_ev; ++i) {
400 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
401 if (pmc) {
402 if (pmc > 4)
403 return -1;
404 if (pmc_inuse & (1 << (pmc - 1)))
405 return -1;
406 pmc_inuse |= 1 << (pmc - 1);
407 }
408 if (event[i] & PM_BUSEVENT_MSK) {
409 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
410 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
411 if (unit > PM_LASTUNIT)
412 return -1;
413 if (unit == PM_ISU0_ALT)
414 unit = PM_ISU0;
415 if (byte >= 4) {
416 if (unit != PM_LSU1)
417 return -1;
418 ++unit;
419 byte &= 3;
420 }
421 if (busbyte[byte] && busbyte[byte] != unit)
422 return -1;
423 busbyte[byte] = unit;
424 unituse[unit] = 1;
425 }
426 }
427
428 /*
429 * Assign resources and set multiplexer selects.
430 *
431 * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
432 * choice we have to deal with.
433 */
434 if (unituse[PM_ISU0] &
435 (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
436 unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
437 unituse[PM_ISU0] = 0;
438 }
439 /* Set TTM[01]SEL fields. */
440 ttmuse = 0;
441 for (i = PM_FPU; i <= PM_ISU1; ++i) {
442 if (!unituse[i])
443 continue;
444 if (ttmuse++)
445 return -1;
446 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH;
447 }
448 ttmuse = 0;
449 for (; i <= PM_GRS; ++i) {
450 if (!unituse[i])
451 continue;
452 if (ttmuse++)
453 return -1;
454 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH;
455 }
456 if (ttmuse > 1)
457 return -1;
458
459 /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
460 for (byte = 0; byte < 4; ++byte) {
461 unit = busbyte[byte];
462 if (!unit)
463 continue;
464 if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
465 /* get ISU0 through TTM1 rather than TTM0 */
466 unit = PM_ISU0_ALT;
467 } else if (unit == PM_LSU1 + 1) {
468 /* select lower word of LSU1 for this byte */
469 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
470 }
471 ttm = unit >> 2;
472 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
473 }
474
475 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
476 for (i = 0; i < n_ev; ++i) {
477 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
478 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
479 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
480 psel = event[i] & PM_PMCSEL_MSK;
481 isbus = event[i] & PM_BUSEVENT_MSK;
482 if (!pmc) {
483 /* Bus event or any-PMC direct event */
484 for (pmc = 0; pmc < 4; ++pmc) {
485 if (!(pmc_inuse & (1 << pmc)))
486 break;
487 }
488 if (pmc >= 4)
489 return -1;
490 pmc_inuse |= 1 << pmc;
491 } else {
492 /* Direct event */
493 --pmc;
494 if (isbus && (byte & 2) &&
495 (psel == 8 || psel == 0x10 || psel == 0x28))
496 /* add events on higher-numbered bus */
497 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
498 }
499 if (isbus && unit == PM_GRS) {
500 bit = psel & 7;
501 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
502 mmcr1 |= (u64)grsel << grsel_shift[bit];
503 }
f708223d
PM		 504 if (power5p_marked_instr_event(event[i]))
505 mmcra |= MMCRA_SAMPLE_ENABLE;
aabbaa60
PM		 506 if ((psel & 0x58) == 0x40 && (byte & 1) != ((pmc >> 1) & 1))
507 /* select alternate byte lane */
508 psel |= 0x10;
509 if (pmc <= 3)
510 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
511 hwc[i] = pmc;
512 }
513
514 /* Return MMCRx values */
515 mmcr[0] = 0;
516 if (pmc_inuse & 1)
517 mmcr[0] = MMCR0_PMC1CE;
518 if (pmc_inuse & 0x3e)
519 mmcr[0] |= MMCR0_PMCjCE;
520 mmcr[1] = mmcr1;
f708223d 521 mmcr[2] = mmcra;
aabbaa60
PM		 522 return 0;
523}
524
525static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[])
526{
527 if (pmc <= 3)
528 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
529}
530
531static int power5p_generic_events[] = {
532 [PERF_COUNT_CPU_CYCLES] = 0xf,
533 [PERF_COUNT_INSTRUCTIONS] = 0x100009,
534 [PERF_COUNT_CACHE_REFERENCES] = 0x1c10a8, /* LD_REF_L1 */
535 [PERF_COUNT_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
536 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
537 [PERF_COUNT_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
538};
539
540struct power_pmu power5p_pmu = {
541 .n_counter = 4,
542 .max_alternatives = MAX_ALT,
543 .add_fields = 0x7000000000055ull,
544 .test_adder = 0x3000040000000ull,
545 .compute_mmcr = power5p_compute_mmcr,
546 .get_constraint = power5p_get_constraint,
547 .get_alternatives = power5p_get_alternatives,
548 .disable_pmc = power5p_disable_pmc,
549 .n_generic = ARRAY_SIZE(power5p_generic_events),
550 .generic_events = power5p_generic_events,
551};
Linux kernel - Deliverables
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