projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f7862837 PM |
1 | /* |
| 2 | * Performance counter support for POWER6 processors. | |
| 3 | * | |
| 4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License | |
| 8 | * as published by the Free Software Foundation; either version | |
| 9 | * 2 of the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | #include <linux/kernel.h> | |
| 12 | #include <linux/perf_counter.h> | |
| 13 | #include <asm/reg.h> | |
| 14 | ||
| 15 | /* | |
| 16 | * Bits in event code for POWER6 | |
| 17 | */ | |
| 18 | #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */ | |
| 19 | #define PM_PMC_MSK 0x7 | |
| 20 | #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) | |
| 21 | #define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */ | |
| 22 | #define PM_UNIT_MSK 0xf | |
| 23 | #define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH) | |
| 24 | #define PM_LLAV 0x8000 /* Load lookahead match value */ | |
| 25 | #define PM_LLA 0x4000 /* Load lookahead match enable */ | |
| 26 | #define PM_BYTE_SH 12 /* Byte of event bus to use */ | |
| 27 | #define PM_BYTE_MSK 3 | |
| 28 | #define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */ | |
| 29 | #define PM_SUBUNIT_MSK 7 | |
| 30 | #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH) | |
| 31 | #define PM_PMCSEL_MSK 0xff /* PMCxSEL value */ | |
| 32 | #define PM_BUSEVENT_MSK 0xf3700 | |
| 33 | ||
| 34 | /* | |
| 35 | * Bits in MMCR1 for POWER6 | |
| 36 | */ | |
| 37 | #define MMCR1_TTM0SEL_SH 60 | |
| 38 | #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4) | |
| 39 | #define MMCR1_TTMSEL_MSK 0xf | |
| 40 | #define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK) | |
| 41 | #define MMCR1_NESTSEL_SH 45 | |
| 42 | #define MMCR1_NESTSEL_MSK 0x7 | |
| 43 | #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) | |
| 44 | #define MMCR1_PMC1_LLA ((u64)1 << 44) | |
| 45 | #define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39) | |
| 46 | #define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35) | |
| 47 | #define MMCR1_PMC1SEL_SH 24 | |
| 48 | #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) | |
| 49 | #define MMCR1_PMCSEL_MSK 0xff | |
| 50 | ||
| 51 | /* | |
| 52 | * Assign PMC numbers and compute MMCR1 value for a set of events | |
| 53 | */ | |
| 54 | static int p6_compute_mmcr(unsigned int event[], int n_ev, | |
| 55 | unsigned int hwc[], u64 mmcr[]) | |
| 56 | { | |
| 57 | u64 mmcr1 = 0; | |
| 58 | int i; | |
| 59 | unsigned int pmc, ev, b, u, s, psel; | |
| 60 | unsigned int ttmset = 0; | |
| 61 | unsigned int pmc_inuse = 0; | |
| 62 | ||
| 63 | if (n_ev > 4) | |
| 64 | return -1; | |
| 65 | for (i = 0; i < n_ev; ++i) { | |
| 66 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
| 67 | if (pmc) { | |
| 68 | if (pmc_inuse & (1 << (pmc - 1))) | |
| 69 | return -1; /* collision! */ | |
| 70 | pmc_inuse |= 1 << (pmc - 1); | |
| 71 | } | |
| 72 | } | |
| 73 | for (i = 0; i < n_ev; ++i) { | |
| 74 | ev = event[i]; | |
| 75 | pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK; | |
| 76 | if (pmc) { | |
| 77 | --pmc; | |
| 78 | } else { | |
| 79 | /* can go on any PMC; find a free one */ | |
| 80 | for (pmc = 0; pmc < 4; ++pmc) | |
| 81 | if (!(pmc_inuse & (1 << pmc))) | |
| 82 | break; | |
| 83 | pmc_inuse |= 1 << pmc; | |
| 84 | } | |
| 85 | hwc[i] = pmc; | |
| 86 | psel = ev & PM_PMCSEL_MSK; | |
| 87 | if (ev & PM_BUSEVENT_MSK) { | |
| 88 | /* this event uses the event bus */ | |
| 89 | b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK; | |
| 90 | u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK; | |
| 91 | /* check for conflict on this byte of event bus */ | |
| 92 | if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) | |
| 93 | return -1; | |
| 94 | mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b); | |
| 95 | ttmset |= 1 << b; | |
| 96 | if (u == 5) { | |
| 97 | /* Nest events have a further mux */ | |
| 98 | s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; | |
| 99 | if ((ttmset & 0x10) && | |
| 100 | MMCR1_NESTSEL(mmcr1) != s) | |
| 101 | return -1; | |
| 102 | ttmset |= 0x10; | |
| 103 | mmcr1 |= (u64)s << MMCR1_NESTSEL_SH; | |
| 104 | } | |
| 105 | if (0x30 <= psel && psel <= 0x3d) { | |
| 106 | /* these need the PMCx_ADDR_SEL bits */ | |
| 107 | if (b >= 2) | |
| 108 | mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc; | |
| 109 | } | |
| 110 | /* bus select values are different for PMC3/4 */ | |
| 111 | if (pmc >= 2 && (psel & 0x90) == 0x80) | |
| 112 | psel ^= 0x20; | |
| 113 | } | |
| 114 | if (ev & PM_LLA) { | |
| 115 | mmcr1 |= MMCR1_PMC1_LLA >> pmc; | |
| 116 | if (ev & PM_LLAV) | |
| 117 | mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc; | |
| 118 | } | |
| 119 | mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc); | |
| 120 | } | |
| 121 | mmcr[0] = 0; | |
| 122 | if (pmc_inuse & 1) | |
| 123 | mmcr[0] = MMCR0_PMC1CE; | |
| 124 | if (pmc_inuse & 0xe) | |
| 125 | mmcr[0] |= MMCR0_PMCjCE; | |
| 126 | mmcr[1] = mmcr1; | |
| 127 | mmcr[2] = 0; | |
| 128 | return 0; | |
| 129 | } | |
| 130 | ||
| 131 | /* | |
| 132 | * Layout of constraint bits: | |
| 133 | * | |
| 134 | * 0-1 add field: number of uses of PMC1 (max 1) | |
| 135 | * 2-3, 4-5, 6-7: ditto for PMC2, 3, 4 | |
| 136 | * 8-10 select field: nest (subunit) event selector | |
| 137 | * 16-19 select field: unit on byte 0 of event bus | |
| 138 | * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 | |
| 139 | */ | |
| 140 | static int p6_get_constraint(unsigned int event, u64 *maskp, u64 *valp) | |
| 141 | { | |
| 142 | int pmc, byte, sh; | |
| 143 | unsigned int mask = 0, value = 0; | |
| 144 | ||
| 145 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
| 146 | if (pmc) { | |
| 147 | if (pmc > 4) | |
| 148 | return -1; | |
| 149 | sh = (pmc - 1) * 2; | |
| 150 | mask |= 2 << sh; | |
| 151 | value |= 1 << sh; | |
| 152 | } | |
| 153 | if (event & PM_BUSEVENT_MSK) { | |
| 154 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | |
| 155 | sh = byte * 4; | |
| 156 | mask |= PM_UNIT_MSKS << sh; | |
| 157 | value |= (event & PM_UNIT_MSKS) << sh; | |
| 158 | if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { | |
| 159 | mask |= PM_SUBUNIT_MSKS; | |
| 160 | value |= event & PM_SUBUNIT_MSKS; | |
| 161 | } | |
| 162 | } | |
| 163 | *maskp = mask; | |
| 164 | *valp = value; | |
| 165 | return 0; | |
| 166 | } | |
| 167 | ||
| 168 | #define MAX_ALT 4 /* at most 4 alternatives for any event */ | |
| 169 | ||
| 170 | static const unsigned int event_alternatives[][MAX_ALT] = { | |
| 171 | { 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */ | |
| 172 | { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */ | |
| 173 | { 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */ | |
| 174 | { 0x10000a, 0x2000f4 }, /* PM_RUN_CYC */ | |
| 175 | { 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */ | |
| 176 | { 0x10000e, 0x400010 }, /* PM_PURR */ | |
| 177 | { 0x100010, 0x4000f8 }, /* PM_FLUSH */ | |
| 178 | { 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */ | |
| 179 | { 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */ | |
| 180 | { 0x100054, 0x2000f0 }, /* PM_ST_FIN */ | |
| 181 | { 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */ | |
| 182 | { 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */ | |
| 183 | { 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */ | |
| 184 | { 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */ | |
| 185 | { 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */ | |
| 186 | { 0x200012, 0x300012 }, /* PM_INST_DISP */ | |
| 187 | { 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */ | |
| 188 | { 0x2000f8, 0x300010 }, /* PM_EXT_INT */ | |
| 189 | { 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */ | |
| 190 | { 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */ | |
| 191 | { 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */ | |
| 192 | { 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */ | |
| 193 | { 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */ | |
| 194 | }; | |
| 195 | ||
| 196 | /* | |
| 197 | * This could be made more efficient with a binary search on | |
| 198 | * a presorted list, if necessary | |
| 199 | */ | |
| 200 | static int find_alternatives_list(unsigned int event) | |
| 201 | { | |
| 202 | int i, j; | |
| 203 | unsigned int alt; | |
| 204 | ||
| 205 | for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { | |
| 206 | if (event < event_alternatives[i][0]) | |
| 207 | return -1; | |
| 208 | for (j = 0; j < MAX_ALT; ++j) { | |
| 209 | alt = event_alternatives[i][j]; | |
| 210 | if (!alt || event < alt) | |
| 211 | break; | |
| 212 | if (event == alt) | |
| 213 | return i; | |
| 214 | } | |
| 215 | } | |
| 216 | return -1; | |
| 217 | } | |
| 218 | ||
| 219 | static int p6_get_alternatives(unsigned int event, unsigned int alt[]) | |
| 220 | { | |
| 221 | int i, j; | |
| 222 | unsigned int aevent, psel, pmc; | |
| 223 | unsigned int nalt = 1; | |
| 224 | ||
| 225 | alt[0] = event; | |
| 226 | ||
| 227 | /* check the alternatives table */ | |
| 228 | i = find_alternatives_list(event); | |
| 229 | if (i >= 0) { | |
| 230 | /* copy out alternatives from list */ | |
| 231 | for (j = 0; j < MAX_ALT; ++j) { | |
| 232 | aevent = event_alternatives[i][j]; | |
| 233 | if (!aevent) | |
| 234 | break; | |
| 235 | if (aevent != event) | |
| 236 | alt[nalt++] = aevent; | |
| 237 | } | |
| 238 | ||
| 239 | } else { | |
| 240 | /* Check for alternative ways of computing sum events */ | |
| 241 | /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */ | |
| 242 | psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */ | |
| 243 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
| 244 | if (pmc && (psel == 0x32 || psel == 0x34)) | |
| 245 | alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) | | |
| 246 | ((5 - pmc) << PM_PMC_SH); | |
| 247 | ||
| 248 | /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */ | |
| 249 | if (pmc && (psel == 0x38 || psel == 0x3a)) | |
| 250 | alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) | | |
| 251 | ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH); | |
| 252 | } | |
| 253 | ||
| 254 | return nalt; | |
| 255 | } | |
| 256 | ||
| 257 | static void p6_disable_pmc(unsigned int pmc, u64 mmcr[]) | |
| 258 | { | |
| 259 | /* Set PMCxSEL to 0 to disable PMCx */ | |
| 260 | mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); | |
| 261 | } | |
| 262 | ||
| 263 | static int power6_generic_events[] = { | |
| 264 | [PERF_COUNT_CPU_CYCLES] = 0x1e, | |
| 265 | [PERF_COUNT_INSTRUCTIONS] = 2, | |
| 266 | [PERF_COUNT_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */ | |
| 267 | [PERF_COUNT_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */ | |
| 268 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */ | |
| 269 | [PERF_COUNT_BRANCH_MISSES] = 0x400052, /* BR_MPRED */ | |
| 270 | }; | |
| 271 | ||
| 272 | struct power_pmu power6_pmu = { | |
| 273 | .n_counter = 4, | |
| 274 | .max_alternatives = MAX_ALT, | |
| 275 | .add_fields = 0x55, | |
| 276 | .test_adder = 0, | |
| 277 | .compute_mmcr = p6_compute_mmcr, | |
| 278 | .get_constraint = p6_get_constraint, | |
| 279 | .get_alternatives = p6_get_alternatives, | |
| 280 | .disable_pmc = p6_disable_pmc, | |
| 281 | .n_generic = ARRAY_SIZE(power6_generic_events), | |
| 282 | .generic_events = power6_generic_events, | |
| 283 | }; |