Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
3caf06c6 | 25 | #include <linux/elf.h> |
1da177e4 LT |
26 | #include <linux/user.h> |
27 | #include <linux/security.h> | |
7ed20e1a | 28 | #include <linux/signal.h> |
ea9c102c DW |
29 | #include <linux/seccomp.h> |
30 | #include <linux/audit.h> | |
e8a30302 | 31 | #ifdef CONFIG_PPC32 |
ea9c102c | 32 | #include <linux/module.h> |
e8a30302 | 33 | #endif |
1da177e4 LT |
34 | |
35 | #include <asm/uaccess.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/system.h> | |
21a62902 | 39 | |
abd06505 BH |
40 | /* |
41 | * does not yet catch signals sent when the child dies. | |
42 | * in exit.c or in signal.c. | |
43 | */ | |
44 | ||
45 | /* | |
46 | * Set of msr bits that gdb can change on behalf of a process. | |
47 | */ | |
48 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
49 | #define MSR_DEBUGCHANGE 0 | |
1da177e4 | 50 | #else |
abd06505 | 51 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 52 | #endif |
acd89828 | 53 | |
1da177e4 | 54 | /* |
abd06505 | 55 | * Max register writeable via put_reg |
1da177e4 | 56 | */ |
abd06505 BH |
57 | #ifdef CONFIG_PPC32 |
58 | #define PT_MAX_PUT_REG PT_MQ | |
59 | #else | |
60 | #define PT_MAX_PUT_REG PT_CCR | |
61 | #endif | |
1da177e4 | 62 | |
26f77130 RM |
63 | static unsigned long get_user_msr(struct task_struct *task) |
64 | { | |
65 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
66 | } | |
67 | ||
68 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
69 | { | |
70 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
71 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
72 | return 0; | |
73 | } | |
74 | ||
75 | /* | |
76 | * We prevent mucking around with the reserved area of trap | |
77 | * which are used internally by the kernel. | |
78 | */ | |
79 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
80 | { | |
81 | task->thread.regs->trap = trap & 0xfff0; | |
82 | return 0; | |
83 | } | |
84 | ||
865418d8 BH |
85 | /* |
86 | * Get contents of register REGNO in task TASK. | |
87 | */ | |
88 | unsigned long ptrace_get_reg(struct task_struct *task, int regno) | |
89 | { | |
865418d8 BH |
90 | if (task->thread.regs == NULL) |
91 | return -EIO; | |
92 | ||
26f77130 RM |
93 | if (regno == PT_MSR) |
94 | return get_user_msr(task); | |
865418d8 BH |
95 | |
96 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) | |
97 | return ((unsigned long *)task->thread.regs)[regno]; | |
98 | ||
99 | return -EIO; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Write contents of register REGNO in task TASK. | |
104 | */ | |
105 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
106 | { | |
107 | if (task->thread.regs == NULL) | |
108 | return -EIO; | |
109 | ||
26f77130 RM |
110 | if (regno == PT_MSR) |
111 | return set_user_msr(task, data); | |
112 | if (regno == PT_TRAP) | |
113 | return set_user_trap(task, data); | |
114 | ||
115 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
116 | ((unsigned long *)task->thread.regs)[regno] = data; |
117 | return 0; | |
118 | } | |
119 | return -EIO; | |
120 | } | |
121 | ||
122 | ||
f65255e8 RM |
123 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
124 | unsigned int pos, unsigned int count, | |
125 | void *kbuf, void __user *ubuf) | |
126 | { | |
127 | flush_fp_to_thread(target); | |
128 | ||
129 | BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != | |
130 | offsetof(struct thread_struct, fpr[32])); | |
131 | ||
132 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
133 | &target->thread.fpr, 0, -1); | |
134 | } | |
135 | ||
136 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, | |
137 | unsigned int pos, unsigned int count, | |
138 | const void *kbuf, const void __user *ubuf) | |
139 | { | |
140 | flush_fp_to_thread(target); | |
141 | ||
142 | BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != | |
143 | offsetof(struct thread_struct, fpr[32])); | |
144 | ||
145 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
146 | &target->thread.fpr, 0, -1); | |
147 | } | |
148 | ||
865418d8 BH |
149 | static int get_fpregs(void __user *data, struct task_struct *task, |
150 | int has_fpscr) | |
151 | { | |
152 | unsigned int count = has_fpscr ? 33 : 32; | |
f65255e8 | 153 | if (!access_ok(VERIFY_WRITE, data, count * sizeof(double))) |
865418d8 | 154 | return -EFAULT; |
f65255e8 | 155 | return fpr_get(task, NULL, 0, count * sizeof(double), NULL, data); |
865418d8 BH |
156 | } |
157 | ||
158 | static int set_fpregs(void __user *data, struct task_struct *task, | |
159 | int has_fpscr) | |
160 | { | |
161 | unsigned int count = has_fpscr ? 33 : 32; | |
f65255e8 | 162 | if (!access_ok(VERIFY_READ, data, count * sizeof(double))) |
865418d8 | 163 | return -EFAULT; |
f65255e8 | 164 | return fpr_set(task, NULL, 0, count * sizeof(double), NULL, data); |
865418d8 BH |
165 | } |
166 | ||
167 | ||
168 | #ifdef CONFIG_ALTIVEC | |
169 | /* | |
170 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
171 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
172 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
173 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
174 | * vrsave as the first word (offset 0) within the quadword. | |
175 | * | |
176 | * This definition of the VMX state is compatible with the current PPC32 | |
177 | * ptrace interface. This allows signal handling and ptrace to use the | |
178 | * same structures. This also simplifies the implementation of a bi-arch | |
179 | * (combined (32- and 64-bit) gdb. | |
180 | */ | |
181 | ||
3caf06c6 RM |
182 | static int vr_active(struct task_struct *target, |
183 | const struct user_regset *regset) | |
184 | { | |
185 | flush_altivec_to_thread(target); | |
186 | return target->thread.used_vr ? regset->n : 0; | |
187 | } | |
188 | ||
189 | static int vr_get(struct task_struct *target, const struct user_regset *regset, | |
190 | unsigned int pos, unsigned int count, | |
191 | void *kbuf, void __user *ubuf) | |
192 | { | |
193 | int ret; | |
194 | ||
195 | flush_altivec_to_thread(target); | |
196 | ||
197 | BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != | |
198 | offsetof(struct thread_struct, vr[32])); | |
199 | ||
200 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
201 | &target->thread.vr, 0, | |
202 | 33 * sizeof(vector128)); | |
203 | if (!ret) { | |
204 | /* | |
205 | * Copy out only the low-order word of vrsave. | |
206 | */ | |
207 | union { | |
208 | elf_vrreg_t reg; | |
209 | u32 word; | |
210 | } vrsave; | |
211 | memset(&vrsave, 0, sizeof(vrsave)); | |
212 | vrsave.word = target->thread.vrsave; | |
213 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, | |
214 | 33 * sizeof(vector128), -1); | |
215 | } | |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
220 | static int vr_set(struct task_struct *target, const struct user_regset *regset, | |
221 | unsigned int pos, unsigned int count, | |
222 | const void *kbuf, const void __user *ubuf) | |
223 | { | |
224 | int ret; | |
225 | ||
226 | flush_altivec_to_thread(target); | |
227 | ||
228 | BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != | |
229 | offsetof(struct thread_struct, vr[32])); | |
230 | ||
231 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
232 | &target->thread.vr, 0, 33 * sizeof(vector128)); | |
233 | if (!ret && count > 0) { | |
234 | /* | |
235 | * We use only the first word of vrsave. | |
236 | */ | |
237 | union { | |
238 | elf_vrreg_t reg; | |
239 | u32 word; | |
240 | } vrsave; | |
241 | memset(&vrsave, 0, sizeof(vrsave)); | |
242 | vrsave.word = target->thread.vrsave; | |
243 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, | |
244 | 33 * sizeof(vector128), -1); | |
245 | if (!ret) | |
246 | target->thread.vrsave = vrsave.word; | |
247 | } | |
248 | ||
249 | return ret; | |
250 | } | |
251 | ||
865418d8 BH |
252 | /* |
253 | * Get contents of AltiVec register state in task TASK | |
254 | */ | |
255 | static int get_vrregs(unsigned long __user *data, struct task_struct *task) | |
256 | { | |
3caf06c6 RM |
257 | if (!access_ok(VERIFY_WRITE, data, |
258 | 33 * sizeof(vector128) + sizeof(u32))) | |
865418d8 BH |
259 | return -EFAULT; |
260 | ||
3caf06c6 RM |
261 | return vr_get(task, NULL, 0, 33 * sizeof(vector128) + sizeof(u32), |
262 | NULL, data); | |
865418d8 BH |
263 | } |
264 | ||
265 | /* | |
266 | * Write contents of AltiVec register state into task TASK. | |
267 | */ | |
268 | static int set_vrregs(struct task_struct *task, unsigned long __user *data) | |
269 | { | |
3caf06c6 | 270 | if (!access_ok(VERIFY_READ, data, 33 * sizeof(vector128) + sizeof(u32))) |
865418d8 BH |
271 | return -EFAULT; |
272 | ||
3caf06c6 RM |
273 | return vr_set(task, NULL, 0, 33 * sizeof(vector128) + sizeof(u32), |
274 | NULL, data); | |
865418d8 BH |
275 | } |
276 | #endif /* CONFIG_ALTIVEC */ | |
277 | ||
278 | #ifdef CONFIG_SPE | |
279 | ||
280 | /* | |
281 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
282 | * | |
283 | * struct { | |
284 | * u32 evr[32]; | |
285 | * u64 acc; | |
286 | * u32 spefscr; | |
287 | * } | |
288 | */ | |
289 | ||
a4e4b175 RM |
290 | static int evr_active(struct task_struct *target, |
291 | const struct user_regset *regset) | |
865418d8 | 292 | { |
a4e4b175 RM |
293 | flush_spe_to_thread(target); |
294 | return target->thread.used_spe ? regset->n : 0; | |
295 | } | |
865418d8 | 296 | |
a4e4b175 RM |
297 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
298 | unsigned int pos, unsigned int count, | |
299 | void *kbuf, void __user *ubuf) | |
300 | { | |
301 | int ret; | |
865418d8 | 302 | |
a4e4b175 | 303 | flush_spe_to_thread(target); |
865418d8 | 304 | |
a4e4b175 RM |
305 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
306 | &target->thread.evr, | |
307 | 0, sizeof(target->thread.evr)); | |
865418d8 | 308 | |
a4e4b175 RM |
309 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
310 | offsetof(struct thread_struct, spefscr)); | |
311 | ||
312 | if (!ret) | |
313 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
314 | &target->thread.acc, | |
315 | sizeof(target->thread.evr), -1); | |
316 | ||
317 | return ret; | |
318 | } | |
319 | ||
320 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
321 | unsigned int pos, unsigned int count, | |
322 | const void *kbuf, const void __user *ubuf) | |
323 | { | |
324 | int ret; | |
325 | ||
326 | flush_spe_to_thread(target); | |
327 | ||
328 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
329 | &target->thread.evr, | |
330 | 0, sizeof(target->thread.evr)); | |
865418d8 | 331 | |
a4e4b175 RM |
332 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
333 | offsetof(struct thread_struct, spefscr)); | |
334 | ||
335 | if (!ret) | |
336 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
337 | &target->thread.acc, | |
338 | sizeof(target->thread.evr), -1); | |
339 | ||
340 | return ret; | |
865418d8 BH |
341 | } |
342 | ||
343 | /* | |
a4e4b175 | 344 | * Get contents of SPE register state in task TASK. |
865418d8 | 345 | */ |
a4e4b175 | 346 | static int get_evrregs(unsigned long __user *data, struct task_struct *task) |
865418d8 | 347 | { |
a4e4b175 | 348 | if (!access_ok(VERIFY_WRITE, data, 35 * sizeof(u32))) |
865418d8 BH |
349 | return -EFAULT; |
350 | ||
a4e4b175 RM |
351 | return evr_get(task, NULL, 0, 35 * sizeof(u32), NULL, data); |
352 | } | |
865418d8 | 353 | |
a4e4b175 RM |
354 | /* |
355 | * Write contents of SPE register state into task TASK. | |
356 | */ | |
357 | static int set_evrregs(struct task_struct *task, unsigned long *data) | |
358 | { | |
359 | if (!access_ok(VERIFY_READ, data, 35 * sizeof(u32))) | |
865418d8 BH |
360 | return -EFAULT; |
361 | ||
a4e4b175 | 362 | return evr_set(task, NULL, 0, 35 * sizeof(u32), NULL, data); |
865418d8 BH |
363 | } |
364 | #endif /* CONFIG_SPE */ | |
365 | ||
366 | ||
2a84b0d7 | 367 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
368 | { |
369 | struct pt_regs *regs = task->thread.regs; | |
370 | ||
371 | if (regs != NULL) { | |
372 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
373 | task->thread.dbcr0 = DBCR0_IDM | DBCR0_IC; | |
374 | regs->msr |= MSR_DE; | |
375 | #else | |
376 | regs->msr |= MSR_SE; | |
377 | #endif | |
378 | } | |
379 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
380 | } | |
381 | ||
2a84b0d7 | 382 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
383 | { |
384 | struct pt_regs *regs = task->thread.regs; | |
385 | ||
386 | if (regs != NULL) { | |
387 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
388 | task->thread.dbcr0 = 0; | |
389 | regs->msr &= ~MSR_DE; | |
390 | #else | |
391 | regs->msr &= ~MSR_SE; | |
392 | #endif | |
393 | } | |
394 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
395 | } | |
396 | ||
abd06505 BH |
397 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
398 | unsigned long data) | |
399 | { | |
400 | /* We only support one DABR and no IABRS at the moment */ | |
401 | if (addr > 0) | |
402 | return -EINVAL; | |
403 | ||
404 | /* The bottom 3 bits are flags */ | |
405 | if ((data & ~0x7UL) >= TASK_SIZE) | |
406 | return -EIO; | |
407 | ||
408 | /* Ensure translation is on */ | |
409 | if (data && !(data & DABR_TRANSLATION)) | |
410 | return -EIO; | |
411 | ||
412 | task->thread.dabr = data; | |
413 | return 0; | |
414 | } | |
abd06505 | 415 | |
1da177e4 LT |
416 | /* |
417 | * Called by kernel/ptrace.c when detaching.. | |
418 | * | |
419 | * Make sure single step bits etc are not set. | |
420 | */ | |
421 | void ptrace_disable(struct task_struct *child) | |
422 | { | |
423 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 424 | user_disable_single_step(child); |
1da177e4 LT |
425 | } |
426 | ||
e17666ba BH |
427 | /* |
428 | * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls, | |
429 | * we mark them as obsolete now, they will be removed in a future version | |
430 | */ | |
431 | static long arch_ptrace_old(struct task_struct *child, long request, long addr, | |
432 | long data) | |
433 | { | |
434 | int ret = -EPERM; | |
435 | ||
436 | switch(request) { | |
437 | case PPC_PTRACE_GETREGS: { /* Get GPRs 0 - 31. */ | |
438 | int i; | |
439 | unsigned long *reg = &((unsigned long *)child->thread.regs)[0]; | |
440 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
441 | ||
fabca2c0 | 442 | CHECK_FULL_REGS(child->thread.regs); |
e17666ba BH |
443 | for (i = 0; i < 32; i++) { |
444 | ret = put_user(*reg, tmp); | |
445 | if (ret) | |
446 | break; | |
447 | reg++; | |
448 | tmp++; | |
449 | } | |
450 | break; | |
451 | } | |
452 | ||
453 | case PPC_PTRACE_SETREGS: { /* Set GPRs 0 - 31. */ | |
454 | int i; | |
455 | unsigned long *reg = &((unsigned long *)child->thread.regs)[0]; | |
456 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
457 | ||
fabca2c0 | 458 | CHECK_FULL_REGS(child->thread.regs); |
e17666ba BH |
459 | for (i = 0; i < 32; i++) { |
460 | ret = get_user(*reg, tmp); | |
461 | if (ret) | |
462 | break; | |
463 | reg++; | |
464 | tmp++; | |
465 | } | |
466 | break; | |
467 | } | |
468 | ||
469 | case PPC_PTRACE_GETFPREGS: { /* Get FPRs 0 - 31. */ | |
470 | flush_fp_to_thread(child); | |
471 | ret = get_fpregs((void __user *)addr, child, 0); | |
472 | break; | |
473 | } | |
474 | ||
475 | case PPC_PTRACE_SETFPREGS: { /* Get FPRs 0 - 31. */ | |
476 | flush_fp_to_thread(child); | |
477 | ret = set_fpregs((void __user *)addr, child, 0); | |
478 | break; | |
479 | } | |
480 | ||
481 | } | |
482 | return ret; | |
483 | } | |
484 | ||
481bed45 | 485 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) |
1da177e4 | 486 | { |
1da177e4 LT |
487 | int ret = -EPERM; |
488 | ||
1da177e4 LT |
489 | switch (request) { |
490 | /* when I and D space are separate, these will need to be fixed. */ | |
491 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | |
76647323 AD |
492 | case PTRACE_PEEKDATA: |
493 | ret = generic_ptrace_peekdata(child, addr, data); | |
1da177e4 | 494 | break; |
1da177e4 LT |
495 | |
496 | /* read the word at location addr in the USER area. */ | |
1da177e4 LT |
497 | case PTRACE_PEEKUSR: { |
498 | unsigned long index, tmp; | |
499 | ||
500 | ret = -EIO; | |
501 | /* convert to index and check */ | |
e8a30302 | 502 | #ifdef CONFIG_PPC32 |
1da177e4 | 503 | index = (unsigned long) addr >> 2; |
e8a30302 SR |
504 | if ((addr & 3) || (index > PT_FPSCR) |
505 | || (child->thread.regs == NULL)) | |
506 | #else | |
507 | index = (unsigned long) addr >> 3; | |
508 | if ((addr & 7) || (index > PT_FPSCR)) | |
509 | #endif | |
1da177e4 LT |
510 | break; |
511 | ||
512 | CHECK_FULL_REGS(child->thread.regs); | |
513 | if (index < PT_FPR0) { | |
865418d8 | 514 | tmp = ptrace_get_reg(child, (int) index); |
1da177e4 | 515 | } else { |
e8a30302 | 516 | flush_fp_to_thread(child); |
1da177e4 LT |
517 | tmp = ((unsigned long *)child->thread.fpr)[index - PT_FPR0]; |
518 | } | |
519 | ret = put_user(tmp,(unsigned long __user *) data); | |
520 | break; | |
521 | } | |
522 | ||
523 | /* If I and D space are separate, this will have to be fixed. */ | |
524 | case PTRACE_POKETEXT: /* write the word at location addr. */ | |
525 | case PTRACE_POKEDATA: | |
f284ce72 | 526 | ret = generic_ptrace_pokedata(child, addr, data); |
1da177e4 LT |
527 | break; |
528 | ||
529 | /* write the word at location addr in the USER area */ | |
530 | case PTRACE_POKEUSR: { | |
531 | unsigned long index; | |
532 | ||
533 | ret = -EIO; | |
534 | /* convert to index and check */ | |
e8a30302 | 535 | #ifdef CONFIG_PPC32 |
1da177e4 | 536 | index = (unsigned long) addr >> 2; |
e8a30302 SR |
537 | if ((addr & 3) || (index > PT_FPSCR) |
538 | || (child->thread.regs == NULL)) | |
539 | #else | |
540 | index = (unsigned long) addr >> 3; | |
541 | if ((addr & 7) || (index > PT_FPSCR)) | |
542 | #endif | |
1da177e4 LT |
543 | break; |
544 | ||
545 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 546 | if (index < PT_FPR0) { |
865418d8 | 547 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 548 | } else { |
e8a30302 | 549 | flush_fp_to_thread(child); |
1da177e4 LT |
550 | ((unsigned long *)child->thread.fpr)[index - PT_FPR0] = data; |
551 | ret = 0; | |
552 | } | |
553 | break; | |
554 | } | |
555 | ||
e8a30302 SR |
556 | case PTRACE_GET_DEBUGREG: { |
557 | ret = -EINVAL; | |
558 | /* We only support one DABR and no IABRS at the moment */ | |
559 | if (addr > 0) | |
560 | break; | |
561 | ret = put_user(child->thread.dabr, | |
562 | (unsigned long __user *)data); | |
563 | break; | |
564 | } | |
565 | ||
566 | case PTRACE_SET_DEBUGREG: | |
567 | ret = ptrace_set_debugreg(child, addr, data); | |
568 | break; | |
e8a30302 | 569 | |
e17666ba BH |
570 | #ifdef CONFIG_PPC64 |
571 | case PTRACE_GETREGS64: | |
572 | #endif | |
573 | case PTRACE_GETREGS: { /* Get all pt_regs from the child. */ | |
574 | int ui; | |
575 | if (!access_ok(VERIFY_WRITE, (void __user *)data, | |
576 | sizeof(struct pt_regs))) { | |
577 | ret = -EIO; | |
578 | break; | |
579 | } | |
fabca2c0 | 580 | CHECK_FULL_REGS(child->thread.regs); |
e17666ba BH |
581 | ret = 0; |
582 | for (ui = 0; ui < PT_REGS_COUNT; ui ++) { | |
865418d8 | 583 | ret |= __put_user(ptrace_get_reg(child, ui), |
e17666ba BH |
584 | (unsigned long __user *) data); |
585 | data += sizeof(long); | |
e8a30302 SR |
586 | } |
587 | break; | |
588 | } | |
589 | ||
e17666ba BH |
590 | #ifdef CONFIG_PPC64 |
591 | case PTRACE_SETREGS64: | |
592 | #endif | |
593 | case PTRACE_SETREGS: { /* Set all gp regs in the child. */ | |
594 | unsigned long tmp; | |
595 | int ui; | |
596 | if (!access_ok(VERIFY_READ, (void __user *)data, | |
597 | sizeof(struct pt_regs))) { | |
598 | ret = -EIO; | |
599 | break; | |
600 | } | |
fabca2c0 | 601 | CHECK_FULL_REGS(child->thread.regs); |
e17666ba BH |
602 | ret = 0; |
603 | for (ui = 0; ui < PT_REGS_COUNT; ui ++) { | |
604 | ret = __get_user(tmp, (unsigned long __user *) data); | |
e8a30302 SR |
605 | if (ret) |
606 | break; | |
865418d8 | 607 | ptrace_put_reg(child, ui, tmp); |
e17666ba | 608 | data += sizeof(long); |
e8a30302 SR |
609 | } |
610 | break; | |
611 | } | |
612 | ||
e17666ba | 613 | case PTRACE_GETFPREGS: { /* Get the child FPU state (FPR0...31 + FPSCR) */ |
e8a30302 | 614 | flush_fp_to_thread(child); |
e17666ba | 615 | ret = get_fpregs((void __user *)data, child, 1); |
e8a30302 SR |
616 | break; |
617 | } | |
618 | ||
e17666ba | 619 | case PTRACE_SETFPREGS: { /* Set the child FPU state (FPR0...31 + FPSCR) */ |
e8a30302 | 620 | flush_fp_to_thread(child); |
e17666ba | 621 | ret = set_fpregs((void __user *)data, child, 1); |
e8a30302 SR |
622 | break; |
623 | } | |
e8a30302 | 624 | |
1da177e4 LT |
625 | #ifdef CONFIG_ALTIVEC |
626 | case PTRACE_GETVRREGS: | |
627 | /* Get the child altivec register state. */ | |
e8a30302 | 628 | flush_altivec_to_thread(child); |
1da177e4 LT |
629 | ret = get_vrregs((unsigned long __user *)data, child); |
630 | break; | |
631 | ||
632 | case PTRACE_SETVRREGS: | |
633 | /* Set the child altivec register state. */ | |
e8a30302 | 634 | flush_altivec_to_thread(child); |
1da177e4 LT |
635 | ret = set_vrregs(child, (unsigned long __user *)data); |
636 | break; | |
637 | #endif | |
638 | #ifdef CONFIG_SPE | |
639 | case PTRACE_GETEVRREGS: | |
640 | /* Get the child spe register state. */ | |
5e14d21e | 641 | flush_spe_to_thread(child); |
1da177e4 LT |
642 | ret = get_evrregs((unsigned long __user *)data, child); |
643 | break; | |
644 | ||
645 | case PTRACE_SETEVRREGS: | |
646 | /* Set the child spe register state. */ | |
647 | /* this is to clear the MSR_SPE bit to force a reload | |
648 | * of register state from memory */ | |
5e14d21e | 649 | flush_spe_to_thread(child); |
1da177e4 LT |
650 | ret = set_evrregs(child, (unsigned long __user *)data); |
651 | break; | |
652 | #endif | |
653 | ||
e17666ba BH |
654 | /* Old reverse args ptrace callss */ |
655 | case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */ | |
656 | case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */ | |
657 | case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */ | |
658 | case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */ | |
659 | ret = arch_ptrace_old(child, request, addr, data); | |
660 | break; | |
661 | ||
1da177e4 LT |
662 | default: |
663 | ret = ptrace_request(child, request, addr, data); | |
664 | break; | |
665 | } | |
1da177e4 LT |
666 | return ret; |
667 | } | |
668 | ||
ea9c102c | 669 | static void do_syscall_trace(void) |
1da177e4 | 670 | { |
ea9c102c DW |
671 | /* the 0x80 provides a way for the tracing parent to distinguish |
672 | between a syscall stop and SIGTRAP delivery */ | |
1da177e4 LT |
673 | ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) |
674 | ? 0x80 : 0)); | |
675 | ||
676 | /* | |
677 | * this isn't the same as continuing with a signal, but it will do | |
678 | * for normal use. strace only continues with a signal if the | |
679 | * stopping signal is not SIGTRAP. -brl | |
680 | */ | |
681 | if (current->exit_code) { | |
682 | send_sig(current->exit_code, current, 1); | |
683 | current->exit_code = 0; | |
684 | } | |
685 | } | |
ea9c102c DW |
686 | |
687 | void do_syscall_trace_enter(struct pt_regs *regs) | |
688 | { | |
e8a30302 | 689 | secure_computing(regs->gpr[0]); |
e8a30302 | 690 | |
ea9c102c DW |
691 | if (test_thread_flag(TIF_SYSCALL_TRACE) |
692 | && (current->ptrace & PT_PTRACED)) | |
693 | do_syscall_trace(); | |
694 | ||
cfcd1705 DW |
695 | if (unlikely(current->audit_context)) { |
696 | #ifdef CONFIG_PPC64 | |
697 | if (!test_thread_flag(TIF_32BIT)) | |
698 | audit_syscall_entry(AUDIT_ARCH_PPC64, | |
699 | regs->gpr[0], | |
700 | regs->gpr[3], regs->gpr[4], | |
701 | regs->gpr[5], regs->gpr[6]); | |
702 | else | |
e8a30302 | 703 | #endif |
cfcd1705 DW |
704 | audit_syscall_entry(AUDIT_ARCH_PPC, |
705 | regs->gpr[0], | |
706 | regs->gpr[3] & 0xffffffff, | |
707 | regs->gpr[4] & 0xffffffff, | |
708 | regs->gpr[5] & 0xffffffff, | |
709 | regs->gpr[6] & 0xffffffff); | |
710 | } | |
ea9c102c DW |
711 | } |
712 | ||
713 | void do_syscall_trace_leave(struct pt_regs *regs) | |
714 | { | |
ea9c102c | 715 | if (unlikely(current->audit_context)) |
4b9c876a | 716 | audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS, |
ea9c102c DW |
717 | regs->result); |
718 | ||
e8a30302 | 719 | if ((test_thread_flag(TIF_SYSCALL_TRACE) |
1bd79336 | 720 | || test_thread_flag(TIF_SINGLESTEP)) |
ea9c102c DW |
721 | && (current->ptrace & PT_PTRACED)) |
722 | do_syscall_trace(); | |
723 | } |