Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
e8a30302 | 32 | #ifdef CONFIG_PPC32 |
ea9c102c | 33 | #include <linux/module.h> |
e8a30302 | 34 | #endif |
5aae8a53 P |
35 | #include <linux/hw_breakpoint.h> |
36 | #include <linux/perf_event.h> | |
1da177e4 LT |
37 | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/page.h> | |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/system.h> | |
21a62902 | 42 | |
359e4284 MS |
43 | /* |
44 | * The parameter save area on the stack is used to store arguments being passed | |
45 | * to callee function and is located at fixed offset from stack pointer. | |
46 | */ | |
47 | #ifdef CONFIG_PPC32 | |
48 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
49 | #else /* CONFIG_PPC32 */ | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
51 | #endif | |
52 | ||
53 | struct pt_regs_offset { | |
54 | const char *name; | |
55 | int offset; | |
56 | }; | |
57 | ||
58 | #define STR(s) #s /* convert to string */ | |
59 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
60 | #define GPR_OFFSET_NAME(num) \ | |
61 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} | |
62 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
63 | ||
64 | static const struct pt_regs_offset regoffset_table[] = { | |
65 | GPR_OFFSET_NAME(0), | |
66 | GPR_OFFSET_NAME(1), | |
67 | GPR_OFFSET_NAME(2), | |
68 | GPR_OFFSET_NAME(3), | |
69 | GPR_OFFSET_NAME(4), | |
70 | GPR_OFFSET_NAME(5), | |
71 | GPR_OFFSET_NAME(6), | |
72 | GPR_OFFSET_NAME(7), | |
73 | GPR_OFFSET_NAME(8), | |
74 | GPR_OFFSET_NAME(9), | |
75 | GPR_OFFSET_NAME(10), | |
76 | GPR_OFFSET_NAME(11), | |
77 | GPR_OFFSET_NAME(12), | |
78 | GPR_OFFSET_NAME(13), | |
79 | GPR_OFFSET_NAME(14), | |
80 | GPR_OFFSET_NAME(15), | |
81 | GPR_OFFSET_NAME(16), | |
82 | GPR_OFFSET_NAME(17), | |
83 | GPR_OFFSET_NAME(18), | |
84 | GPR_OFFSET_NAME(19), | |
85 | GPR_OFFSET_NAME(20), | |
86 | GPR_OFFSET_NAME(21), | |
87 | GPR_OFFSET_NAME(22), | |
88 | GPR_OFFSET_NAME(23), | |
89 | GPR_OFFSET_NAME(24), | |
90 | GPR_OFFSET_NAME(25), | |
91 | GPR_OFFSET_NAME(26), | |
92 | GPR_OFFSET_NAME(27), | |
93 | GPR_OFFSET_NAME(28), | |
94 | GPR_OFFSET_NAME(29), | |
95 | GPR_OFFSET_NAME(30), | |
96 | GPR_OFFSET_NAME(31), | |
97 | REG_OFFSET_NAME(nip), | |
98 | REG_OFFSET_NAME(msr), | |
99 | REG_OFFSET_NAME(ctr), | |
100 | REG_OFFSET_NAME(link), | |
101 | REG_OFFSET_NAME(xer), | |
102 | REG_OFFSET_NAME(ccr), | |
103 | #ifdef CONFIG_PPC64 | |
104 | REG_OFFSET_NAME(softe), | |
105 | #else | |
106 | REG_OFFSET_NAME(mq), | |
107 | #endif | |
108 | REG_OFFSET_NAME(trap), | |
109 | REG_OFFSET_NAME(dar), | |
110 | REG_OFFSET_NAME(dsisr), | |
111 | REG_OFFSET_END, | |
112 | }; | |
113 | ||
114 | /** | |
115 | * regs_query_register_offset() - query register offset from its name | |
116 | * @name: the name of a register | |
117 | * | |
118 | * regs_query_register_offset() returns the offset of a register in struct | |
119 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
120 | */ | |
121 | int regs_query_register_offset(const char *name) | |
122 | { | |
123 | const struct pt_regs_offset *roff; | |
124 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
125 | if (!strcmp(roff->name, name)) | |
126 | return roff->offset; | |
127 | return -EINVAL; | |
128 | } | |
129 | ||
130 | /** | |
131 | * regs_query_register_name() - query register name from its offset | |
132 | * @offset: the offset of a register in struct pt_regs. | |
133 | * | |
134 | * regs_query_register_name() returns the name of a register from its | |
135 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
136 | */ | |
137 | const char *regs_query_register_name(unsigned int offset) | |
138 | { | |
139 | const struct pt_regs_offset *roff; | |
140 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
141 | if (roff->offset == offset) | |
142 | return roff->name; | |
143 | return NULL; | |
144 | } | |
145 | ||
abd06505 BH |
146 | /* |
147 | * does not yet catch signals sent when the child dies. | |
148 | * in exit.c or in signal.c. | |
149 | */ | |
150 | ||
151 | /* | |
152 | * Set of msr bits that gdb can change on behalf of a process. | |
153 | */ | |
172ae2e7 | 154 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 155 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 156 | #else |
abd06505 | 157 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 158 | #endif |
acd89828 | 159 | |
1da177e4 | 160 | /* |
abd06505 | 161 | * Max register writeable via put_reg |
1da177e4 | 162 | */ |
abd06505 BH |
163 | #ifdef CONFIG_PPC32 |
164 | #define PT_MAX_PUT_REG PT_MQ | |
165 | #else | |
166 | #define PT_MAX_PUT_REG PT_CCR | |
167 | #endif | |
1da177e4 | 168 | |
26f77130 RM |
169 | static unsigned long get_user_msr(struct task_struct *task) |
170 | { | |
171 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
172 | } | |
173 | ||
174 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
175 | { | |
176 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
177 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | /* | |
182 | * We prevent mucking around with the reserved area of trap | |
183 | * which are used internally by the kernel. | |
184 | */ | |
185 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
186 | { | |
187 | task->thread.regs->trap = trap & 0xfff0; | |
188 | return 0; | |
189 | } | |
190 | ||
865418d8 BH |
191 | /* |
192 | * Get contents of register REGNO in task TASK. | |
193 | */ | |
194 | unsigned long ptrace_get_reg(struct task_struct *task, int regno) | |
195 | { | |
865418d8 BH |
196 | if (task->thread.regs == NULL) |
197 | return -EIO; | |
198 | ||
26f77130 RM |
199 | if (regno == PT_MSR) |
200 | return get_user_msr(task); | |
865418d8 BH |
201 | |
202 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) | |
203 | return ((unsigned long *)task->thread.regs)[regno]; | |
204 | ||
205 | return -EIO; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Write contents of register REGNO in task TASK. | |
210 | */ | |
211 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
212 | { | |
213 | if (task->thread.regs == NULL) | |
214 | return -EIO; | |
215 | ||
26f77130 RM |
216 | if (regno == PT_MSR) |
217 | return set_user_msr(task, data); | |
218 | if (regno == PT_TRAP) | |
219 | return set_user_trap(task, data); | |
220 | ||
221 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
222 | ((unsigned long *)task->thread.regs)[regno] = data; |
223 | return 0; | |
224 | } | |
225 | return -EIO; | |
226 | } | |
227 | ||
44dd3f50 RM |
228 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
229 | unsigned int pos, unsigned int count, | |
230 | void *kbuf, void __user *ubuf) | |
231 | { | |
232 | int ret; | |
233 | ||
234 | if (target->thread.regs == NULL) | |
235 | return -EIO; | |
236 | ||
237 | CHECK_FULL_REGS(target->thread.regs); | |
238 | ||
239 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
240 | target->thread.regs, | |
241 | 0, offsetof(struct pt_regs, msr)); | |
242 | if (!ret) { | |
243 | unsigned long msr = get_user_msr(target); | |
244 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
245 | offsetof(struct pt_regs, msr), | |
246 | offsetof(struct pt_regs, msr) + | |
247 | sizeof(msr)); | |
248 | } | |
249 | ||
250 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
251 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
252 | ||
253 | if (!ret) | |
254 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
255 | &target->thread.regs->orig_gpr3, | |
256 | offsetof(struct pt_regs, orig_gpr3), | |
257 | sizeof(struct pt_regs)); | |
258 | if (!ret) | |
259 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
260 | sizeof(struct pt_regs), -1); | |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
265 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
266 | unsigned int pos, unsigned int count, | |
267 | const void *kbuf, const void __user *ubuf) | |
268 | { | |
269 | unsigned long reg; | |
270 | int ret; | |
271 | ||
272 | if (target->thread.regs == NULL) | |
273 | return -EIO; | |
274 | ||
275 | CHECK_FULL_REGS(target->thread.regs); | |
276 | ||
277 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
278 | target->thread.regs, | |
279 | 0, PT_MSR * sizeof(reg)); | |
280 | ||
281 | if (!ret && count > 0) { | |
282 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
283 | PT_MSR * sizeof(reg), | |
284 | (PT_MSR + 1) * sizeof(reg)); | |
285 | if (!ret) | |
286 | ret = set_user_msr(target, reg); | |
287 | } | |
288 | ||
289 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
290 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
291 | ||
292 | if (!ret) | |
293 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
294 | &target->thread.regs->orig_gpr3, | |
295 | PT_ORIG_R3 * sizeof(reg), | |
296 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
297 | ||
298 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
299 | ret = user_regset_copyin_ignore( | |
300 | &pos, &count, &kbuf, &ubuf, | |
301 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
302 | PT_TRAP * sizeof(reg)); | |
303 | ||
304 | if (!ret && count > 0) { | |
305 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
306 | PT_TRAP * sizeof(reg), | |
307 | (PT_TRAP + 1) * sizeof(reg)); | |
308 | if (!ret) | |
309 | ret = set_user_trap(target, reg); | |
310 | } | |
311 | ||
312 | if (!ret) | |
313 | ret = user_regset_copyin_ignore( | |
314 | &pos, &count, &kbuf, &ubuf, | |
315 | (PT_TRAP + 1) * sizeof(reg), -1); | |
316 | ||
317 | return ret; | |
318 | } | |
865418d8 | 319 | |
f65255e8 RM |
320 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
321 | unsigned int pos, unsigned int count, | |
322 | void *kbuf, void __user *ubuf) | |
323 | { | |
c6e6771b MN |
324 | #ifdef CONFIG_VSX |
325 | double buf[33]; | |
326 | int i; | |
327 | #endif | |
f65255e8 RM |
328 | flush_fp_to_thread(target); |
329 | ||
c6e6771b MN |
330 | #ifdef CONFIG_VSX |
331 | /* copy to local buffer then write that out */ | |
332 | for (i = 0; i < 32 ; i++) | |
333 | buf[i] = target->thread.TS_FPR(i); | |
334 | memcpy(&buf[32], &target->thread.fpscr, sizeof(double)); | |
335 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
336 | ||
337 | #else | |
f65255e8 | 338 | BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != |
9c75a31c | 339 | offsetof(struct thread_struct, TS_FPR(32))); |
f65255e8 RM |
340 | |
341 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
342 | &target->thread.fpr, 0, -1); | |
c6e6771b | 343 | #endif |
f65255e8 RM |
344 | } |
345 | ||
346 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, | |
347 | unsigned int pos, unsigned int count, | |
348 | const void *kbuf, const void __user *ubuf) | |
349 | { | |
c6e6771b MN |
350 | #ifdef CONFIG_VSX |
351 | double buf[33]; | |
352 | int i; | |
353 | #endif | |
f65255e8 RM |
354 | flush_fp_to_thread(target); |
355 | ||
c6e6771b MN |
356 | #ifdef CONFIG_VSX |
357 | /* copy to local buffer then write that out */ | |
358 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
359 | if (i) | |
360 | return i; | |
361 | for (i = 0; i < 32 ; i++) | |
362 | target->thread.TS_FPR(i) = buf[i]; | |
363 | memcpy(&target->thread.fpscr, &buf[32], sizeof(double)); | |
364 | return 0; | |
365 | #else | |
f65255e8 | 366 | BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) != |
9c75a31c | 367 | offsetof(struct thread_struct, TS_FPR(32))); |
f65255e8 RM |
368 | |
369 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
370 | &target->thread.fpr, 0, -1); | |
c6e6771b | 371 | #endif |
f65255e8 RM |
372 | } |
373 | ||
865418d8 BH |
374 | #ifdef CONFIG_ALTIVEC |
375 | /* | |
376 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
377 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
378 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
379 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
380 | * vrsave as the first word (offset 0) within the quadword. | |
381 | * | |
382 | * This definition of the VMX state is compatible with the current PPC32 | |
383 | * ptrace interface. This allows signal handling and ptrace to use the | |
384 | * same structures. This also simplifies the implementation of a bi-arch | |
385 | * (combined (32- and 64-bit) gdb. | |
386 | */ | |
387 | ||
3caf06c6 RM |
388 | static int vr_active(struct task_struct *target, |
389 | const struct user_regset *regset) | |
390 | { | |
391 | flush_altivec_to_thread(target); | |
392 | return target->thread.used_vr ? regset->n : 0; | |
393 | } | |
394 | ||
395 | static int vr_get(struct task_struct *target, const struct user_regset *regset, | |
396 | unsigned int pos, unsigned int count, | |
397 | void *kbuf, void __user *ubuf) | |
398 | { | |
399 | int ret; | |
400 | ||
401 | flush_altivec_to_thread(target); | |
402 | ||
403 | BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != | |
404 | offsetof(struct thread_struct, vr[32])); | |
405 | ||
406 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
407 | &target->thread.vr, 0, | |
408 | 33 * sizeof(vector128)); | |
409 | if (!ret) { | |
410 | /* | |
411 | * Copy out only the low-order word of vrsave. | |
412 | */ | |
413 | union { | |
414 | elf_vrreg_t reg; | |
415 | u32 word; | |
416 | } vrsave; | |
417 | memset(&vrsave, 0, sizeof(vrsave)); | |
418 | vrsave.word = target->thread.vrsave; | |
419 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, | |
420 | 33 * sizeof(vector128), -1); | |
421 | } | |
422 | ||
423 | return ret; | |
424 | } | |
425 | ||
426 | static int vr_set(struct task_struct *target, const struct user_regset *regset, | |
427 | unsigned int pos, unsigned int count, | |
428 | const void *kbuf, const void __user *ubuf) | |
429 | { | |
430 | int ret; | |
431 | ||
432 | flush_altivec_to_thread(target); | |
433 | ||
434 | BUILD_BUG_ON(offsetof(struct thread_struct, vscr) != | |
435 | offsetof(struct thread_struct, vr[32])); | |
436 | ||
437 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
438 | &target->thread.vr, 0, 33 * sizeof(vector128)); | |
439 | if (!ret && count > 0) { | |
440 | /* | |
441 | * We use only the first word of vrsave. | |
442 | */ | |
443 | union { | |
444 | elf_vrreg_t reg; | |
445 | u32 word; | |
446 | } vrsave; | |
447 | memset(&vrsave, 0, sizeof(vrsave)); | |
448 | vrsave.word = target->thread.vrsave; | |
449 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, | |
450 | 33 * sizeof(vector128), -1); | |
451 | if (!ret) | |
452 | target->thread.vrsave = vrsave.word; | |
453 | } | |
454 | ||
455 | return ret; | |
456 | } | |
865418d8 BH |
457 | #endif /* CONFIG_ALTIVEC */ |
458 | ||
ce48b210 MN |
459 | #ifdef CONFIG_VSX |
460 | /* | |
461 | * Currently to set and and get all the vsx state, you need to call | |
462 | * the fp and VMX calls aswell. This only get/sets the lower 32 | |
463 | * 128bit VSX registers. | |
464 | */ | |
465 | ||
466 | static int vsr_active(struct task_struct *target, | |
467 | const struct user_regset *regset) | |
468 | { | |
469 | flush_vsx_to_thread(target); | |
470 | return target->thread.used_vsr ? regset->n : 0; | |
471 | } | |
472 | ||
473 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, | |
474 | unsigned int pos, unsigned int count, | |
475 | void *kbuf, void __user *ubuf) | |
476 | { | |
f3e909c2 MN |
477 | double buf[32]; |
478 | int ret, i; | |
ce48b210 MN |
479 | |
480 | flush_vsx_to_thread(target); | |
481 | ||
f3e909c2 | 482 | for (i = 0; i < 32 ; i++) |
7d2a175b | 483 | buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET]; |
ce48b210 | 484 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 485 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
486 | |
487 | return ret; | |
488 | } | |
489 | ||
490 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, | |
491 | unsigned int pos, unsigned int count, | |
492 | const void *kbuf, const void __user *ubuf) | |
493 | { | |
f3e909c2 MN |
494 | double buf[32]; |
495 | int ret,i; | |
ce48b210 MN |
496 | |
497 | flush_vsx_to_thread(target); | |
498 | ||
499 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 MN |
500 | buf, 0, 32 * sizeof(double)); |
501 | for (i = 0; i < 32 ; i++) | |
7d2a175b | 502 | target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
f3e909c2 | 503 | |
ce48b210 MN |
504 | |
505 | return ret; | |
506 | } | |
507 | #endif /* CONFIG_VSX */ | |
508 | ||
865418d8 BH |
509 | #ifdef CONFIG_SPE |
510 | ||
511 | /* | |
512 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
513 | * | |
514 | * struct { | |
515 | * u32 evr[32]; | |
516 | * u64 acc; | |
517 | * u32 spefscr; | |
518 | * } | |
519 | */ | |
520 | ||
a4e4b175 RM |
521 | static int evr_active(struct task_struct *target, |
522 | const struct user_regset *regset) | |
865418d8 | 523 | { |
a4e4b175 RM |
524 | flush_spe_to_thread(target); |
525 | return target->thread.used_spe ? regset->n : 0; | |
526 | } | |
865418d8 | 527 | |
a4e4b175 RM |
528 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
529 | unsigned int pos, unsigned int count, | |
530 | void *kbuf, void __user *ubuf) | |
531 | { | |
532 | int ret; | |
865418d8 | 533 | |
a4e4b175 | 534 | flush_spe_to_thread(target); |
865418d8 | 535 | |
a4e4b175 RM |
536 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
537 | &target->thread.evr, | |
538 | 0, sizeof(target->thread.evr)); | |
865418d8 | 539 | |
a4e4b175 RM |
540 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
541 | offsetof(struct thread_struct, spefscr)); | |
542 | ||
543 | if (!ret) | |
544 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
545 | &target->thread.acc, | |
546 | sizeof(target->thread.evr), -1); | |
547 | ||
548 | return ret; | |
549 | } | |
550 | ||
551 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
552 | unsigned int pos, unsigned int count, | |
553 | const void *kbuf, const void __user *ubuf) | |
554 | { | |
555 | int ret; | |
556 | ||
557 | flush_spe_to_thread(target); | |
558 | ||
559 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
560 | &target->thread.evr, | |
561 | 0, sizeof(target->thread.evr)); | |
865418d8 | 562 | |
a4e4b175 RM |
563 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
564 | offsetof(struct thread_struct, spefscr)); | |
565 | ||
566 | if (!ret) | |
567 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
568 | &target->thread.acc, | |
569 | sizeof(target->thread.evr), -1); | |
570 | ||
571 | return ret; | |
865418d8 | 572 | } |
865418d8 BH |
573 | #endif /* CONFIG_SPE */ |
574 | ||
575 | ||
80fdf470 RM |
576 | /* |
577 | * These are our native regset flavors. | |
578 | */ | |
579 | enum powerpc_regset { | |
580 | REGSET_GPR, | |
581 | REGSET_FPR, | |
582 | #ifdef CONFIG_ALTIVEC | |
583 | REGSET_VMX, | |
584 | #endif | |
ce48b210 MN |
585 | #ifdef CONFIG_VSX |
586 | REGSET_VSX, | |
587 | #endif | |
80fdf470 RM |
588 | #ifdef CONFIG_SPE |
589 | REGSET_SPE, | |
590 | #endif | |
591 | }; | |
592 | ||
593 | static const struct user_regset native_regsets[] = { | |
594 | [REGSET_GPR] = { | |
595 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
596 | .size = sizeof(long), .align = sizeof(long), | |
597 | .get = gpr_get, .set = gpr_set | |
598 | }, | |
599 | [REGSET_FPR] = { | |
600 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
601 | .size = sizeof(double), .align = sizeof(double), | |
602 | .get = fpr_get, .set = fpr_set | |
603 | }, | |
604 | #ifdef CONFIG_ALTIVEC | |
605 | [REGSET_VMX] = { | |
606 | .core_note_type = NT_PPC_VMX, .n = 34, | |
607 | .size = sizeof(vector128), .align = sizeof(vector128), | |
608 | .active = vr_active, .get = vr_get, .set = vr_set | |
609 | }, | |
610 | #endif | |
ce48b210 MN |
611 | #ifdef CONFIG_VSX |
612 | [REGSET_VSX] = { | |
f3e909c2 MN |
613 | .core_note_type = NT_PPC_VSX, .n = 32, |
614 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
615 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
616 | }, | |
617 | #endif | |
80fdf470 RM |
618 | #ifdef CONFIG_SPE |
619 | [REGSET_SPE] = { | |
620 | .n = 35, | |
621 | .size = sizeof(u32), .align = sizeof(u32), | |
622 | .active = evr_active, .get = evr_get, .set = evr_set | |
623 | }, | |
624 | #endif | |
625 | }; | |
626 | ||
627 | static const struct user_regset_view user_ppc_native_view = { | |
628 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
629 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
630 | }; | |
631 | ||
fa8f5cb0 RM |
632 | #ifdef CONFIG_PPC64 |
633 | #include <linux/compat.h> | |
634 | ||
635 | static int gpr32_get(struct task_struct *target, | |
636 | const struct user_regset *regset, | |
637 | unsigned int pos, unsigned int count, | |
638 | void *kbuf, void __user *ubuf) | |
639 | { | |
640 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
641 | compat_ulong_t *k = kbuf; | |
642 | compat_ulong_t __user *u = ubuf; | |
643 | compat_ulong_t reg; | |
644 | ||
645 | if (target->thread.regs == NULL) | |
646 | return -EIO; | |
647 | ||
648 | CHECK_FULL_REGS(target->thread.regs); | |
649 | ||
650 | pos /= sizeof(reg); | |
651 | count /= sizeof(reg); | |
652 | ||
653 | if (kbuf) | |
654 | for (; count > 0 && pos < PT_MSR; --count) | |
655 | *k++ = regs[pos++]; | |
656 | else | |
657 | for (; count > 0 && pos < PT_MSR; --count) | |
658 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
659 | return -EFAULT; | |
660 | ||
661 | if (count > 0 && pos == PT_MSR) { | |
662 | reg = get_user_msr(target); | |
663 | if (kbuf) | |
664 | *k++ = reg; | |
665 | else if (__put_user(reg, u++)) | |
666 | return -EFAULT; | |
667 | ++pos; | |
668 | --count; | |
669 | } | |
670 | ||
671 | if (kbuf) | |
672 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
673 | *k++ = regs[pos++]; | |
674 | else | |
675 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
676 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
677 | return -EFAULT; | |
678 | ||
679 | kbuf = k; | |
680 | ubuf = u; | |
681 | pos *= sizeof(reg); | |
682 | count *= sizeof(reg); | |
683 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
684 | PT_REGS_COUNT * sizeof(reg), -1); | |
685 | } | |
686 | ||
687 | static int gpr32_set(struct task_struct *target, | |
688 | const struct user_regset *regset, | |
689 | unsigned int pos, unsigned int count, | |
690 | const void *kbuf, const void __user *ubuf) | |
691 | { | |
692 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
693 | const compat_ulong_t *k = kbuf; | |
694 | const compat_ulong_t __user *u = ubuf; | |
695 | compat_ulong_t reg; | |
696 | ||
697 | if (target->thread.regs == NULL) | |
698 | return -EIO; | |
699 | ||
700 | CHECK_FULL_REGS(target->thread.regs); | |
701 | ||
702 | pos /= sizeof(reg); | |
703 | count /= sizeof(reg); | |
704 | ||
705 | if (kbuf) | |
706 | for (; count > 0 && pos < PT_MSR; --count) | |
707 | regs[pos++] = *k++; | |
708 | else | |
709 | for (; count > 0 && pos < PT_MSR; --count) { | |
710 | if (__get_user(reg, u++)) | |
711 | return -EFAULT; | |
712 | regs[pos++] = reg; | |
713 | } | |
714 | ||
715 | ||
716 | if (count > 0 && pos == PT_MSR) { | |
717 | if (kbuf) | |
718 | reg = *k++; | |
719 | else if (__get_user(reg, u++)) | |
720 | return -EFAULT; | |
721 | set_user_msr(target, reg); | |
722 | ++pos; | |
723 | --count; | |
724 | } | |
725 | ||
c2372eb9 | 726 | if (kbuf) { |
fa8f5cb0 RM |
727 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
728 | regs[pos++] = *k++; | |
c2372eb9 RM |
729 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
730 | ++k; | |
731 | } else { | |
fa8f5cb0 RM |
732 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
733 | if (__get_user(reg, u++)) | |
734 | return -EFAULT; | |
735 | regs[pos++] = reg; | |
736 | } | |
c2372eb9 RM |
737 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
738 | if (__get_user(reg, u++)) | |
739 | return -EFAULT; | |
740 | } | |
fa8f5cb0 RM |
741 | |
742 | if (count > 0 && pos == PT_TRAP) { | |
743 | if (kbuf) | |
744 | reg = *k++; | |
745 | else if (__get_user(reg, u++)) | |
746 | return -EFAULT; | |
747 | set_user_trap(target, reg); | |
748 | ++pos; | |
749 | --count; | |
750 | } | |
751 | ||
752 | kbuf = k; | |
753 | ubuf = u; | |
754 | pos *= sizeof(reg); | |
755 | count *= sizeof(reg); | |
756 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
757 | (PT_TRAP + 1) * sizeof(reg), -1); | |
758 | } | |
759 | ||
760 | /* | |
761 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
762 | */ | |
763 | static const struct user_regset compat_regsets[] = { | |
764 | [REGSET_GPR] = { | |
765 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
766 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
767 | .get = gpr32_get, .set = gpr32_set | |
768 | }, | |
769 | [REGSET_FPR] = { | |
770 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
771 | .size = sizeof(double), .align = sizeof(double), | |
772 | .get = fpr_get, .set = fpr_set | |
773 | }, | |
774 | #ifdef CONFIG_ALTIVEC | |
775 | [REGSET_VMX] = { | |
776 | .core_note_type = NT_PPC_VMX, .n = 34, | |
777 | .size = sizeof(vector128), .align = sizeof(vector128), | |
778 | .active = vr_active, .get = vr_get, .set = vr_set | |
779 | }, | |
780 | #endif | |
781 | #ifdef CONFIG_SPE | |
782 | [REGSET_SPE] = { | |
24f1a849 | 783 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
784 | .size = sizeof(u32), .align = sizeof(u32), |
785 | .active = evr_active, .get = evr_get, .set = evr_set | |
786 | }, | |
787 | #endif | |
788 | }; | |
789 | ||
790 | static const struct user_regset_view user_ppc_compat_view = { | |
791 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
792 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
793 | }; | |
794 | #endif /* CONFIG_PPC64 */ | |
795 | ||
80fdf470 RM |
796 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
797 | { | |
fa8f5cb0 RM |
798 | #ifdef CONFIG_PPC64 |
799 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
800 | return &user_ppc_compat_view; | |
801 | #endif | |
80fdf470 RM |
802 | return &user_ppc_native_view; |
803 | } | |
804 | ||
805 | ||
2a84b0d7 | 806 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
807 | { |
808 | struct pt_regs *regs = task->thread.regs; | |
809 | ||
810 | if (regs != NULL) { | |
172ae2e7 | 811 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
ec097c84 | 812 | task->thread.dbcr0 &= ~DBCR0_BT; |
d6a61bfc | 813 | task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; |
865418d8 BH |
814 | regs->msr |= MSR_DE; |
815 | #else | |
ec097c84 | 816 | regs->msr &= ~MSR_BE; |
865418d8 BH |
817 | regs->msr |= MSR_SE; |
818 | #endif | |
819 | } | |
820 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
821 | } | |
822 | ||
ec097c84 RM |
823 | void user_enable_block_step(struct task_struct *task) |
824 | { | |
825 | struct pt_regs *regs = task->thread.regs; | |
826 | ||
827 | if (regs != NULL) { | |
172ae2e7 | 828 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
ec097c84 RM |
829 | task->thread.dbcr0 &= ~DBCR0_IC; |
830 | task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
831 | regs->msr |= MSR_DE; | |
832 | #else | |
833 | regs->msr &= ~MSR_SE; | |
834 | regs->msr |= MSR_BE; | |
835 | #endif | |
836 | } | |
837 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
838 | } | |
839 | ||
2a84b0d7 | 840 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
841 | { |
842 | struct pt_regs *regs = task->thread.regs; | |
843 | ||
844 | if (regs != NULL) { | |
172ae2e7 | 845 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
846 | /* |
847 | * The logic to disable single stepping should be as | |
848 | * simple as turning off the Instruction Complete flag. | |
849 | * And, after doing so, if all debug flags are off, turn | |
850 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
851 | */ | |
852 | task->thread.dbcr0 &= ~DBCR0_IC; | |
853 | /* | |
854 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
855 | */ | |
856 | if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, | |
857 | task->thread.dbcr1)) { | |
858 | /* | |
859 | * All debug events were off..... | |
860 | */ | |
861 | task->thread.dbcr0 &= ~DBCR0_IDM; | |
28477fb1 DK |
862 | regs->msr &= ~MSR_DE; |
863 | } | |
865418d8 | 864 | #else |
ec097c84 | 865 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
866 | #endif |
867 | } | |
868 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
869 | } | |
870 | ||
5aae8a53 P |
871 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
872 | void ptrace_triggered(struct perf_event *bp, int nmi, | |
873 | struct perf_sample_data *data, struct pt_regs *regs) | |
874 | { | |
875 | struct perf_event_attr attr; | |
876 | ||
877 | /* | |
878 | * Disable the breakpoint request here since ptrace has defined a | |
879 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
880 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
881 | * We don't have to do anything about that here | |
882 | */ | |
883 | attr = bp->attr; | |
884 | attr.disabled = true; | |
885 | modify_user_hw_breakpoint(bp, &attr); | |
886 | } | |
887 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
888 | ||
d6a61bfc | 889 | int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
890 | unsigned long data) |
891 | { | |
5aae8a53 P |
892 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
893 | int ret; | |
894 | struct thread_struct *thread = &(task->thread); | |
895 | struct perf_event *bp; | |
896 | struct perf_event_attr attr; | |
897 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
898 | ||
d6a61bfc LM |
899 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
900 | * For embedded processors we support one DAC and no IAC's at the | |
901 | * moment. | |
902 | */ | |
abd06505 BH |
903 | if (addr > 0) |
904 | return -EINVAL; | |
905 | ||
2325f0a0 | 906 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
907 | if ((data & ~0x7UL) >= TASK_SIZE) |
908 | return -EIO; | |
909 | ||
172ae2e7 | 910 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
911 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
912 | * It was assumed, on previous implementations, that 3 bits were | |
913 | * passed together with the data address, fitting the design of the | |
914 | * DABR register, as follows: | |
915 | * | |
916 | * bit 0: Read flag | |
917 | * bit 1: Write flag | |
918 | * bit 2: Breakpoint translation | |
919 | * | |
920 | * Thus, we use them here as so. | |
921 | */ | |
922 | ||
923 | /* Ensure breakpoint translation bit is set */ | |
abd06505 BH |
924 | if (data && !(data & DABR_TRANSLATION)) |
925 | return -EIO; | |
5aae8a53 P |
926 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
927 | bp = thread->ptrace_bps[0]; | |
928 | if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) { | |
929 | if (bp) { | |
930 | unregister_hw_breakpoint(bp); | |
931 | thread->ptrace_bps[0] = NULL; | |
932 | } | |
933 | return 0; | |
934 | } | |
935 | if (bp) { | |
936 | attr = bp->attr; | |
937 | attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN; | |
938 | arch_bp_generic_fields(data & | |
939 | (DABR_DATA_WRITE | DABR_DATA_READ), | |
940 | &attr.bp_type); | |
941 | ret = modify_user_hw_breakpoint(bp, &attr); | |
942 | if (ret) | |
943 | return ret; | |
944 | thread->ptrace_bps[0] = bp; | |
945 | thread->dabr = data; | |
946 | return 0; | |
947 | } | |
948 | ||
949 | /* Create a new breakpoint request if one doesn't exist already */ | |
950 | hw_breakpoint_init(&attr); | |
951 | attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN; | |
952 | arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ), | |
953 | &attr.bp_type); | |
954 | ||
955 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
956 | ptrace_triggered, task); | |
957 | if (IS_ERR(bp)) { | |
958 | thread->ptrace_bps[0] = NULL; | |
959 | return PTR_ERR(bp); | |
960 | } | |
961 | ||
962 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
abd06505 | 963 | |
d6a61bfc | 964 | /* Move contents to the DABR register */ |
abd06505 | 965 | task->thread.dabr = data; |
172ae2e7 | 966 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
967 | /* As described above, it was assumed 3 bits were passed with the data |
968 | * address, but we will assume only the mode bits will be passed | |
969 | * as to not cause alignment restrictions for DAC-based processors. | |
970 | */ | |
971 | ||
972 | /* DAC's hold the whole address without any mode flags */ | |
3bffb652 DK |
973 | task->thread.dac1 = data & ~0x3UL; |
974 | ||
975 | if (task->thread.dac1 == 0) { | |
976 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
977 | if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, | |
978 | task->thread.dbcr1)) { | |
979 | task->thread.regs->msr &= ~MSR_DE; | |
980 | task->thread.dbcr0 &= ~DBCR0_IDM; | |
981 | } | |
d6a61bfc LM |
982 | return 0; |
983 | } | |
984 | ||
985 | /* Read or Write bits must be set */ | |
986 | ||
987 | if (!(data & 0x3UL)) | |
988 | return -EINVAL; | |
989 | ||
990 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
991 | register */ | |
3bffb652 | 992 | task->thread.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
993 | |
994 | /* Check for write and read flags and set DBCR0 | |
995 | accordingly */ | |
3bffb652 | 996 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 997 | if (data & 0x1UL) |
3bffb652 | 998 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 999 | if (data & 0x2UL) |
3bffb652 | 1000 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 1001 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 1002 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
1003 | return 0; |
1004 | } | |
abd06505 | 1005 | |
1da177e4 LT |
1006 | /* |
1007 | * Called by kernel/ptrace.c when detaching.. | |
1008 | * | |
1009 | * Make sure single step bits etc are not set. | |
1010 | */ | |
1011 | void ptrace_disable(struct task_struct *child) | |
1012 | { | |
1013 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 1014 | user_disable_single_step(child); |
1da177e4 LT |
1015 | } |
1016 | ||
3bffb652 DK |
1017 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1018 | static long set_intruction_bp(struct task_struct *child, | |
1019 | struct ppc_hw_breakpoint *bp_info) | |
1020 | { | |
1021 | int slot; | |
1022 | int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0); | |
1023 | int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0); | |
1024 | int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0); | |
1025 | int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0); | |
1026 | ||
1027 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1028 | slot2_in_use = 1; | |
1029 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1030 | slot4_in_use = 1; | |
1031 | ||
1032 | if (bp_info->addr >= TASK_SIZE) | |
1033 | return -EIO; | |
1034 | ||
1035 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
1036 | ||
1037 | /* Make sure range is valid. */ | |
1038 | if (bp_info->addr2 >= TASK_SIZE) | |
1039 | return -EIO; | |
1040 | ||
1041 | /* We need a pair of IAC regsisters */ | |
1042 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
1043 | slot = 1; | |
1044 | child->thread.iac1 = bp_info->addr; | |
1045 | child->thread.iac2 = bp_info->addr2; | |
1046 | child->thread.dbcr0 |= DBCR0_IAC1; | |
1047 | if (bp_info->addr_mode == | |
1048 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1049 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
1050 | else | |
1051 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
1052 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1053 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
1054 | slot = 3; | |
1055 | child->thread.iac3 = bp_info->addr; | |
1056 | child->thread.iac4 = bp_info->addr2; | |
1057 | child->thread.dbcr0 |= DBCR0_IAC3; | |
1058 | if (bp_info->addr_mode == | |
1059 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1060 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
1061 | else | |
1062 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
1063 | #endif | |
1064 | } else | |
1065 | return -ENOSPC; | |
1066 | } else { | |
1067 | /* We only need one. If possible leave a pair free in | |
1068 | * case a range is needed later | |
1069 | */ | |
1070 | if (!slot1_in_use) { | |
1071 | /* | |
1072 | * Don't use iac1 if iac1-iac2 are free and either | |
1073 | * iac3 or iac4 (but not both) are free | |
1074 | */ | |
1075 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
1076 | slot = 1; | |
1077 | child->thread.iac1 = bp_info->addr; | |
1078 | child->thread.dbcr0 |= DBCR0_IAC1; | |
1079 | goto out; | |
1080 | } | |
1081 | } | |
1082 | if (!slot2_in_use) { | |
1083 | slot = 2; | |
1084 | child->thread.iac2 = bp_info->addr; | |
1085 | child->thread.dbcr0 |= DBCR0_IAC2; | |
1086 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1087 | } else if (!slot3_in_use) { | |
1088 | slot = 3; | |
1089 | child->thread.iac3 = bp_info->addr; | |
1090 | child->thread.dbcr0 |= DBCR0_IAC3; | |
1091 | } else if (!slot4_in_use) { | |
1092 | slot = 4; | |
1093 | child->thread.iac4 = bp_info->addr; | |
1094 | child->thread.dbcr0 |= DBCR0_IAC4; | |
1095 | #endif | |
1096 | } else | |
1097 | return -ENOSPC; | |
1098 | } | |
1099 | out: | |
1100 | child->thread.dbcr0 |= DBCR0_IDM; | |
1101 | child->thread.regs->msr |= MSR_DE; | |
1102 | ||
1103 | return slot; | |
1104 | } | |
1105 | ||
1106 | static int del_instruction_bp(struct task_struct *child, int slot) | |
1107 | { | |
1108 | switch (slot) { | |
1109 | case 1: | |
30124d11 | 1110 | if ((child->thread.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
1111 | return -ENOENT; |
1112 | ||
1113 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
1114 | /* address range - clear slots 1 & 2 */ | |
1115 | child->thread.iac2 = 0; | |
1116 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; | |
1117 | } | |
1118 | child->thread.iac1 = 0; | |
1119 | child->thread.dbcr0 &= ~DBCR0_IAC1; | |
1120 | break; | |
1121 | case 2: | |
30124d11 | 1122 | if ((child->thread.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
1123 | return -ENOENT; |
1124 | ||
1125 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1126 | /* used in a range */ | |
1127 | return -EINVAL; | |
1128 | child->thread.iac2 = 0; | |
1129 | child->thread.dbcr0 &= ~DBCR0_IAC2; | |
1130 | break; | |
1131 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1132 | case 3: | |
30124d11 | 1133 | if ((child->thread.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
1134 | return -ENOENT; |
1135 | ||
1136 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
1137 | /* address range - clear slots 3 & 4 */ | |
1138 | child->thread.iac4 = 0; | |
1139 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; | |
1140 | } | |
1141 | child->thread.iac3 = 0; | |
1142 | child->thread.dbcr0 &= ~DBCR0_IAC3; | |
1143 | break; | |
1144 | case 4: | |
30124d11 | 1145 | if ((child->thread.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
1146 | return -ENOENT; |
1147 | ||
1148 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1149 | /* Used in a range */ | |
1150 | return -EINVAL; | |
1151 | child->thread.iac4 = 0; | |
1152 | child->thread.dbcr0 &= ~DBCR0_IAC4; | |
1153 | break; | |
1154 | #endif | |
1155 | default: | |
1156 | return -EINVAL; | |
1157 | } | |
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
1162 | { | |
1163 | int byte_enable = | |
1164 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
1165 | & 0xf; | |
1166 | int condition_mode = | |
1167 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
1168 | int slot; | |
1169 | ||
1170 | if (byte_enable && (condition_mode == 0)) | |
1171 | return -EINVAL; | |
1172 | ||
1173 | if (bp_info->addr >= TASK_SIZE) | |
1174 | return -EIO; | |
1175 | ||
1176 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
1177 | slot = 1; | |
1178 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1179 | dbcr_dac(child) |= DBCR_DAC1R; | |
1180 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1181 | dbcr_dac(child) |= DBCR_DAC1W; | |
1182 | child->thread.dac1 = (unsigned long)bp_info->addr; | |
1183 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
1184 | if (byte_enable) { | |
1185 | child->thread.dvc1 = | |
1186 | (unsigned long)bp_info->condition_value; | |
1187 | child->thread.dbcr2 |= | |
1188 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | | |
1189 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
1190 | } | |
1191 | #endif | |
1192 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1193 | } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) { | |
1194 | /* Both dac1 and dac2 are part of a range */ | |
1195 | return -ENOSPC; | |
1196 | #endif | |
1197 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
1198 | slot = 2; | |
1199 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1200 | dbcr_dac(child) |= DBCR_DAC2R; | |
1201 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1202 | dbcr_dac(child) |= DBCR_DAC2W; | |
1203 | child->thread.dac2 = (unsigned long)bp_info->addr; | |
1204 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
1205 | if (byte_enable) { | |
1206 | child->thread.dvc2 = | |
1207 | (unsigned long)bp_info->condition_value; | |
1208 | child->thread.dbcr2 |= | |
1209 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | | |
1210 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
1211 | } | |
1212 | #endif | |
1213 | } else | |
1214 | return -ENOSPC; | |
1215 | child->thread.dbcr0 |= DBCR0_IDM; | |
1216 | child->thread.regs->msr |= MSR_DE; | |
1217 | ||
1218 | return slot + 4; | |
1219 | } | |
1220 | ||
1221 | static int del_dac(struct task_struct *child, int slot) | |
1222 | { | |
1223 | if (slot == 1) { | |
30124d11 | 1224 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
1225 | return -ENOENT; |
1226 | ||
1227 | child->thread.dac1 = 0; | |
1228 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1229 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1230 | if (child->thread.dbcr2 & DBCR2_DAC12MODE) { | |
1231 | child->thread.dac2 = 0; | |
1232 | child->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1233 | } | |
1234 | child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); | |
1235 | #endif | |
1236 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
1237 | child->thread.dvc1 = 0; | |
1238 | #endif | |
1239 | } else if (slot == 2) { | |
30124d11 | 1240 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
1241 | return -ENOENT; |
1242 | ||
1243 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1244 | if (child->thread.dbcr2 & DBCR2_DAC12MODE) | |
1245 | /* Part of a range */ | |
1246 | return -EINVAL; | |
1247 | child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); | |
1248 | #endif | |
1249 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
1250 | child->thread.dvc2 = 0; | |
1251 | #endif | |
1252 | child->thread.dac2 = 0; | |
1253 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1254 | } else | |
1255 | return -EINVAL; | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
1260 | ||
1261 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1262 | static int set_dac_range(struct task_struct *child, | |
1263 | struct ppc_hw_breakpoint *bp_info) | |
1264 | { | |
1265 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
1266 | ||
1267 | /* We don't allow range watchpoints to be used with DVC */ | |
1268 | if (bp_info->condition_mode) | |
1269 | return -EINVAL; | |
1270 | ||
1271 | /* | |
1272 | * Best effort to verify the address range. The user/supervisor bits | |
1273 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
1274 | * range. The simple test on the mask is not fool-proof, and any | |
1275 | * exclusive range will spill over into kernel space. | |
1276 | */ | |
1277 | if (bp_info->addr >= TASK_SIZE) | |
1278 | return -EIO; | |
1279 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
1280 | /* | |
1281 | * dac2 is a bitmask. Don't allow a mask that makes a | |
1282 | * kernel space address from a valid dac1 value | |
1283 | */ | |
1284 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
1285 | return -EIO; | |
1286 | } else { | |
1287 | /* | |
1288 | * For range breakpoints, addr2 must also be a valid address | |
1289 | */ | |
1290 | if (bp_info->addr2 >= TASK_SIZE) | |
1291 | return -EIO; | |
1292 | } | |
1293 | ||
1294 | if (child->thread.dbcr0 & | |
1295 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) | |
1296 | return -ENOSPC; | |
1297 | ||
1298 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1299 | child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); | |
1300 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1301 | child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); | |
1302 | child->thread.dac1 = bp_info->addr; | |
1303 | child->thread.dac2 = bp_info->addr2; | |
1304 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) | |
1305 | child->thread.dbcr2 |= DBCR2_DAC12M; | |
1306 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1307 | child->thread.dbcr2 |= DBCR2_DAC12MX; | |
1308 | else /* PPC_BREAKPOINT_MODE_MASK */ | |
1309 | child->thread.dbcr2 |= DBCR2_DAC12MM; | |
1310 | child->thread.regs->msr |= MSR_DE; | |
1311 | ||
1312 | return 5; | |
1313 | } | |
1314 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
1315 | ||
3162d92d DK |
1316 | static long ppc_set_hwdebug(struct task_struct *child, |
1317 | struct ppc_hw_breakpoint *bp_info) | |
1318 | { | |
3bffb652 DK |
1319 | if (bp_info->version != 1) |
1320 | return -ENOTSUPP; | |
1321 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
1322 | /* | |
1323 | * Check for invalid flags and combinations | |
1324 | */ | |
1325 | if ((bp_info->trigger_type == 0) || | |
1326 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
1327 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
1328 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
1329 | (bp_info->condition_mode & | |
1330 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
1331 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
1332 | return -EINVAL; | |
1333 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
1334 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
1335 | return -EINVAL; | |
1336 | #endif | |
1337 | ||
1338 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
1339 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
1340 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
1341 | return -EINVAL; | |
1342 | return set_intruction_bp(child, bp_info); | |
1343 | } | |
1344 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
1345 | return set_dac(child, bp_info); | |
1346 | ||
1347 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1348 | return set_dac_range(child, bp_info); | |
1349 | #else | |
1350 | return -EINVAL; | |
1351 | #endif | |
1352 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 1353 | /* |
3bffb652 | 1354 | * We only support one data breakpoint |
3162d92d DK |
1355 | */ |
1356 | if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) || | |
1357 | ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) || | |
1358 | (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) || | |
1359 | (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) || | |
1360 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
1361 | return -EINVAL; | |
1362 | ||
1363 | if (child->thread.dabr) | |
1364 | return -ENOSPC; | |
1365 | ||
1366 | if ((unsigned long)bp_info->addr >= TASK_SIZE) | |
1367 | return -EIO; | |
1368 | ||
1369 | child->thread.dabr = (unsigned long)bp_info->addr; | |
3bffb652 | 1370 | |
3162d92d | 1371 | return 1; |
3bffb652 | 1372 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
1373 | } |
1374 | ||
1375 | static long ppc_del_hwdebug(struct task_struct *child, long addr, long data) | |
1376 | { | |
3bffb652 DK |
1377 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1378 | int rc; | |
1379 | ||
1380 | if (data <= 4) | |
1381 | rc = del_instruction_bp(child, (int)data); | |
1382 | else | |
1383 | rc = del_dac(child, (int)data - 4); | |
1384 | ||
1385 | if (!rc) { | |
1386 | if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0, | |
1387 | child->thread.dbcr1)) { | |
1388 | child->thread.dbcr0 &= ~DBCR0_IDM; | |
1389 | child->thread.regs->msr &= ~MSR_DE; | |
1390 | } | |
1391 | } | |
1392 | return rc; | |
1393 | #else | |
3162d92d DK |
1394 | if (data != 1) |
1395 | return -EINVAL; | |
1396 | if (child->thread.dabr == 0) | |
1397 | return -ENOENT; | |
1398 | ||
1399 | child->thread.dabr = 0; | |
3bffb652 | 1400 | |
3162d92d | 1401 | return 0; |
3bffb652 | 1402 | #endif |
3162d92d DK |
1403 | } |
1404 | ||
e17666ba BH |
1405 | /* |
1406 | * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls, | |
1407 | * we mark them as obsolete now, they will be removed in a future version | |
1408 | */ | |
9b05a69e NK |
1409 | static long arch_ptrace_old(struct task_struct *child, long request, |
1410 | unsigned long addr, unsigned long data) | |
e17666ba | 1411 | { |
f68d2048 NK |
1412 | void __user *datavp = (void __user *) data; |
1413 | ||
c391cd00 RM |
1414 | switch (request) { |
1415 | case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */ | |
1416 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1417 | REGSET_GPR, 0, 32 * sizeof(long), | |
f68d2048 | 1418 | datavp); |
c391cd00 RM |
1419 | |
1420 | case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */ | |
1421 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1422 | REGSET_GPR, 0, 32 * sizeof(long), | |
f68d2048 | 1423 | datavp); |
c391cd00 RM |
1424 | |
1425 | case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */ | |
1426 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1427 | REGSET_FPR, 0, 32 * sizeof(double), | |
f68d2048 | 1428 | datavp); |
c391cd00 RM |
1429 | |
1430 | case PPC_PTRACE_SETFPREGS: /* Set FPRs 0 - 31. */ | |
1431 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1432 | REGSET_FPR, 0, 32 * sizeof(double), | |
f68d2048 | 1433 | datavp); |
e17666ba BH |
1434 | } |
1435 | ||
c391cd00 | 1436 | return -EPERM; |
e17666ba BH |
1437 | } |
1438 | ||
9b05a69e NK |
1439 | long arch_ptrace(struct task_struct *child, long request, |
1440 | unsigned long addr, unsigned long data) | |
1da177e4 | 1441 | { |
1da177e4 | 1442 | int ret = -EPERM; |
f68d2048 NK |
1443 | void __user *datavp = (void __user *) data; |
1444 | unsigned long __user *datalp = datavp; | |
1da177e4 | 1445 | |
1da177e4 | 1446 | switch (request) { |
1da177e4 | 1447 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
1448 | case PTRACE_PEEKUSR: { |
1449 | unsigned long index, tmp; | |
1450 | ||
1451 | ret = -EIO; | |
1452 | /* convert to index and check */ | |
e8a30302 | 1453 | #ifdef CONFIG_PPC32 |
9b05a69e | 1454 | index = addr >> 2; |
e8a30302 SR |
1455 | if ((addr & 3) || (index > PT_FPSCR) |
1456 | || (child->thread.regs == NULL)) | |
1457 | #else | |
9b05a69e | 1458 | index = addr >> 3; |
e8a30302 SR |
1459 | if ((addr & 7) || (index > PT_FPSCR)) |
1460 | #endif | |
1da177e4 LT |
1461 | break; |
1462 | ||
1463 | CHECK_FULL_REGS(child->thread.regs); | |
1464 | if (index < PT_FPR0) { | |
865418d8 | 1465 | tmp = ptrace_get_reg(child, (int) index); |
1da177e4 | 1466 | } else { |
e8a30302 | 1467 | flush_fp_to_thread(child); |
9c75a31c MN |
1468 | tmp = ((unsigned long *)child->thread.fpr) |
1469 | [TS_FPRWIDTH * (index - PT_FPR0)]; | |
1da177e4 | 1470 | } |
f68d2048 | 1471 | ret = put_user(tmp, datalp); |
1da177e4 LT |
1472 | break; |
1473 | } | |
1474 | ||
1da177e4 LT |
1475 | /* write the word at location addr in the USER area */ |
1476 | case PTRACE_POKEUSR: { | |
1477 | unsigned long index; | |
1478 | ||
1479 | ret = -EIO; | |
1480 | /* convert to index and check */ | |
e8a30302 | 1481 | #ifdef CONFIG_PPC32 |
9b05a69e | 1482 | index = addr >> 2; |
e8a30302 SR |
1483 | if ((addr & 3) || (index > PT_FPSCR) |
1484 | || (child->thread.regs == NULL)) | |
1485 | #else | |
9b05a69e | 1486 | index = addr >> 3; |
e8a30302 SR |
1487 | if ((addr & 7) || (index > PT_FPSCR)) |
1488 | #endif | |
1da177e4 LT |
1489 | break; |
1490 | ||
1491 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 1492 | if (index < PT_FPR0) { |
865418d8 | 1493 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 1494 | } else { |
e8a30302 | 1495 | flush_fp_to_thread(child); |
9c75a31c MN |
1496 | ((unsigned long *)child->thread.fpr) |
1497 | [TS_FPRWIDTH * (index - PT_FPR0)] = data; | |
1da177e4 LT |
1498 | ret = 0; |
1499 | } | |
1500 | break; | |
1501 | } | |
1502 | ||
3162d92d DK |
1503 | case PPC_PTRACE_GETHWDBGINFO: { |
1504 | struct ppc_debug_info dbginfo; | |
1505 | ||
1506 | dbginfo.version = 1; | |
3bffb652 DK |
1507 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1508 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
1509 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
1510 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
1511 | dbginfo.data_bp_alignment = 4; | |
1512 | dbginfo.sizeof_condition = 4; | |
1513 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
1514 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
1515 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1516 | dbginfo.features |= | |
1517 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
1518 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
1519 | #endif | |
1520 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
1521 | dbginfo.num_instruction_bps = 0; |
1522 | dbginfo.num_data_bps = 1; | |
1523 | dbginfo.num_condition_regs = 0; | |
1524 | #ifdef CONFIG_PPC64 | |
1525 | dbginfo.data_bp_alignment = 8; | |
1526 | #else | |
1527 | dbginfo.data_bp_alignment = 4; | |
1528 | #endif | |
1529 | dbginfo.sizeof_condition = 0; | |
1530 | dbginfo.features = 0; | |
3bffb652 | 1531 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 1532 | |
f68d2048 | 1533 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
1534 | sizeof(struct ppc_debug_info))) |
1535 | return -EFAULT; | |
f68d2048 NK |
1536 | ret = __copy_to_user(datavp, &dbginfo, |
1537 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
1538 | -EFAULT : 0; |
1539 | break; | |
1540 | } | |
1541 | ||
1542 | case PPC_PTRACE_SETHWDEBUG: { | |
1543 | struct ppc_hw_breakpoint bp_info; | |
1544 | ||
f68d2048 | 1545 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
1546 | sizeof(struct ppc_hw_breakpoint))) |
1547 | return -EFAULT; | |
f68d2048 | 1548 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
1549 | sizeof(struct ppc_hw_breakpoint)) ? |
1550 | -EFAULT : 0; | |
1551 | if (!ret) | |
1552 | ret = ppc_set_hwdebug(child, &bp_info); | |
1553 | break; | |
1554 | } | |
1555 | ||
1556 | case PPC_PTRACE_DELHWDEBUG: { | |
1557 | ret = ppc_del_hwdebug(child, addr, data); | |
1558 | break; | |
1559 | } | |
1560 | ||
e8a30302 SR |
1561 | case PTRACE_GET_DEBUGREG: { |
1562 | ret = -EINVAL; | |
1563 | /* We only support one DABR and no IABRS at the moment */ | |
1564 | if (addr > 0) | |
1565 | break; | |
3bffb652 | 1566 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
f68d2048 | 1567 | ret = put_user(child->thread.dac1, datalp); |
3bffb652 | 1568 | #else |
f68d2048 | 1569 | ret = put_user(child->thread.dabr, datalp); |
3bffb652 | 1570 | #endif |
e8a30302 SR |
1571 | break; |
1572 | } | |
1573 | ||
1574 | case PTRACE_SET_DEBUGREG: | |
1575 | ret = ptrace_set_debugreg(child, addr, data); | |
1576 | break; | |
e8a30302 | 1577 | |
e17666ba BH |
1578 | #ifdef CONFIG_PPC64 |
1579 | case PTRACE_GETREGS64: | |
1580 | #endif | |
c391cd00 RM |
1581 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
1582 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1583 | REGSET_GPR, | |
1584 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1585 | datavp); |
e8a30302 | 1586 | |
e17666ba BH |
1587 | #ifdef CONFIG_PPC64 |
1588 | case PTRACE_SETREGS64: | |
1589 | #endif | |
c391cd00 RM |
1590 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
1591 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1592 | REGSET_GPR, | |
1593 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1594 | datavp); |
c391cd00 RM |
1595 | |
1596 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
1597 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1598 | REGSET_FPR, | |
1599 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1600 | datavp); |
c391cd00 RM |
1601 | |
1602 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
1603 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1604 | REGSET_FPR, | |
1605 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1606 | datavp); |
e8a30302 | 1607 | |
1da177e4 LT |
1608 | #ifdef CONFIG_ALTIVEC |
1609 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
1610 | return copy_regset_to_user(child, &user_ppc_native_view, |
1611 | REGSET_VMX, | |
1612 | 0, (33 * sizeof(vector128) + | |
1613 | sizeof(u32)), | |
f68d2048 | 1614 | datavp); |
1da177e4 LT |
1615 | |
1616 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
1617 | return copy_regset_from_user(child, &user_ppc_native_view, |
1618 | REGSET_VMX, | |
1619 | 0, (33 * sizeof(vector128) + | |
1620 | sizeof(u32)), | |
f68d2048 | 1621 | datavp); |
1da177e4 | 1622 | #endif |
ce48b210 MN |
1623 | #ifdef CONFIG_VSX |
1624 | case PTRACE_GETVSRREGS: | |
1625 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1626 | REGSET_VSX, | |
1ac42ef8 | 1627 | 0, 32 * sizeof(double), |
f68d2048 | 1628 | datavp); |
ce48b210 MN |
1629 | |
1630 | case PTRACE_SETVSRREGS: | |
1631 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1632 | REGSET_VSX, | |
1ac42ef8 | 1633 | 0, 32 * sizeof(double), |
f68d2048 | 1634 | datavp); |
ce48b210 | 1635 | #endif |
1da177e4 LT |
1636 | #ifdef CONFIG_SPE |
1637 | case PTRACE_GETEVRREGS: | |
1638 | /* Get the child spe register state. */ | |
c391cd00 RM |
1639 | return copy_regset_to_user(child, &user_ppc_native_view, |
1640 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 1641 | datavp); |
1da177e4 LT |
1642 | |
1643 | case PTRACE_SETEVRREGS: | |
1644 | /* Set the child spe register state. */ | |
c391cd00 RM |
1645 | return copy_regset_from_user(child, &user_ppc_native_view, |
1646 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 1647 | datavp); |
1da177e4 LT |
1648 | #endif |
1649 | ||
e17666ba BH |
1650 | /* Old reverse args ptrace callss */ |
1651 | case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */ | |
1652 | case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */ | |
1653 | case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */ | |
1654 | case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */ | |
1655 | ret = arch_ptrace_old(child, request, addr, data); | |
1656 | break; | |
1657 | ||
1da177e4 LT |
1658 | default: |
1659 | ret = ptrace_request(child, request, addr, data); | |
1660 | break; | |
1661 | } | |
1da177e4 LT |
1662 | return ret; |
1663 | } | |
1664 | ||
4f72c427 RM |
1665 | /* |
1666 | * We must return the syscall number to actually look up in the table. | |
1667 | * This can be -1L to skip running any syscall at all. | |
1668 | */ | |
1669 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 1670 | { |
4f72c427 | 1671 | long ret = 0; |
ea9c102c | 1672 | |
e8a30302 | 1673 | secure_computing(regs->gpr[0]); |
e8a30302 | 1674 | |
4f72c427 RM |
1675 | if (test_thread_flag(TIF_SYSCALL_TRACE) && |
1676 | tracehook_report_syscall_entry(regs)) | |
1677 | /* | |
1678 | * Tracing decided this syscall should not happen. | |
1679 | * We'll return a bogus call number to get an ENOSYS | |
1680 | * error, but leave the original number in regs->gpr[0]. | |
1681 | */ | |
1682 | ret = -1L; | |
ea9c102c | 1683 | |
cfcd1705 DW |
1684 | if (unlikely(current->audit_context)) { |
1685 | #ifdef CONFIG_PPC64 | |
cab175f9 | 1686 | if (!is_32bit_task()) |
cfcd1705 DW |
1687 | audit_syscall_entry(AUDIT_ARCH_PPC64, |
1688 | regs->gpr[0], | |
1689 | regs->gpr[3], regs->gpr[4], | |
1690 | regs->gpr[5], regs->gpr[6]); | |
1691 | else | |
e8a30302 | 1692 | #endif |
cfcd1705 DW |
1693 | audit_syscall_entry(AUDIT_ARCH_PPC, |
1694 | regs->gpr[0], | |
1695 | regs->gpr[3] & 0xffffffff, | |
1696 | regs->gpr[4] & 0xffffffff, | |
1697 | regs->gpr[5] & 0xffffffff, | |
1698 | regs->gpr[6] & 0xffffffff); | |
1699 | } | |
4f72c427 RM |
1700 | |
1701 | return ret ?: regs->gpr[0]; | |
ea9c102c DW |
1702 | } |
1703 | ||
1704 | void do_syscall_trace_leave(struct pt_regs *regs) | |
1705 | { | |
4f72c427 RM |
1706 | int step; |
1707 | ||
ea9c102c | 1708 | if (unlikely(current->audit_context)) |
4b9c876a | 1709 | audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS, |
ea9c102c DW |
1710 | regs->result); |
1711 | ||
4f72c427 RM |
1712 | step = test_thread_flag(TIF_SINGLESTEP); |
1713 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
1714 | tracehook_report_syscall_exit(regs, step); | |
ea9c102c | 1715 | } |