Merge branch 'for-linus' of git://neil.brown.name/md
[deliverable/linux.git] / arch / powerpc / kernel / ptrace.c
CommitLineData
1da177e4 1/*
1da177e4
LT
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
b123923d 11 * and Paul Mackerras (paulus@samba.org).
1da177e4
LT
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
1da177e4
LT
22#include <linux/errno.h>
23#include <linux/ptrace.h>
f65255e8 24#include <linux/regset.h>
4f72c427 25#include <linux/tracehook.h>
3caf06c6 26#include <linux/elf.h>
1da177e4
LT
27#include <linux/user.h>
28#include <linux/security.h>
7ed20e1a 29#include <linux/signal.h>
ea9c102c
DW
30#include <linux/seccomp.h>
31#include <linux/audit.h>
e8a30302 32#ifdef CONFIG_PPC32
ea9c102c 33#include <linux/module.h>
e8a30302 34#endif
1da177e4
LT
35
36#include <asm/uaccess.h>
37#include <asm/page.h>
38#include <asm/pgtable.h>
39#include <asm/system.h>
21a62902 40
abd06505
BH
41/*
42 * does not yet catch signals sent when the child dies.
43 * in exit.c or in signal.c.
44 */
45
46/*
47 * Set of msr bits that gdb can change on behalf of a process.
48 */
49#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
50#define MSR_DEBUGCHANGE 0
1da177e4 51#else
abd06505 52#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
1da177e4 53#endif
acd89828 54
1da177e4 55/*
abd06505 56 * Max register writeable via put_reg
1da177e4 57 */
abd06505
BH
58#ifdef CONFIG_PPC32
59#define PT_MAX_PUT_REG PT_MQ
60#else
61#define PT_MAX_PUT_REG PT_CCR
62#endif
1da177e4 63
26f77130
RM
64static unsigned long get_user_msr(struct task_struct *task)
65{
66 return task->thread.regs->msr | task->thread.fpexc_mode;
67}
68
69static int set_user_msr(struct task_struct *task, unsigned long msr)
70{
71 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
72 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
73 return 0;
74}
75
76/*
77 * We prevent mucking around with the reserved area of trap
78 * which are used internally by the kernel.
79 */
80static int set_user_trap(struct task_struct *task, unsigned long trap)
81{
82 task->thread.regs->trap = trap & 0xfff0;
83 return 0;
84}
85
865418d8
BH
86/*
87 * Get contents of register REGNO in task TASK.
88 */
89unsigned long ptrace_get_reg(struct task_struct *task, int regno)
90{
865418d8
BH
91 if (task->thread.regs == NULL)
92 return -EIO;
93
26f77130
RM
94 if (regno == PT_MSR)
95 return get_user_msr(task);
865418d8
BH
96
97 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
98 return ((unsigned long *)task->thread.regs)[regno];
99
100 return -EIO;
101}
102
103/*
104 * Write contents of register REGNO in task TASK.
105 */
106int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
107{
108 if (task->thread.regs == NULL)
109 return -EIO;
110
26f77130
RM
111 if (regno == PT_MSR)
112 return set_user_msr(task, data);
113 if (regno == PT_TRAP)
114 return set_user_trap(task, data);
115
116 if (regno <= PT_MAX_PUT_REG) {
865418d8
BH
117 ((unsigned long *)task->thread.regs)[regno] = data;
118 return 0;
119 }
120 return -EIO;
121}
122
44dd3f50
RM
123static int gpr_get(struct task_struct *target, const struct user_regset *regset,
124 unsigned int pos, unsigned int count,
125 void *kbuf, void __user *ubuf)
126{
127 int ret;
128
129 if (target->thread.regs == NULL)
130 return -EIO;
131
132 CHECK_FULL_REGS(target->thread.regs);
133
134 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
135 target->thread.regs,
136 0, offsetof(struct pt_regs, msr));
137 if (!ret) {
138 unsigned long msr = get_user_msr(target);
139 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
140 offsetof(struct pt_regs, msr),
141 offsetof(struct pt_regs, msr) +
142 sizeof(msr));
143 }
144
145 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
146 offsetof(struct pt_regs, msr) + sizeof(long));
147
148 if (!ret)
149 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
150 &target->thread.regs->orig_gpr3,
151 offsetof(struct pt_regs, orig_gpr3),
152 sizeof(struct pt_regs));
153 if (!ret)
154 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
155 sizeof(struct pt_regs), -1);
156
157 return ret;
158}
159
160static int gpr_set(struct task_struct *target, const struct user_regset *regset,
161 unsigned int pos, unsigned int count,
162 const void *kbuf, const void __user *ubuf)
163{
164 unsigned long reg;
165 int ret;
166
167 if (target->thread.regs == NULL)
168 return -EIO;
169
170 CHECK_FULL_REGS(target->thread.regs);
171
172 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
173 target->thread.regs,
174 0, PT_MSR * sizeof(reg));
175
176 if (!ret && count > 0) {
177 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
178 PT_MSR * sizeof(reg),
179 (PT_MSR + 1) * sizeof(reg));
180 if (!ret)
181 ret = set_user_msr(target, reg);
182 }
183
184 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
185 offsetof(struct pt_regs, msr) + sizeof(long));
186
187 if (!ret)
188 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
189 &target->thread.regs->orig_gpr3,
190 PT_ORIG_R3 * sizeof(reg),
191 (PT_MAX_PUT_REG + 1) * sizeof(reg));
192
193 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
194 ret = user_regset_copyin_ignore(
195 &pos, &count, &kbuf, &ubuf,
196 (PT_MAX_PUT_REG + 1) * sizeof(reg),
197 PT_TRAP * sizeof(reg));
198
199 if (!ret && count > 0) {
200 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
201 PT_TRAP * sizeof(reg),
202 (PT_TRAP + 1) * sizeof(reg));
203 if (!ret)
204 ret = set_user_trap(target, reg);
205 }
206
207 if (!ret)
208 ret = user_regset_copyin_ignore(
209 &pos, &count, &kbuf, &ubuf,
210 (PT_TRAP + 1) * sizeof(reg), -1);
211
212 return ret;
213}
865418d8 214
f65255e8
RM
215static int fpr_get(struct task_struct *target, const struct user_regset *regset,
216 unsigned int pos, unsigned int count,
217 void *kbuf, void __user *ubuf)
218{
c6e6771b
MN
219#ifdef CONFIG_VSX
220 double buf[33];
221 int i;
222#endif
f65255e8
RM
223 flush_fp_to_thread(target);
224
c6e6771b
MN
225#ifdef CONFIG_VSX
226 /* copy to local buffer then write that out */
227 for (i = 0; i < 32 ; i++)
228 buf[i] = target->thread.TS_FPR(i);
229 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
230 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
231
232#else
f65255e8 233 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 234 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM
235
236 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
237 &target->thread.fpr, 0, -1);
c6e6771b 238#endif
f65255e8
RM
239}
240
241static int fpr_set(struct task_struct *target, const struct user_regset *regset,
242 unsigned int pos, unsigned int count,
243 const void *kbuf, const void __user *ubuf)
244{
c6e6771b
MN
245#ifdef CONFIG_VSX
246 double buf[33];
247 int i;
248#endif
f65255e8
RM
249 flush_fp_to_thread(target);
250
c6e6771b
MN
251#ifdef CONFIG_VSX
252 /* copy to local buffer then write that out */
253 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
254 if (i)
255 return i;
256 for (i = 0; i < 32 ; i++)
257 target->thread.TS_FPR(i) = buf[i];
258 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
259 return 0;
260#else
f65255e8 261 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
9c75a31c 262 offsetof(struct thread_struct, TS_FPR(32)));
f65255e8
RM
263
264 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
265 &target->thread.fpr, 0, -1);
c6e6771b 266#endif
f65255e8
RM
267}
268
865418d8
BH
269#ifdef CONFIG_ALTIVEC
270/*
271 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
272 * The transfer totals 34 quadword. Quadwords 0-31 contain the
273 * corresponding vector registers. Quadword 32 contains the vscr as the
274 * last word (offset 12) within that quadword. Quadword 33 contains the
275 * vrsave as the first word (offset 0) within the quadword.
276 *
277 * This definition of the VMX state is compatible with the current PPC32
278 * ptrace interface. This allows signal handling and ptrace to use the
279 * same structures. This also simplifies the implementation of a bi-arch
280 * (combined (32- and 64-bit) gdb.
281 */
282
3caf06c6
RM
283static int vr_active(struct task_struct *target,
284 const struct user_regset *regset)
285{
286 flush_altivec_to_thread(target);
287 return target->thread.used_vr ? regset->n : 0;
288}
289
290static int vr_get(struct task_struct *target, const struct user_regset *regset,
291 unsigned int pos, unsigned int count,
292 void *kbuf, void __user *ubuf)
293{
294 int ret;
295
296 flush_altivec_to_thread(target);
297
298 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
299 offsetof(struct thread_struct, vr[32]));
300
301 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
302 &target->thread.vr, 0,
303 33 * sizeof(vector128));
304 if (!ret) {
305 /*
306 * Copy out only the low-order word of vrsave.
307 */
308 union {
309 elf_vrreg_t reg;
310 u32 word;
311 } vrsave;
312 memset(&vrsave, 0, sizeof(vrsave));
313 vrsave.word = target->thread.vrsave;
314 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
315 33 * sizeof(vector128), -1);
316 }
317
318 return ret;
319}
320
321static int vr_set(struct task_struct *target, const struct user_regset *regset,
322 unsigned int pos, unsigned int count,
323 const void *kbuf, const void __user *ubuf)
324{
325 int ret;
326
327 flush_altivec_to_thread(target);
328
329 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
330 offsetof(struct thread_struct, vr[32]));
331
332 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
333 &target->thread.vr, 0, 33 * sizeof(vector128));
334 if (!ret && count > 0) {
335 /*
336 * We use only the first word of vrsave.
337 */
338 union {
339 elf_vrreg_t reg;
340 u32 word;
341 } vrsave;
342 memset(&vrsave, 0, sizeof(vrsave));
343 vrsave.word = target->thread.vrsave;
344 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
345 33 * sizeof(vector128), -1);
346 if (!ret)
347 target->thread.vrsave = vrsave.word;
348 }
349
350 return ret;
351}
865418d8
BH
352#endif /* CONFIG_ALTIVEC */
353
ce48b210
MN
354#ifdef CONFIG_VSX
355/*
356 * Currently to set and and get all the vsx state, you need to call
357 * the fp and VMX calls aswell. This only get/sets the lower 32
358 * 128bit VSX registers.
359 */
360
361static int vsr_active(struct task_struct *target,
362 const struct user_regset *regset)
363{
364 flush_vsx_to_thread(target);
365 return target->thread.used_vsr ? regset->n : 0;
366}
367
368static int vsr_get(struct task_struct *target, const struct user_regset *regset,
369 unsigned int pos, unsigned int count,
370 void *kbuf, void __user *ubuf)
371{
f3e909c2
MN
372 double buf[32];
373 int ret, i;
ce48b210
MN
374
375 flush_vsx_to_thread(target);
376
f3e909c2 377 for (i = 0; i < 32 ; i++)
7d2a175b 378 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
ce48b210 379 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
f3e909c2 380 buf, 0, 32 * sizeof(double));
ce48b210
MN
381
382 return ret;
383}
384
385static int vsr_set(struct task_struct *target, const struct user_regset *regset,
386 unsigned int pos, unsigned int count,
387 const void *kbuf, const void __user *ubuf)
388{
f3e909c2
MN
389 double buf[32];
390 int ret,i;
ce48b210
MN
391
392 flush_vsx_to_thread(target);
393
394 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
f3e909c2
MN
395 buf, 0, 32 * sizeof(double));
396 for (i = 0; i < 32 ; i++)
7d2a175b 397 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
f3e909c2 398
ce48b210
MN
399
400 return ret;
401}
402#endif /* CONFIG_VSX */
403
865418d8
BH
404#ifdef CONFIG_SPE
405
406/*
407 * For get_evrregs/set_evrregs functions 'data' has the following layout:
408 *
409 * struct {
410 * u32 evr[32];
411 * u64 acc;
412 * u32 spefscr;
413 * }
414 */
415
a4e4b175
RM
416static int evr_active(struct task_struct *target,
417 const struct user_regset *regset)
865418d8 418{
a4e4b175
RM
419 flush_spe_to_thread(target);
420 return target->thread.used_spe ? regset->n : 0;
421}
865418d8 422
a4e4b175
RM
423static int evr_get(struct task_struct *target, const struct user_regset *regset,
424 unsigned int pos, unsigned int count,
425 void *kbuf, void __user *ubuf)
426{
427 int ret;
865418d8 428
a4e4b175 429 flush_spe_to_thread(target);
865418d8 430
a4e4b175
RM
431 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
432 &target->thread.evr,
433 0, sizeof(target->thread.evr));
865418d8 434
a4e4b175
RM
435 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
436 offsetof(struct thread_struct, spefscr));
437
438 if (!ret)
439 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
440 &target->thread.acc,
441 sizeof(target->thread.evr), -1);
442
443 return ret;
444}
445
446static int evr_set(struct task_struct *target, const struct user_regset *regset,
447 unsigned int pos, unsigned int count,
448 const void *kbuf, const void __user *ubuf)
449{
450 int ret;
451
452 flush_spe_to_thread(target);
453
454 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
455 &target->thread.evr,
456 0, sizeof(target->thread.evr));
865418d8 457
a4e4b175
RM
458 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
459 offsetof(struct thread_struct, spefscr));
460
461 if (!ret)
462 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
463 &target->thread.acc,
464 sizeof(target->thread.evr), -1);
465
466 return ret;
865418d8 467}
865418d8
BH
468#endif /* CONFIG_SPE */
469
470
80fdf470
RM
471/*
472 * These are our native regset flavors.
473 */
474enum powerpc_regset {
475 REGSET_GPR,
476 REGSET_FPR,
477#ifdef CONFIG_ALTIVEC
478 REGSET_VMX,
479#endif
ce48b210
MN
480#ifdef CONFIG_VSX
481 REGSET_VSX,
482#endif
80fdf470
RM
483#ifdef CONFIG_SPE
484 REGSET_SPE,
485#endif
486};
487
488static const struct user_regset native_regsets[] = {
489 [REGSET_GPR] = {
490 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
491 .size = sizeof(long), .align = sizeof(long),
492 .get = gpr_get, .set = gpr_set
493 },
494 [REGSET_FPR] = {
495 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
496 .size = sizeof(double), .align = sizeof(double),
497 .get = fpr_get, .set = fpr_set
498 },
499#ifdef CONFIG_ALTIVEC
500 [REGSET_VMX] = {
501 .core_note_type = NT_PPC_VMX, .n = 34,
502 .size = sizeof(vector128), .align = sizeof(vector128),
503 .active = vr_active, .get = vr_get, .set = vr_set
504 },
505#endif
ce48b210
MN
506#ifdef CONFIG_VSX
507 [REGSET_VSX] = {
f3e909c2
MN
508 .core_note_type = NT_PPC_VSX, .n = 32,
509 .size = sizeof(double), .align = sizeof(double),
ce48b210
MN
510 .active = vsr_active, .get = vsr_get, .set = vsr_set
511 },
512#endif
80fdf470
RM
513#ifdef CONFIG_SPE
514 [REGSET_SPE] = {
515 .n = 35,
516 .size = sizeof(u32), .align = sizeof(u32),
517 .active = evr_active, .get = evr_get, .set = evr_set
518 },
519#endif
520};
521
522static const struct user_regset_view user_ppc_native_view = {
523 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
524 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
525};
526
fa8f5cb0
RM
527#ifdef CONFIG_PPC64
528#include <linux/compat.h>
529
530static int gpr32_get(struct task_struct *target,
531 const struct user_regset *regset,
532 unsigned int pos, unsigned int count,
533 void *kbuf, void __user *ubuf)
534{
535 const unsigned long *regs = &target->thread.regs->gpr[0];
536 compat_ulong_t *k = kbuf;
537 compat_ulong_t __user *u = ubuf;
538 compat_ulong_t reg;
539
540 if (target->thread.regs == NULL)
541 return -EIO;
542
543 CHECK_FULL_REGS(target->thread.regs);
544
545 pos /= sizeof(reg);
546 count /= sizeof(reg);
547
548 if (kbuf)
549 for (; count > 0 && pos < PT_MSR; --count)
550 *k++ = regs[pos++];
551 else
552 for (; count > 0 && pos < PT_MSR; --count)
553 if (__put_user((compat_ulong_t) regs[pos++], u++))
554 return -EFAULT;
555
556 if (count > 0 && pos == PT_MSR) {
557 reg = get_user_msr(target);
558 if (kbuf)
559 *k++ = reg;
560 else if (__put_user(reg, u++))
561 return -EFAULT;
562 ++pos;
563 --count;
564 }
565
566 if (kbuf)
567 for (; count > 0 && pos < PT_REGS_COUNT; --count)
568 *k++ = regs[pos++];
569 else
570 for (; count > 0 && pos < PT_REGS_COUNT; --count)
571 if (__put_user((compat_ulong_t) regs[pos++], u++))
572 return -EFAULT;
573
574 kbuf = k;
575 ubuf = u;
576 pos *= sizeof(reg);
577 count *= sizeof(reg);
578 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
579 PT_REGS_COUNT * sizeof(reg), -1);
580}
581
582static int gpr32_set(struct task_struct *target,
583 const struct user_regset *regset,
584 unsigned int pos, unsigned int count,
585 const void *kbuf, const void __user *ubuf)
586{
587 unsigned long *regs = &target->thread.regs->gpr[0];
588 const compat_ulong_t *k = kbuf;
589 const compat_ulong_t __user *u = ubuf;
590 compat_ulong_t reg;
591
592 if (target->thread.regs == NULL)
593 return -EIO;
594
595 CHECK_FULL_REGS(target->thread.regs);
596
597 pos /= sizeof(reg);
598 count /= sizeof(reg);
599
600 if (kbuf)
601 for (; count > 0 && pos < PT_MSR; --count)
602 regs[pos++] = *k++;
603 else
604 for (; count > 0 && pos < PT_MSR; --count) {
605 if (__get_user(reg, u++))
606 return -EFAULT;
607 regs[pos++] = reg;
608 }
609
610
611 if (count > 0 && pos == PT_MSR) {
612 if (kbuf)
613 reg = *k++;
614 else if (__get_user(reg, u++))
615 return -EFAULT;
616 set_user_msr(target, reg);
617 ++pos;
618 --count;
619 }
620
c2372eb9 621 if (kbuf) {
fa8f5cb0
RM
622 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
623 regs[pos++] = *k++;
c2372eb9
RM
624 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
625 ++k;
626 } else {
fa8f5cb0
RM
627 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
628 if (__get_user(reg, u++))
629 return -EFAULT;
630 regs[pos++] = reg;
631 }
c2372eb9
RM
632 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
633 if (__get_user(reg, u++))
634 return -EFAULT;
635 }
fa8f5cb0
RM
636
637 if (count > 0 && pos == PT_TRAP) {
638 if (kbuf)
639 reg = *k++;
640 else if (__get_user(reg, u++))
641 return -EFAULT;
642 set_user_trap(target, reg);
643 ++pos;
644 --count;
645 }
646
647 kbuf = k;
648 ubuf = u;
649 pos *= sizeof(reg);
650 count *= sizeof(reg);
651 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
652 (PT_TRAP + 1) * sizeof(reg), -1);
653}
654
655/*
656 * These are the regset flavors matching the CONFIG_PPC32 native set.
657 */
658static const struct user_regset compat_regsets[] = {
659 [REGSET_GPR] = {
660 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
661 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
662 .get = gpr32_get, .set = gpr32_set
663 },
664 [REGSET_FPR] = {
665 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
666 .size = sizeof(double), .align = sizeof(double),
667 .get = fpr_get, .set = fpr_set
668 },
669#ifdef CONFIG_ALTIVEC
670 [REGSET_VMX] = {
671 .core_note_type = NT_PPC_VMX, .n = 34,
672 .size = sizeof(vector128), .align = sizeof(vector128),
673 .active = vr_active, .get = vr_get, .set = vr_set
674 },
675#endif
676#ifdef CONFIG_SPE
677 [REGSET_SPE] = {
24f1a849 678 .core_note_type = NT_PPC_SPE, .n = 35,
fa8f5cb0
RM
679 .size = sizeof(u32), .align = sizeof(u32),
680 .active = evr_active, .get = evr_get, .set = evr_set
681 },
682#endif
683};
684
685static const struct user_regset_view user_ppc_compat_view = {
686 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
687 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
688};
689#endif /* CONFIG_PPC64 */
690
80fdf470
RM
691const struct user_regset_view *task_user_regset_view(struct task_struct *task)
692{
fa8f5cb0
RM
693#ifdef CONFIG_PPC64
694 if (test_tsk_thread_flag(task, TIF_32BIT))
695 return &user_ppc_compat_view;
696#endif
80fdf470
RM
697 return &user_ppc_native_view;
698}
699
700
2a84b0d7 701void user_enable_single_step(struct task_struct *task)
865418d8
BH
702{
703 struct pt_regs *regs = task->thread.regs;
704
705 if (regs != NULL) {
706#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
ec097c84 707 task->thread.dbcr0 &= ~DBCR0_BT;
d6a61bfc 708 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
865418d8
BH
709 regs->msr |= MSR_DE;
710#else
ec097c84 711 regs->msr &= ~MSR_BE;
865418d8
BH
712 regs->msr |= MSR_SE;
713#endif
714 }
715 set_tsk_thread_flag(task, TIF_SINGLESTEP);
716}
717
ec097c84
RM
718void user_enable_block_step(struct task_struct *task)
719{
720 struct pt_regs *regs = task->thread.regs;
721
722 if (regs != NULL) {
723#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
724 task->thread.dbcr0 &= ~DBCR0_IC;
725 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
726 regs->msr |= MSR_DE;
727#else
728 regs->msr &= ~MSR_SE;
729 regs->msr |= MSR_BE;
730#endif
731 }
732 set_tsk_thread_flag(task, TIF_SINGLESTEP);
733}
734
2a84b0d7 735void user_disable_single_step(struct task_struct *task)
865418d8
BH
736{
737 struct pt_regs *regs = task->thread.regs;
738
d6a61bfc 739
2325f0a0 740#if defined(CONFIG_BOOKE)
d6a61bfc
LM
741 /* If DAC then do not single step, skip */
742 if (task->thread.dabr)
743 return;
744#endif
745
865418d8
BH
746 if (regs != NULL) {
747#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
ec097c84 748 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
865418d8
BH
749 regs->msr &= ~MSR_DE;
750#else
ec097c84 751 regs->msr &= ~(MSR_SE | MSR_BE);
865418d8
BH
752#endif
753 }
754 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
755}
756
d6a61bfc 757int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
abd06505
BH
758 unsigned long data)
759{
d6a61bfc
LM
760 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
761 * For embedded processors we support one DAC and no IAC's at the
762 * moment.
763 */
abd06505
BH
764 if (addr > 0)
765 return -EINVAL;
766
2325f0a0 767 /* The bottom 3 bits in dabr are flags */
abd06505
BH
768 if ((data & ~0x7UL) >= TASK_SIZE)
769 return -EIO;
770
2325f0a0 771#ifndef CONFIG_BOOKE
d6a61bfc
LM
772
773 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
774 * It was assumed, on previous implementations, that 3 bits were
775 * passed together with the data address, fitting the design of the
776 * DABR register, as follows:
777 *
778 * bit 0: Read flag
779 * bit 1: Write flag
780 * bit 2: Breakpoint translation
781 *
782 * Thus, we use them here as so.
783 */
784
785 /* Ensure breakpoint translation bit is set */
abd06505
BH
786 if (data && !(data & DABR_TRANSLATION))
787 return -EIO;
788
d6a61bfc 789 /* Move contents to the DABR register */
abd06505 790 task->thread.dabr = data;
d6a61bfc
LM
791
792#endif
2325f0a0 793#if defined(CONFIG_BOOKE)
d6a61bfc
LM
794
795 /* As described above, it was assumed 3 bits were passed with the data
796 * address, but we will assume only the mode bits will be passed
797 * as to not cause alignment restrictions for DAC-based processors.
798 */
799
800 /* DAC's hold the whole address without any mode flags */
801 task->thread.dabr = data & ~0x3UL;
802
803 if (task->thread.dabr == 0) {
804 task->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
805 task->thread.regs->msr &= ~MSR_DE;
806 return 0;
807 }
808
809 /* Read or Write bits must be set */
810
811 if (!(data & 0x3UL))
812 return -EINVAL;
813
814 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
815 register */
816 task->thread.dbcr0 = DBCR0_IDM;
817
818 /* Check for write and read flags and set DBCR0
819 accordingly */
820 if (data & 0x1UL)
821 task->thread.dbcr0 |= DBSR_DAC1R;
822 if (data & 0x2UL)
823 task->thread.dbcr0 |= DBSR_DAC1W;
824
825 task->thread.regs->msr |= MSR_DE;
826#endif
abd06505
BH
827 return 0;
828}
abd06505 829
1da177e4
LT
830/*
831 * Called by kernel/ptrace.c when detaching..
832 *
833 * Make sure single step bits etc are not set.
834 */
835void ptrace_disable(struct task_struct *child)
836{
837 /* make sure the single step bit is not set. */
2a84b0d7 838 user_disable_single_step(child);
1da177e4
LT
839}
840
e17666ba
BH
841/*
842 * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
843 * we mark them as obsolete now, they will be removed in a future version
844 */
845static long arch_ptrace_old(struct task_struct *child, long request, long addr,
846 long data)
847{
c391cd00
RM
848 switch (request) {
849 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
850 return copy_regset_to_user(child, &user_ppc_native_view,
851 REGSET_GPR, 0, 32 * sizeof(long),
852 (void __user *) data);
853
854 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
855 return copy_regset_from_user(child, &user_ppc_native_view,
856 REGSET_GPR, 0, 32 * sizeof(long),
857 (const void __user *) data);
858
859 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
860 return copy_regset_to_user(child, &user_ppc_native_view,
861 REGSET_FPR, 0, 32 * sizeof(double),
862 (void __user *) data);
863
864 case PPC_PTRACE_SETFPREGS: /* Set FPRs 0 - 31. */
865 return copy_regset_from_user(child, &user_ppc_native_view,
866 REGSET_FPR, 0, 32 * sizeof(double),
867 (const void __user *) data);
e17666ba
BH
868 }
869
c391cd00 870 return -EPERM;
e17666ba
BH
871}
872
481bed45 873long arch_ptrace(struct task_struct *child, long request, long addr, long data)
1da177e4 874{
1da177e4
LT
875 int ret = -EPERM;
876
1da177e4 877 switch (request) {
1da177e4 878 /* read the word at location addr in the USER area. */
1da177e4
LT
879 case PTRACE_PEEKUSR: {
880 unsigned long index, tmp;
881
882 ret = -EIO;
883 /* convert to index and check */
e8a30302 884#ifdef CONFIG_PPC32
1da177e4 885 index = (unsigned long) addr >> 2;
e8a30302
SR
886 if ((addr & 3) || (index > PT_FPSCR)
887 || (child->thread.regs == NULL))
888#else
889 index = (unsigned long) addr >> 3;
890 if ((addr & 7) || (index > PT_FPSCR))
891#endif
1da177e4
LT
892 break;
893
894 CHECK_FULL_REGS(child->thread.regs);
895 if (index < PT_FPR0) {
865418d8 896 tmp = ptrace_get_reg(child, (int) index);
1da177e4 897 } else {
e8a30302 898 flush_fp_to_thread(child);
9c75a31c
MN
899 tmp = ((unsigned long *)child->thread.fpr)
900 [TS_FPRWIDTH * (index - PT_FPR0)];
1da177e4
LT
901 }
902 ret = put_user(tmp,(unsigned long __user *) data);
903 break;
904 }
905
1da177e4
LT
906 /* write the word at location addr in the USER area */
907 case PTRACE_POKEUSR: {
908 unsigned long index;
909
910 ret = -EIO;
911 /* convert to index and check */
e8a30302 912#ifdef CONFIG_PPC32
1da177e4 913 index = (unsigned long) addr >> 2;
e8a30302
SR
914 if ((addr & 3) || (index > PT_FPSCR)
915 || (child->thread.regs == NULL))
916#else
917 index = (unsigned long) addr >> 3;
918 if ((addr & 7) || (index > PT_FPSCR))
919#endif
1da177e4
LT
920 break;
921
922 CHECK_FULL_REGS(child->thread.regs);
1da177e4 923 if (index < PT_FPR0) {
865418d8 924 ret = ptrace_put_reg(child, index, data);
1da177e4 925 } else {
e8a30302 926 flush_fp_to_thread(child);
9c75a31c
MN
927 ((unsigned long *)child->thread.fpr)
928 [TS_FPRWIDTH * (index - PT_FPR0)] = data;
1da177e4
LT
929 ret = 0;
930 }
931 break;
932 }
933
e8a30302
SR
934 case PTRACE_GET_DEBUGREG: {
935 ret = -EINVAL;
936 /* We only support one DABR and no IABRS at the moment */
937 if (addr > 0)
938 break;
939 ret = put_user(child->thread.dabr,
940 (unsigned long __user *)data);
941 break;
942 }
943
944 case PTRACE_SET_DEBUGREG:
945 ret = ptrace_set_debugreg(child, addr, data);
946 break;
e8a30302 947
e17666ba
BH
948#ifdef CONFIG_PPC64
949 case PTRACE_GETREGS64:
950#endif
c391cd00
RM
951 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
952 return copy_regset_to_user(child, &user_ppc_native_view,
953 REGSET_GPR,
954 0, sizeof(struct pt_regs),
955 (void __user *) data);
e8a30302 956
e17666ba
BH
957#ifdef CONFIG_PPC64
958 case PTRACE_SETREGS64:
959#endif
c391cd00
RM
960 case PTRACE_SETREGS: /* Set all gp regs in the child. */
961 return copy_regset_from_user(child, &user_ppc_native_view,
962 REGSET_GPR,
963 0, sizeof(struct pt_regs),
964 (const void __user *) data);
965
966 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
967 return copy_regset_to_user(child, &user_ppc_native_view,
968 REGSET_FPR,
969 0, sizeof(elf_fpregset_t),
970 (void __user *) data);
971
972 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
973 return copy_regset_from_user(child, &user_ppc_native_view,
974 REGSET_FPR,
975 0, sizeof(elf_fpregset_t),
976 (const void __user *) data);
e8a30302 977
1da177e4
LT
978#ifdef CONFIG_ALTIVEC
979 case PTRACE_GETVRREGS:
c391cd00
RM
980 return copy_regset_to_user(child, &user_ppc_native_view,
981 REGSET_VMX,
982 0, (33 * sizeof(vector128) +
983 sizeof(u32)),
984 (void __user *) data);
1da177e4
LT
985
986 case PTRACE_SETVRREGS:
c391cd00
RM
987 return copy_regset_from_user(child, &user_ppc_native_view,
988 REGSET_VMX,
989 0, (33 * sizeof(vector128) +
990 sizeof(u32)),
991 (const void __user *) data);
1da177e4 992#endif
ce48b210
MN
993#ifdef CONFIG_VSX
994 case PTRACE_GETVSRREGS:
995 return copy_regset_to_user(child, &user_ppc_native_view,
996 REGSET_VSX,
1ac42ef8 997 0, 32 * sizeof(double),
ce48b210
MN
998 (void __user *) data);
999
1000 case PTRACE_SETVSRREGS:
1001 return copy_regset_from_user(child, &user_ppc_native_view,
1002 REGSET_VSX,
1ac42ef8 1003 0, 32 * sizeof(double),
ce48b210
MN
1004 (const void __user *) data);
1005#endif
1da177e4
LT
1006#ifdef CONFIG_SPE
1007 case PTRACE_GETEVRREGS:
1008 /* Get the child spe register state. */
c391cd00
RM
1009 return copy_regset_to_user(child, &user_ppc_native_view,
1010 REGSET_SPE, 0, 35 * sizeof(u32),
1011 (void __user *) data);
1da177e4
LT
1012
1013 case PTRACE_SETEVRREGS:
1014 /* Set the child spe register state. */
c391cd00
RM
1015 return copy_regset_from_user(child, &user_ppc_native_view,
1016 REGSET_SPE, 0, 35 * sizeof(u32),
1017 (const void __user *) data);
1da177e4
LT
1018#endif
1019
e17666ba
BH
1020 /* Old reverse args ptrace callss */
1021 case PPC_PTRACE_GETREGS: /* Get GPRs 0 - 31. */
1022 case PPC_PTRACE_SETREGS: /* Set GPRs 0 - 31. */
1023 case PPC_PTRACE_GETFPREGS: /* Get FPRs 0 - 31. */
1024 case PPC_PTRACE_SETFPREGS: /* Get FPRs 0 - 31. */
1025 ret = arch_ptrace_old(child, request, addr, data);
1026 break;
1027
1da177e4
LT
1028 default:
1029 ret = ptrace_request(child, request, addr, data);
1030 break;
1031 }
1da177e4
LT
1032 return ret;
1033}
1034
4f72c427
RM
1035/*
1036 * We must return the syscall number to actually look up in the table.
1037 * This can be -1L to skip running any syscall at all.
1038 */
1039long do_syscall_trace_enter(struct pt_regs *regs)
1da177e4 1040{
4f72c427 1041 long ret = 0;
ea9c102c 1042
e8a30302 1043 secure_computing(regs->gpr[0]);
e8a30302 1044
4f72c427
RM
1045 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1046 tracehook_report_syscall_entry(regs))
1047 /*
1048 * Tracing decided this syscall should not happen.
1049 * We'll return a bogus call number to get an ENOSYS
1050 * error, but leave the original number in regs->gpr[0].
1051 */
1052 ret = -1L;
ea9c102c 1053
cfcd1705
DW
1054 if (unlikely(current->audit_context)) {
1055#ifdef CONFIG_PPC64
1056 if (!test_thread_flag(TIF_32BIT))
1057 audit_syscall_entry(AUDIT_ARCH_PPC64,
1058 regs->gpr[0],
1059 regs->gpr[3], regs->gpr[4],
1060 regs->gpr[5], regs->gpr[6]);
1061 else
e8a30302 1062#endif
cfcd1705
DW
1063 audit_syscall_entry(AUDIT_ARCH_PPC,
1064 regs->gpr[0],
1065 regs->gpr[3] & 0xffffffff,
1066 regs->gpr[4] & 0xffffffff,
1067 regs->gpr[5] & 0xffffffff,
1068 regs->gpr[6] & 0xffffffff);
1069 }
4f72c427
RM
1070
1071 return ret ?: regs->gpr[0];
ea9c102c
DW
1072}
1073
1074void do_syscall_trace_leave(struct pt_regs *regs)
1075{
4f72c427
RM
1076 int step;
1077
ea9c102c 1078 if (unlikely(current->audit_context))
4b9c876a 1079 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
ea9c102c
DW
1080 regs->result);
1081
4f72c427
RM
1082 step = test_thread_flag(TIF_SINGLESTEP);
1083 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1084 tracehook_report_syscall_exit(regs, step);
ea9c102c 1085}
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