[deliverable/linux.git] / arch / powerpc / kernel / rtas_pci.c

/*
 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * RTAS specific routines for PCI.
 *
 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/iommu.h>
#include <asm/rtas.h>
#include <asm/mpic.h>
#include <asm/ppc-pci.h>
#include <asm/eeh.h>

/* RTAS tokens */
static int read_pci_config;
static int write_pci_config;
static int ibm_read_pci_config;
static int ibm_write_pci_config;

static inline int config_access_valid(struct pci_dn *dn, int where)
{
	if (where < 256)
		return 1;
	if (where < 4096 && dn->pci_ext_config_space)
		return 1;

	return 0;
}

static int of_device_available(struct device_node * dn)
{
        const char *status;

        status = of_get_property(dn, "status", NULL);

        if (!status)
                return 1;

        if (!strcmp(status, "okay"))
                return 1;

        return 0;
}

int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
	int returnval = -1;
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
				addr, BUID_HI(buid), BUID_LO(buid), size);
	} else {
		ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	}
	*val = returnval;

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	if (returnval == EEH_IO_ERROR_VALUE(size) &&
	    eeh_dn_check_failure (pdn->node, NULL))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_read_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 *val)
{
	struct device_node *busdn, *dn;

	if (bus->self)
		busdn = pci_device_to_OF_node(bus->self);
	else
		busdn = bus->sysdata;	/* must be a phb */

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_available(dn))
			return rtas_read_config(pdn, where, size, val);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
{
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
			BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
	} else {
		ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	}

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_write_config(struct pci_bus *bus,
				 unsigned int devfn,
				 int where, int size, u32 val)
{
	struct device_node *busdn, *dn;

	if (bus->self)
		busdn = pci_device_to_OF_node(bus->self);
	else
		busdn = bus->sysdata;	/* must be a phb */

	/* Search only direct children of the bus */
	for (dn = busdn->child; dn; dn = dn->sibling) {
		struct pci_dn *pdn = PCI_DN(dn);
		if (pdn && pdn->devfn == devfn
		    && of_device_available(dn))
			return rtas_write_config(pdn, where, size, val);
	}
	return PCIBIOS_DEVICE_NOT_FOUND;
}

struct pci_ops rtas_pci_ops = {
	.read = rtas_pci_read_config,
	.write = rtas_pci_write_config,
};

int is_python(struct device_node *dev)
{
	const char *model = of_get_property(dev, "model", NULL);

	if (model && strstr(model, "Python"))
		return 1;

	return 0;
}

static void python_countermeasures(struct device_node *dev)
{
	struct resource registers;
	void __iomem *chip_regs;
	volatile u32 val;

	if (of_address_to_resource(dev, 0, &registers)) {
		printk(KERN_ERR "Can't get address for Python workarounds !\n");
		return;
	}

	/* Python's register file is 1 MB in size. */
	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);

	/*
	 * Firmware doesn't always clear this bit which is critical
	 * for good performance - Anton
	 */

#define PRG_CL_RESET_VALID 0x00010000

	val = in_be32(chip_regs + 0xf6030);
	if (val & PRG_CL_RESET_VALID) {
		printk(KERN_INFO "Python workaround: ");
		val &= ~PRG_CL_RESET_VALID;
		out_be32(chip_regs + 0xf6030, val);
		/*
		 * We must read it back for changes to
		 * take effect
		 */
		val = in_be32(chip_regs + 0xf6030);
		printk("reg0: %x\n", val);
	}

	iounmap(chip_regs);
}

void __init init_pci_config_tokens (void)
{
	read_pci_config = rtas_token("read-pci-config");
	write_pci_config = rtas_token("write-pci-config");
	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
}

unsigned long __devinit get_phb_buid (struct device_node *phb)
{
	struct resource r;

	if (ibm_read_pci_config == -1)
		return 0;
	if (of_address_to_resource(phb, 0, &r))
		return 0;
	return r.start;
}

static int phb_set_bus_ranges(struct device_node *dev,
			      struct pci_controller *phb)
{
	const int *bus_range;
	unsigned int len;

	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		return 1;
 	}

	phb->first_busno =  bus_range[0];
	phb->last_busno  =  bus_range[1];

	return 0;
}

int __devinit rtas_setup_phb(struct pci_controller *phb)
{
	struct device_node *dev = phb->dn;

	if (is_python(dev))
		python_countermeasures(dev);

	if (phb_set_bus_ranges(dev, phb))
		return 1;

	phb->ops = &rtas_pci_ops;
	phb->buid = get_phb_buid(dev);

	return 0;
}

void __init find_and_init_phbs(void)
{
	struct device_node *node;
	struct pci_controller *phb;
	struct device_node *root = of_find_node_by_path("/");

	for_each_child_of_node(root, node) {
		if (node->type == NULL || (strcmp(node->type, "pci") != 0 &&
					   strcmp(node->type, "pciex") != 0))
			continue;

		phb = pcibios_alloc_controller(node);
		if (!phb)
			continue;
		rtas_setup_phb(phb);
		pci_process_bridge_OF_ranges(phb, node, 0);
		isa_bridge_find_early(phb);
	}

	of_node_put(root);
	pci_devs_phb_init();

	/*
	 * pci_probe_only and pci_assign_all_buses can be set via properties
	 * in chosen.
	 */
	if (of_chosen) {
		const int *prop;

		prop = of_get_property(of_chosen,
				"linux,pci-probe-only", NULL);
		if (prop)
			pci_probe_only = *prop;

#ifdef CONFIG_PPC32 /* Will be made generic soon */
		prop = of_get_property(of_chosen,
				"linux,pci-assign-all-buses", NULL);
		if (prop && *prop)
			ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
#endif /* CONFIG_PPC32 */
	}
}

/* RPA-specific bits for removing PHBs */
int pcibios_remove_root_bus(struct pci_controller *phb)
{
	struct pci_bus *b = phb->bus;
	struct resource *res;
	int rc, i;

	res = b->resource[0];
	if (!res->flags) {
		printk(KERN_ERR "%s: no IO resource for PHB %s\n", __FUNCTION__,
				b->name);
		return 1;
	}

	rc = pcibios_unmap_io_space(b);
	if (rc) {
		printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
			__FUNCTION__, b->name);
		return 1;
	}

	if (release_resource(res)) {
		printk(KERN_ERR "%s: failed to release IO on bus %s\n",
				__FUNCTION__, b->name);
		return 1;
	}

	for (i = 1; i < 3; ++i) {
		res = b->resource[i];
		if (!res->flags && i == 0) {
			printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
				__FUNCTION__, b->name);
			return 1;
		}
		if (res->flags && release_resource(res)) {
			printk(KERN_ERR
			       "%s: failed to release IO %d on bus %s\n",
				__FUNCTION__, i, b->name);
			return 1;
		}
	}

	pcibios_free_controller(phb);

	return 0;
}
EXPORT_SYMBOL(pcibios_remove_root_bus);
Commit	Line	Data
c5a3c2e5	1	/*
c5a3c2e5 AB	2	* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
	3	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	4	*
	5	* RTAS specific routines for PCI.
ae65a391	6	*
c5a3c2e5 AB	7	* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
ae65a391	13	*
c5a3c2e5 AB	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
ae65a391	18	*
c5a3c2e5 AB	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/threads.h>
	26	#include <linux/pci.h>
	27	#include <linux/string.h>
	28	#include <linux/init.h>
	29	#include <linux/bootmem.h>
	30
	31	#include <asm/io.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/irq.h>
	34	#include <asm/prom.h>
	35	#include <asm/machdep.h>
	36	#include <asm/pci-bridge.h>
	37	#include <asm/iommu.h>
	38	#include <asm/rtas.h>
bbeb3f4c	39	#include <asm/mpic.h>
d387899f	40	#include <asm/ppc-pci.h>
68a64357	41	#include <asm/eeh.h>
c5a3c2e5 AB	42
	43	/* RTAS tokens */
	44	static int read_pci_config;
	45	static int write_pci_config;
	46	static int ibm_read_pci_config;
	47	static int ibm_write_pci_config;
	48
ae65a391	49	static inline int config_access_valid(struct pci_dn *dn, int where)
c5a3c2e5 AB	50	{
	51	if (where < 256)
	52	return 1;
	53	if (where < 4096 && dn->pci_ext_config_space)
	54	return 1;
	55
	56	return 0;
	57	}
	58
293da76b JM	59	static int of_device_available(struct device_node * dn)
293da76b JM	60	{
a7f67bdf	61	const char *status;
293da76b	62
e2eb6392	63	status = of_get_property(dn, "status", NULL);
293da76b JM	64
	65	if (!status)
	66	return 1;
	67
	68	if (!strcmp(status, "okay"))
	69	return 1;
	70
	71	return 0;
	72	}
	73
7684b40c	74	int rtas_read_config(struct pci_dn pdn, int where, int size, u32 val)
c5a3c2e5 AB	75	{
	76	int returnval = -1;
	77	unsigned long buid, addr;
	78	int ret;
	79
ae65a391	80	if (!pdn)
c5a3c2e5	81	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	82	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	83	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	84
6f3d5d3c	85	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	86	buid = pdn->phb->buid;
c5a3c2e5 AB	87	if (buid) {
c5a3c2e5 AB	88	ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
ae65a391	89	addr, BUID_HI(buid), BUID_LO(buid), size);
c5a3c2e5 AB	90	} else {
	91	ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	92	}
	93	*val = returnval;
	94
	95	if (ret)
	96	return PCIBIOS_DEVICE_NOT_FOUND;
	97
1635317f	98	if (returnval == EEH_IO_ERROR_VALUE(size) &&
ae65a391	99	eeh_dn_check_failure (pdn->node, NULL))
c5a3c2e5 AB	100	return PCIBIOS_DEVICE_NOT_FOUND;
	101
	102	return PCIBIOS_SUCCESSFUL;
	103	}
	104
	105	static int rtas_pci_read_config(struct pci_bus *bus,
	106	unsigned int devfn,
	107	int where, int size, u32 *val)
	108	{
	109	struct device_node busdn, dn;
	110
	111	if (bus->self)
	112	busdn = pci_device_to_OF_node(bus->self);
	113	else
	114	busdn = bus->sysdata; /* must be a phb */
	115
	116	/* Search only direct children of the bus */
ae65a391	117	for (dn = busdn->child; dn; dn = dn->sibling) {
	118	struct pci_dn *pdn = PCI_DN(dn);
	119	if (pdn && pdn->devfn == devfn
1635317f	120	&& of_device_available(dn))
ae65a391	121	return rtas_read_config(pdn, where, size, val);
ae65a391	122	}
1635317f	123
c5a3c2e5 AB	124	return PCIBIOS_DEVICE_NOT_FOUND;
	125	}
	126
ae65a391	127	int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
c5a3c2e5 AB	128	{
	129	unsigned long buid, addr;
	130	int ret;
	131
ae65a391	132	if (!pdn)
c5a3c2e5	133	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	134	if (!config_access_valid(pdn, where))
c5a3c2e5 AB	135	return PCIBIOS_BAD_REGISTER_NUMBER;
c5a3c2e5 AB	136
6f3d5d3c	137	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	138	buid = pdn->phb->buid;
c5a3c2e5	139	if (buid) {
ae65a391	140	ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
ae65a391	141	BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
c5a3c2e5 AB	142	} else {
	143	ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	144	}
	145
	146	if (ret)
	147	return PCIBIOS_DEVICE_NOT_FOUND;
	148
	149	return PCIBIOS_SUCCESSFUL;
	150	}
	151
	152	static int rtas_pci_write_config(struct pci_bus *bus,
	153	unsigned int devfn,
	154	int where, int size, u32 val)
	155	{
	156	struct device_node busdn, dn;
	157
	158	if (bus->self)
	159	busdn = pci_device_to_OF_node(bus->self);
	160	else
	161	busdn = bus->sysdata; /* must be a phb */
	162
	163	/* Search only direct children of the bus */
ae65a391	164	for (dn = busdn->child; dn; dn = dn->sibling) {
	165	struct pci_dn *pdn = PCI_DN(dn);
	166	if (pdn && pdn->devfn == devfn
1635317f	167	&& of_device_available(dn))
ae65a391	168	return rtas_write_config(pdn, where, size, val);
ae65a391	169	}
c5a3c2e5 AB	170	return PCIBIOS_DEVICE_NOT_FOUND;
	171	}
	172
	173	struct pci_ops rtas_pci_ops = {
8674e0c9 NL	174	.read = rtas_pci_read_config,
8674e0c9 NL	175	.write = rtas_pci_write_config,
c5a3c2e5 AB	176	};
	177
	178	int is_python(struct device_node *dev)
	179	{
e2eb6392	180	const char *model = of_get_property(dev, "model", NULL);
c5a3c2e5 AB	181
	182	if (model && strstr(model, "Python"))
	183	return 1;
	184
	185	return 0;
	186	}
	187
cc5d0189	188	static void python_countermeasures(struct device_node *dev)
c5a3c2e5	189	{
cc5d0189	190	struct resource registers;
c5a3c2e5 AB	191	void __iomem *chip_regs;
	192	volatile u32 val;
	193
cc5d0189 BH	194	if (of_address_to_resource(dev, 0, &registers)) {
cc5d0189 BH	195	printk(KERN_ERR "Can't get address for Python workarounds !\n");
c5a3c2e5	196	return;
cc5d0189	197	}
c5a3c2e5 AB	198
c5a3c2e5 AB	199	/* Python's register file is 1 MB in size. */
cc5d0189	200	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
c5a3c2e5	201
ae65a391	202	/*
c5a3c2e5 AB	203	* Firmware doesn't always clear this bit which is critical
	204	* for good performance - Anton
	205	*/
	206
	207	#define PRG_CL_RESET_VALID 0x00010000
	208
	209	val = in_be32(chip_regs + 0xf6030);
	210	if (val & PRG_CL_RESET_VALID) {
	211	printk(KERN_INFO "Python workaround: ");
	212	val &= ~PRG_CL_RESET_VALID;
	213	out_be32(chip_regs + 0xf6030, val);
	214	/*
	215	* We must read it back for changes to
	216	* take effect
	217	*/
	218	val = in_be32(chip_regs + 0xf6030);
	219	printk("reg0: %x\n", val);
	220	}
	221
	222	iounmap(chip_regs);
	223	}
	224
	225	void __init init_pci_config_tokens (void)
	226	{
	227	read_pci_config = rtas_token("read-pci-config");
	228	write_pci_config = rtas_token("write-pci-config");
	229	ibm_read_pci_config = rtas_token("ibm,read-pci-config");
	230	ibm_write_pci_config = rtas_token("ibm,write-pci-config");
	231	}
	232
	233	unsigned long __devinit get_phb_buid (struct device_node *phb)
	234	{
6506e710	235	struct resource r;
c5a3c2e5	236
6506e710	237	if (ibm_read_pci_config == -1)
c5a3c2e5	238	return 0;
6506e710	239	if (of_address_to_resource(phb, 0, &r))
c5a3c2e5	240	return 0;
6506e710	241	return r.start;
c5a3c2e5 AB	242	}
	243
	244	static int phb_set_bus_ranges(struct device_node *dev,
	245	struct pci_controller *phb)
	246	{
a7f67bdf	247	const int *bus_range;
c5a3c2e5 AB	248	unsigned int len;
c5a3c2e5 AB	249
e2eb6392	250	bus_range = of_get_property(dev, "bus-range", &len);
c5a3c2e5 AB	251	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	252	return 1;
	253	}
ae65a391	254
c5a3c2e5 AB	255	phb->first_busno = bus_range[0];
	256	phb->last_busno = bus_range[1];
	257
	258	return 0;
	259	}
	260
4c9d2800	261	int __devinit rtas_setup_phb(struct pci_controller *phb)
c5a3c2e5	262	{
44ef3390	263	struct device_node *dev = phb->dn;
4c9d2800	264
c5a3c2e5	265	if (is_python(dev))
cc5d0189	266	python_countermeasures(dev);
c5a3c2e5 AB	267
	268	if (phb_set_bus_ranges(dev, phb))
	269	return 1;
	270
c5a3c2e5 AB	271	phb->ops = &rtas_pci_ops;
	272	phb->buid = get_phb_buid(dev);
	273
	274	return 0;
	275	}
	276
36241ce6	277	void __init find_and_init_phbs(void)
c5a3c2e5 AB	278	{
	279	struct device_node *node;
	280	struct pci_controller *phb;
c5a3c2e5 AB	281	struct device_node *root = of_find_node_by_path("/");
c5a3c2e5 AB	282
85e99b9f	283	for_each_child_of_node(root, node) {
bb53bb3d JM	284	if (node->type == NULL \|\| (strcmp(node->type, "pci") != 0 &&
bb53bb3d JM	285	strcmp(node->type, "pciex") != 0))
c5a3c2e5 AB	286	continue;
c5a3c2e5 AB	287
b5166cc2	288	phb = pcibios_alloc_controller(node);
c5a3c2e5 AB	289	if (!phb)
c5a3c2e5 AB	290	continue;
4c9d2800	291	rtas_setup_phb(phb);
f7abbc19	292	pci_process_bridge_OF_ranges(phb, node, 0);
3d5134ee	293	isa_bridge_find_early(phb);
c5a3c2e5 AB	294	}
	295
	296	of_node_put(root);
	297	pci_devs_phb_init();
	298
	299	/*
	300	* pci_probe_only and pci_assign_all_buses can be set via properties
	301	* in chosen.
	302	*/
	303	if (of_chosen) {
a7f67bdf	304	const int *prop;
c5a3c2e5	305
e2eb6392	306	prop = of_get_property(of_chosen,
a7f67bdf	307	"linux,pci-probe-only", NULL);
c5a3c2e5 AB	308	if (prop)
	309	pci_probe_only = *prop;
	310
fc3fb71c	311	#ifdef CONFIG_PPC32 /* Will be made generic soon */
e2eb6392	312	prop = of_get_property(of_chosen,
a7f67bdf	313	"linux,pci-assign-all-buses", NULL);
fc3fb71c BH	314	if (prop && *prop)
	315	ppc_pci_flags \|= PPC_PCI_REASSIGN_ALL_BUS;
	316	#endif /* CONFIG_PPC32 */
c5a3c2e5	317	}
c5a3c2e5 AB	318	}
c5a3c2e5 AB	319
c5a3c2e5 AB	320	/* RPA-specific bits for removing PHBs */
	321	int pcibios_remove_root_bus(struct pci_controller *phb)
	322	{
	323	struct pci_bus *b = phb->bus;
	324	struct resource *res;
	325	int rc, i;
	326
	327	res = b->resource[0];
	328	if (!res->flags) {
	329	printk(KERN_ERR "%s: no IO resource for PHB %s\n", __FUNCTION__,
	330	b->name);
	331	return 1;
	332	}
	333
3d5134ee	334	rc = pcibios_unmap_io_space(b);
c5a3c2e5 AB	335	if (rc) {
	336	printk(KERN_ERR "%s: failed to unmap IO on bus %s\n",
	337	__FUNCTION__, b->name);
	338	return 1;
	339	}
	340
	341	if (release_resource(res)) {
	342	printk(KERN_ERR "%s: failed to release IO on bus %s\n",
	343	__FUNCTION__, b->name);
	344	return 1;
	345	}
	346
	347	for (i = 1; i < 3; ++i) {
	348	res = b->resource[i];
	349	if (!res->flags && i == 0) {
	350	printk(KERN_ERR "%s: no MEM resource for PHB %s\n",
	351	__FUNCTION__, b->name);
	352	return 1;
	353	}
	354	if (res->flags && release_resource(res)) {
	355	printk(KERN_ERR
	356	"%s: failed to release IO %d on bus %s\n",
	357	__FUNCTION__, i, b->name);
	358	return 1;
	359	}
	360	}
	361
b5166cc2	362	pcibios_free_controller(phb);
c5a3c2e5 AB	363
	364	return 0;
	365	}
	366	EXPORT_SYMBOL(pcibios_remove_root_bus);