Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * SMP support for ppc. | |
3 | * | |
4 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
5 | * deal of code from the sparc and intel versions. | |
6 | * | |
7 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
8 | * | |
9 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
10 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #undef DEBUG | |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
4b16f8e2 | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/sched.h> |
23 | #include <linux/smp.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/cache.h> | |
29 | #include <linux/err.h> | |
8a25a2fd | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include <linux/cpu.h> |
32 | #include <linux/notifier.h> | |
4b703a23 | 33 | #include <linux/topology.h> |
1da177e4 LT |
34 | |
35 | #include <asm/ptrace.h> | |
60063497 | 36 | #include <linux/atomic.h> |
1da177e4 | 37 | #include <asm/irq.h> |
1b67bee1 | 38 | #include <asm/hw_irq.h> |
1da177e4 LT |
39 | #include <asm/page.h> |
40 | #include <asm/pgtable.h> | |
41 | #include <asm/prom.h> | |
42 | #include <asm/smp.h> | |
1da177e4 LT |
43 | #include <asm/time.h> |
44 | #include <asm/machdep.h> | |
e2075f79 | 45 | #include <asm/cputhreads.h> |
1da177e4 | 46 | #include <asm/cputable.h> |
bbeb3f4c | 47 | #include <asm/mpic.h> |
a7f290da | 48 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
49 | #ifdef CONFIG_PPC64 |
50 | #include <asm/paca.h> | |
51 | #endif | |
18ad51dd | 52 | #include <asm/vdso.h> |
ae3a197e | 53 | #include <asm/debug.h> |
5ad57078 | 54 | |
1da177e4 | 55 | #ifdef DEBUG |
f9e4ec57 | 56 | #include <asm/udbg.h> |
1da177e4 LT |
57 | #define DBG(fmt...) udbg_printf(fmt) |
58 | #else | |
59 | #define DBG(fmt...) | |
60 | #endif | |
61 | ||
c56e5853 | 62 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
63 | /* State of each CPU during hotplug phases */ |
64 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
65 | #endif |
66 | ||
f9e4ec57 ME |
67 | struct thread_info *secondary_ti; |
68 | ||
cc1ba8ea AB |
69 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
70 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); | |
1da177e4 | 71 | |
d5a7430d | 72 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
440a0857 | 73 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
1da177e4 | 74 | |
5ad57078 | 75 | /* SMP operations for this machine */ |
1da177e4 LT |
76 | struct smp_ops_t *smp_ops; |
77 | ||
7ccbe504 BH |
78 | /* Can't be static due to PowerMac hackery */ |
79 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 80 | |
1da177e4 LT |
81 | int smt_enabled_at_boot = 1; |
82 | ||
cc532915 ME |
83 | static void (*crash_ipi_function_ptr)(struct pt_regs *) = NULL; |
84 | ||
3cd85250 AF |
85 | /* |
86 | * Returns 1 if the specified cpu should be brought up during boot. | |
87 | * Used to inhibit booting threads if they've been disabled or | |
88 | * limited on the command line | |
89 | */ | |
90 | int smp_generic_cpu_bootable(unsigned int nr) | |
91 | { | |
92 | /* Special case - we inhibit secondary thread startup | |
93 | * during boot if the user requests it. | |
94 | */ | |
95 | if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) { | |
96 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) | |
97 | return 0; | |
98 | if (smt_enabled_at_boot | |
99 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
100 | return 0; | |
101 | } | |
102 | ||
103 | return 1; | |
104 | } | |
105 | ||
106 | ||
5ad57078 | 107 | #ifdef CONFIG_PPC64 |
cad5cef6 | 108 | int smp_generic_kick_cpu(int nr) |
1da177e4 LT |
109 | { |
110 | BUG_ON(nr < 0 || nr >= NR_CPUS); | |
111 | ||
112 | /* | |
113 | * The processor is currently spinning, waiting for the | |
114 | * cpu_start field to become non-zero After we set cpu_start, | |
115 | * the processor will continue on to secondary_start | |
116 | */ | |
fb82b839 BH |
117 | if (!paca[nr].cpu_start) { |
118 | paca[nr].cpu_start = 1; | |
119 | smp_mb(); | |
120 | return 0; | |
121 | } | |
122 | ||
123 | #ifdef CONFIG_HOTPLUG_CPU | |
124 | /* | |
125 | * Ok it's not there, so it might be soft-unplugged, let's | |
126 | * try to bring it back | |
127 | */ | |
ae5cab47 | 128 | generic_set_cpu_up(nr); |
fb82b839 BH |
129 | smp_wmb(); |
130 | smp_send_reschedule(nr); | |
131 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
132 | |
133 | return 0; | |
1da177e4 | 134 | } |
fb82b839 | 135 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 136 | |
25ddd738 MM |
137 | static irqreturn_t call_function_action(int irq, void *data) |
138 | { | |
139 | generic_smp_call_function_interrupt(); | |
140 | return IRQ_HANDLED; | |
141 | } | |
142 | ||
143 | static irqreturn_t reschedule_action(int irq, void *data) | |
144 | { | |
184748cc | 145 | scheduler_ipi(); |
25ddd738 MM |
146 | return IRQ_HANDLED; |
147 | } | |
148 | ||
1b67bee1 | 149 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 150 | { |
1b67bee1 | 151 | tick_broadcast_ipi_handler(); |
25ddd738 MM |
152 | return IRQ_HANDLED; |
153 | } | |
154 | ||
7ef71d75 | 155 | static irqreturn_t debug_ipi_action(int irq, void *data) |
25ddd738 | 156 | { |
23d72bfd MM |
157 | if (crash_ipi_function_ptr) { |
158 | crash_ipi_function_ptr(get_irq_regs()); | |
159 | return IRQ_HANDLED; | |
160 | } | |
161 | ||
162 | #ifdef CONFIG_DEBUGGER | |
163 | debugger_ipi(get_irq_regs()); | |
164 | #endif /* CONFIG_DEBUGGER */ | |
165 | ||
25ddd738 MM |
166 | return IRQ_HANDLED; |
167 | } | |
168 | ||
169 | static irq_handler_t smp_ipi_action[] = { | |
170 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
171 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
1b67bee1 | 172 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
25ddd738 MM |
173 | [PPC_MSG_DEBUGGER_BREAK] = debug_ipi_action, |
174 | }; | |
175 | ||
176 | const char *smp_ipi_name[] = { | |
177 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
178 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
1b67bee1 | 179 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
25ddd738 MM |
180 | [PPC_MSG_DEBUGGER_BREAK] = "ipi debugger", |
181 | }; | |
182 | ||
183 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
184 | int smp_request_message_ipi(int virq, int msg) | |
185 | { | |
186 | int err; | |
187 | ||
188 | if (msg < 0 || msg > PPC_MSG_DEBUGGER_BREAK) { | |
189 | return -EINVAL; | |
190 | } | |
191 | #if !defined(CONFIG_DEBUGGER) && !defined(CONFIG_KEXEC) | |
192 | if (msg == PPC_MSG_DEBUGGER_BREAK) { | |
193 | return 1; | |
194 | } | |
195 | #endif | |
3b5e16d7 | 196 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 197 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 198 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
199 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
200 | virq, smp_ipi_name[msg], err); | |
201 | ||
202 | return err; | |
203 | } | |
204 | ||
1ece355b | 205 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 206 | struct cpu_messages { |
71454272 | 207 | int messages; /* current messages */ |
23d72bfd MM |
208 | unsigned long data; /* data for cause ipi */ |
209 | }; | |
210 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
211 | ||
212 | void smp_muxed_ipi_set_data(int cpu, unsigned long data) | |
213 | { | |
214 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
215 | ||
216 | info->data = data; | |
217 | } | |
218 | ||
219 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
220 | { | |
221 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 222 | char *message = (char *)&info->messages; |
23d72bfd | 223 | |
9fb1b36c PM |
224 | /* |
225 | * Order previous accesses before accesses in the IPI handler. | |
226 | */ | |
227 | smp_mb(); | |
71454272 | 228 | message[msg] = 1; |
9fb1b36c PM |
229 | /* |
230 | * cause_ipi functions are required to include a full barrier | |
231 | * before doing whatever causes the IPI. | |
232 | */ | |
23d72bfd MM |
233 | smp_ops->cause_ipi(cpu, info->data); |
234 | } | |
235 | ||
0654de1c AB |
236 | #ifdef __BIG_ENDIAN__ |
237 | #define IPI_MESSAGE(A) (1 << (24 - 8 * (A))) | |
238 | #else | |
239 | #define IPI_MESSAGE(A) (1 << (8 * (A))) | |
240 | #endif | |
241 | ||
23d72bfd MM |
242 | irqreturn_t smp_ipi_demux(void) |
243 | { | |
244 | struct cpu_messages *info = &__get_cpu_var(ipi_message); | |
71454272 | 245 | unsigned int all; |
23d72bfd MM |
246 | |
247 | mb(); /* order any irq clear */ | |
71454272 MM |
248 | |
249 | do { | |
9fb1b36c | 250 | all = xchg(&info->messages, 0); |
0654de1c | 251 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 252 | generic_smp_call_function_interrupt(); |
0654de1c | 253 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 254 | scheduler_ipi(); |
1b67bee1 SB |
255 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
256 | tick_broadcast_ipi_handler(); | |
0654de1c | 257 | if (all & IPI_MESSAGE(PPC_MSG_DEBUGGER_BREAK)) |
23d72bfd | 258 | debug_ipi_action(0, NULL); |
71454272 MM |
259 | } while (info->messages); |
260 | ||
23d72bfd MM |
261 | return IRQ_HANDLED; |
262 | } | |
1ece355b | 263 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 264 | |
9ca980dc PM |
265 | static inline void do_message_pass(int cpu, int msg) |
266 | { | |
267 | if (smp_ops->message_pass) | |
268 | smp_ops->message_pass(cpu, msg); | |
269 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
270 | else | |
271 | smp_muxed_ipi_message_pass(cpu, msg); | |
272 | #endif | |
273 | } | |
274 | ||
1da177e4 LT |
275 | void smp_send_reschedule(int cpu) |
276 | { | |
8cffc6ac | 277 | if (likely(smp_ops)) |
9ca980dc | 278 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 279 | } |
de56a948 | 280 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 281 | |
b7d7a240 JA |
282 | void arch_send_call_function_single_ipi(int cpu) |
283 | { | |
402d9a1e | 284 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
285 | } |
286 | ||
f063ea02 | 287 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
288 | { |
289 | unsigned int cpu; | |
290 | ||
f063ea02 | 291 | for_each_cpu(cpu, mask) |
9ca980dc | 292 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
293 | } |
294 | ||
1b67bee1 SB |
295 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
296 | void tick_broadcast(const struct cpumask *mask) | |
297 | { | |
298 | unsigned int cpu; | |
299 | ||
300 | for_each_cpu(cpu, mask) | |
301 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
302 | } | |
303 | #endif | |
304 | ||
e0476371 MM |
305 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
306 | void smp_send_debugger_break(void) | |
1da177e4 | 307 | { |
e0476371 MM |
308 | int cpu; |
309 | int me = raw_smp_processor_id(); | |
310 | ||
311 | if (unlikely(!smp_ops)) | |
312 | return; | |
313 | ||
314 | for_each_online_cpu(cpu) | |
315 | if (cpu != me) | |
9ca980dc | 316 | do_message_pass(cpu, PPC_MSG_DEBUGGER_BREAK); |
1da177e4 LT |
317 | } |
318 | #endif | |
319 | ||
cc532915 ME |
320 | #ifdef CONFIG_KEXEC |
321 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) | |
322 | { | |
323 | crash_ipi_function_ptr = crash_ipi_callback; | |
e0476371 | 324 | if (crash_ipi_callback) { |
cc532915 | 325 | mb(); |
e0476371 | 326 | smp_send_debugger_break(); |
cc532915 ME |
327 | } |
328 | } | |
329 | #endif | |
330 | ||
1da177e4 LT |
331 | static void stop_this_cpu(void *dummy) |
332 | { | |
8389b37d VB |
333 | /* Remove this CPU */ |
334 | set_cpu_online(smp_processor_id(), false); | |
335 | ||
1da177e4 LT |
336 | local_irq_disable(); |
337 | while (1) | |
338 | ; | |
339 | } | |
340 | ||
8fd7675c SS |
341 | void smp_send_stop(void) |
342 | { | |
8691e5a8 | 343 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
344 | } |
345 | ||
1da177e4 LT |
346 | struct thread_info *current_set[NR_CPUS]; |
347 | ||
cad5cef6 | 348 | static void smp_store_cpu_info(int id) |
1da177e4 | 349 | { |
6b7487fc | 350 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
351 | #ifdef CONFIG_PPC_FSL_BOOK3E |
352 | per_cpu(next_tlbcam_idx, id) | |
353 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
354 | #endif | |
1da177e4 LT |
355 | } |
356 | ||
1da177e4 LT |
357 | void __init smp_prepare_cpus(unsigned int max_cpus) |
358 | { | |
359 | unsigned int cpu; | |
360 | ||
361 | DBG("smp_prepare_cpus\n"); | |
362 | ||
363 | /* | |
364 | * setup_cpu may need to be called on the boot cpu. We havent | |
365 | * spun any cpus up but lets be paranoid. | |
366 | */ | |
367 | BUG_ON(boot_cpuid != smp_processor_id()); | |
368 | ||
369 | /* Fixup boot cpu */ | |
370 | smp_store_cpu_info(boot_cpuid); | |
371 | cpu_callin_map[boot_cpuid] = 1; | |
372 | ||
cc1ba8ea AB |
373 | for_each_possible_cpu(cpu) { |
374 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
375 | GFP_KERNEL, cpu_to_node(cpu)); | |
376 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), | |
377 | GFP_KERNEL, cpu_to_node(cpu)); | |
378 | } | |
379 | ||
380 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); | |
381 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); | |
382 | ||
dfee0efe CG |
383 | if (smp_ops && smp_ops->probe) |
384 | smp_ops->probe(); | |
1da177e4 LT |
385 | } |
386 | ||
cad5cef6 | 387 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
388 | { |
389 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 390 | #ifdef CONFIG_PPC64 |
1da177e4 | 391 | paca[boot_cpuid].__current = current; |
5ad57078 | 392 | #endif |
b5e2fc1c | 393 | current_set[boot_cpuid] = task_thread_info(current); |
1da177e4 LT |
394 | } |
395 | ||
396 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
397 | |
398 | int generic_cpu_disable(void) | |
399 | { | |
400 | unsigned int cpu = smp_processor_id(); | |
401 | ||
402 | if (cpu == boot_cpuid) | |
403 | return -EBUSY; | |
404 | ||
ea0f1cab | 405 | set_cpu_online(cpu, false); |
799d6046 | 406 | #ifdef CONFIG_PPC64 |
a7f290da | 407 | vdso_data->processorCount--; |
094fe2e7 | 408 | #endif |
1c91cc57 | 409 | migrate_irqs(); |
1da177e4 LT |
410 | return 0; |
411 | } | |
412 | ||
1da177e4 LT |
413 | void generic_cpu_die(unsigned int cpu) |
414 | { | |
415 | int i; | |
416 | ||
417 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 418 | smp_rmb(); |
1da177e4 LT |
419 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) |
420 | return; | |
421 | msleep(100); | |
422 | } | |
423 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
424 | } | |
425 | ||
426 | void generic_mach_cpu_die(void) | |
427 | { | |
428 | unsigned int cpu; | |
429 | ||
430 | local_irq_disable(); | |
4fcb8833 | 431 | idle_task_exit(); |
1da177e4 LT |
432 | cpu = smp_processor_id(); |
433 | printk(KERN_DEBUG "CPU%d offline\n", cpu); | |
434 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
0d8d4d42 | 435 | smp_wmb(); |
1da177e4 LT |
436 | while (__get_cpu_var(cpu_state) != CPU_UP_PREPARE) |
437 | cpu_relax(); | |
1da177e4 | 438 | } |
105765f4 BH |
439 | |
440 | void generic_set_cpu_dead(unsigned int cpu) | |
441 | { | |
442 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
443 | } | |
fb82b839 | 444 | |
ae5cab47 ZC |
445 | /* |
446 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
447 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
448 | * which makes the delay in generic_cpu_die() not happen. | |
449 | */ | |
450 | void generic_set_cpu_up(unsigned int cpu) | |
451 | { | |
452 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
453 | } | |
454 | ||
fb82b839 BH |
455 | int generic_check_cpu_restart(unsigned int cpu) |
456 | { | |
457 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
458 | } | |
512691d4 PM |
459 | |
460 | static atomic_t secondary_inhibit_count; | |
461 | ||
462 | /* | |
463 | * Don't allow secondary CPU threads to come online | |
464 | */ | |
465 | void inhibit_secondary_onlining(void) | |
466 | { | |
467 | /* | |
468 | * This makes secondary_inhibit_count stable during cpu | |
469 | * online/offline operations. | |
470 | */ | |
471 | get_online_cpus(); | |
472 | ||
473 | atomic_inc(&secondary_inhibit_count); | |
474 | put_online_cpus(); | |
475 | } | |
476 | EXPORT_SYMBOL_GPL(inhibit_secondary_onlining); | |
477 | ||
478 | /* | |
479 | * Allow secondary CPU threads to come online again | |
480 | */ | |
481 | void uninhibit_secondary_onlining(void) | |
482 | { | |
483 | get_online_cpus(); | |
484 | atomic_dec(&secondary_inhibit_count); | |
485 | put_online_cpus(); | |
486 | } | |
487 | EXPORT_SYMBOL_GPL(uninhibit_secondary_onlining); | |
488 | ||
489 | static int secondaries_inhibited(void) | |
490 | { | |
491 | return atomic_read(&secondary_inhibit_count); | |
492 | } | |
493 | ||
494 | #else /* HOTPLUG_CPU */ | |
495 | ||
496 | #define secondaries_inhibited() 0 | |
497 | ||
1da177e4 LT |
498 | #endif |
499 | ||
17e32eac | 500 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 501 | { |
17e32eac | 502 | struct thread_info *ti = task_thread_info(idle); |
c56e5853 BH |
503 | |
504 | #ifdef CONFIG_PPC64 | |
17e32eac | 505 | paca[cpu].__current = idle; |
c56e5853 BH |
506 | paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; |
507 | #endif | |
508 | ti->cpu = cpu; | |
17e32eac | 509 | secondary_ti = current_set[cpu] = ti; |
c56e5853 BH |
510 | } |
511 | ||
061d19f2 | 512 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 513 | { |
c56e5853 | 514 | int rc, c; |
1da177e4 | 515 | |
512691d4 PM |
516 | /* |
517 | * Don't allow secondary threads to come online if inhibited | |
518 | */ | |
519 | if (threads_per_core > 1 && secondaries_inhibited() && | |
520 | cpu % threads_per_core != 0) | |
521 | return -EBUSY; | |
522 | ||
8cffc6ac BH |
523 | if (smp_ops == NULL || |
524 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
525 | return -EINVAL; |
526 | ||
17e32eac | 527 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 528 | |
1da177e4 LT |
529 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
530 | * hotplug | |
531 | */ | |
532 | cpu_callin_map[cpu] = 0; | |
533 | ||
534 | /* The information for processor bringup must | |
535 | * be written out to main store before we release | |
536 | * the processor. | |
537 | */ | |
0d8d4d42 | 538 | smp_mb(); |
1da177e4 LT |
539 | |
540 | /* wake up cpus */ | |
541 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
542 | rc = smp_ops->kick_cpu(cpu); |
543 | if (rc) { | |
544 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
545 | return rc; | |
546 | } | |
1da177e4 LT |
547 | |
548 | /* | |
549 | * wait to see if the cpu made a callin (is actually up). | |
550 | * use this value that I found through experimentation. | |
551 | * -- Cort | |
552 | */ | |
553 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 554 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
555 | udelay(100); |
556 | #ifdef CONFIG_HOTPLUG_CPU | |
557 | else | |
558 | /* | |
559 | * CPUs can take much longer to come up in the | |
560 | * hotplug case. Wait five seconds. | |
561 | */ | |
67764263 GS |
562 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
563 | msleep(1); | |
1da177e4 LT |
564 | #endif |
565 | ||
566 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 567 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
568 | return -ENOENT; |
569 | } | |
570 | ||
6685a477 | 571 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
572 | |
573 | if (smp_ops->give_timebase) | |
574 | smp_ops->give_timebase(); | |
575 | ||
576 | /* Wait until cpu puts itself in the online map */ | |
577 | while (!cpu_online(cpu)) | |
578 | cpu_relax(); | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
e9efed3b NL |
583 | /* Return the value of the reg property corresponding to the given |
584 | * logical cpu. | |
585 | */ | |
586 | int cpu_to_core_id(int cpu) | |
587 | { | |
588 | struct device_node *np; | |
f8a1883a | 589 | const __be32 *reg; |
e9efed3b NL |
590 | int id = -1; |
591 | ||
592 | np = of_get_cpu_node(cpu, NULL); | |
593 | if (!np) | |
594 | goto out; | |
595 | ||
596 | reg = of_get_property(np, "reg", NULL); | |
597 | if (!reg) | |
598 | goto out; | |
599 | ||
f8a1883a | 600 | id = be32_to_cpup(reg); |
e9efed3b NL |
601 | out: |
602 | of_node_put(np); | |
603 | return id; | |
604 | } | |
605 | ||
99d86705 VS |
606 | /* Helper routines for cpu to core mapping */ |
607 | int cpu_core_index_of_thread(int cpu) | |
608 | { | |
609 | return cpu >> threads_shift; | |
610 | } | |
611 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
612 | ||
613 | int cpu_first_thread_of_core(int core) | |
614 | { | |
615 | return core << threads_shift; | |
616 | } | |
617 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
618 | ||
256f2d4b PM |
619 | static void traverse_siblings_chip_id(int cpu, bool add, int chipid) |
620 | { | |
621 | const struct cpumask *mask; | |
622 | struct device_node *np; | |
623 | int i, plen; | |
624 | const __be32 *prop; | |
625 | ||
626 | mask = add ? cpu_online_mask : cpu_present_mask; | |
627 | for_each_cpu(i, mask) { | |
628 | np = of_get_cpu_node(i, NULL); | |
629 | if (!np) | |
630 | continue; | |
631 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
632 | if (prop && plen == sizeof(int) && | |
633 | of_read_number(prop, 1) == chipid) { | |
634 | if (add) { | |
635 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
636 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
637 | } else { | |
638 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
639 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
640 | } | |
641 | } | |
642 | of_node_put(np); | |
643 | } | |
644 | } | |
645 | ||
104699c0 | 646 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
647 | * i.e. during cpu online or offline. |
648 | */ | |
649 | static struct device_node *cpu_to_l2cache(int cpu) | |
650 | { | |
651 | struct device_node *np; | |
b2ea25b9 | 652 | struct device_node *cache; |
440a0857 NL |
653 | |
654 | if (!cpu_present(cpu)) | |
655 | return NULL; | |
656 | ||
657 | np = of_get_cpu_node(cpu, NULL); | |
658 | if (np == NULL) | |
659 | return NULL; | |
660 | ||
b2ea25b9 NL |
661 | cache = of_find_next_cache_node(np); |
662 | ||
440a0857 NL |
663 | of_node_put(np); |
664 | ||
b2ea25b9 | 665 | return cache; |
440a0857 | 666 | } |
1da177e4 | 667 | |
a8a5356c PM |
668 | static void traverse_core_siblings(int cpu, bool add) |
669 | { | |
256f2d4b | 670 | struct device_node *l2_cache, *np; |
a8a5356c | 671 | const struct cpumask *mask; |
256f2d4b PM |
672 | int i, chip, plen; |
673 | const __be32 *prop; | |
674 | ||
675 | /* First see if we have ibm,chip-id properties in cpu nodes */ | |
676 | np = of_get_cpu_node(cpu, NULL); | |
677 | if (np) { | |
678 | chip = -1; | |
679 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
680 | if (prop && plen == sizeof(int)) | |
681 | chip = of_read_number(prop, 1); | |
682 | of_node_put(np); | |
683 | if (chip >= 0) { | |
684 | traverse_siblings_chip_id(cpu, add, chip); | |
685 | return; | |
686 | } | |
687 | } | |
a8a5356c PM |
688 | |
689 | l2_cache = cpu_to_l2cache(cpu); | |
690 | mask = add ? cpu_online_mask : cpu_present_mask; | |
691 | for_each_cpu(i, mask) { | |
256f2d4b | 692 | np = cpu_to_l2cache(i); |
a8a5356c PM |
693 | if (!np) |
694 | continue; | |
695 | if (np == l2_cache) { | |
696 | if (add) { | |
697 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
698 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
699 | } else { | |
700 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
701 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
702 | } | |
703 | } | |
704 | of_node_put(np); | |
705 | } | |
706 | of_node_put(l2_cache); | |
707 | } | |
708 | ||
1da177e4 | 709 | /* Activate a secondary processor. */ |
061d19f2 | 710 | void start_secondary(void *unused) |
1da177e4 LT |
711 | { |
712 | unsigned int cpu = smp_processor_id(); | |
e2075f79 | 713 | int i, base; |
1da177e4 LT |
714 | |
715 | atomic_inc(&init_mm.mm_count); | |
716 | current->active_mm = &init_mm; | |
717 | ||
718 | smp_store_cpu_info(cpu); | |
5ad57078 | 719 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 720 | preempt_disable(); |
1da177e4 LT |
721 | cpu_callin_map[cpu] = 1; |
722 | ||
757cbd46 KG |
723 | if (smp_ops->setup_cpu) |
724 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
725 | if (smp_ops->take_timebase) |
726 | smp_ops->take_timebase(); | |
727 | ||
d831d0b8 TB |
728 | secondary_cpu_time_init(); |
729 | ||
aeeafbfa BH |
730 | #ifdef CONFIG_PPC64 |
731 | if (system_state == SYSTEM_RUNNING) | |
732 | vdso_data->processorCount++; | |
18ad51dd AB |
733 | |
734 | vdso_getcpu_init(); | |
aeeafbfa | 735 | #endif |
e2075f79 | 736 | /* Update sibling maps */ |
99d86705 | 737 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 738 | for (i = 0; i < threads_per_core; i++) { |
cce606fe | 739 | if (cpu_is_offline(base + i) && (cpu != base + i)) |
e2075f79 | 740 | continue; |
cc1ba8ea AB |
741 | cpumask_set_cpu(cpu, cpu_sibling_mask(base + i)); |
742 | cpumask_set_cpu(base + i, cpu_sibling_mask(cpu)); | |
440a0857 NL |
743 | |
744 | /* cpu_core_map should be a superset of | |
745 | * cpu_sibling_map even if we don't have cache | |
746 | * information, so update the former here, too. | |
747 | */ | |
cc1ba8ea AB |
748 | cpumask_set_cpu(cpu, cpu_core_mask(base + i)); |
749 | cpumask_set_cpu(base + i, cpu_core_mask(cpu)); | |
e2075f79 | 750 | } |
a8a5356c | 751 | traverse_core_siblings(cpu, true); |
1da177e4 | 752 | |
cce606fe LZ |
753 | smp_wmb(); |
754 | notify_cpu_starting(cpu); | |
755 | set_cpu_online(cpu, true); | |
756 | ||
1da177e4 LT |
757 | local_irq_enable(); |
758 | ||
799fef06 | 759 | cpu_startup_entry(CPUHP_ONLINE); |
fa3f82c8 BH |
760 | |
761 | BUG(); | |
1da177e4 LT |
762 | } |
763 | ||
764 | int setup_profiling_timer(unsigned int multiplier) | |
765 | { | |
766 | return 0; | |
767 | } | |
768 | ||
607b45e9 VG |
769 | #ifdef CONFIG_SCHED_SMT |
770 | /* cpumask of CPUs with asymetric SMT dependancy */ | |
771 | static const int powerpc_smt_flags(void) | |
772 | { | |
773 | int flags = SD_SHARE_CPUPOWER | SD_SHARE_PKG_RESOURCES; | |
774 | ||
775 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
776 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
777 | flags |= SD_ASYM_PACKING; | |
778 | } | |
779 | return flags; | |
780 | } | |
781 | #endif | |
782 | ||
783 | static struct sched_domain_topology_level powerpc_topology[] = { | |
784 | #ifdef CONFIG_SCHED_SMT | |
785 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
786 | #endif | |
787 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
788 | { NULL, }, | |
789 | }; | |
790 | ||
1da177e4 LT |
791 | void __init smp_cpus_done(unsigned int max_cpus) |
792 | { | |
bfb9126d | 793 | cpumask_var_t old_mask; |
1da177e4 LT |
794 | |
795 | /* We want the setup_cpu() here to be called from CPU 0, but our | |
796 | * init thread may have been "borrowed" by another CPU in the meantime | |
797 | * se we pin us down to CPU 0 for a short while | |
798 | */ | |
bfb9126d | 799 | alloc_cpumask_var(&old_mask, GFP_NOWAIT); |
104699c0 | 800 | cpumask_copy(old_mask, tsk_cpus_allowed(current)); |
21dbeb91 | 801 | set_cpus_allowed_ptr(current, cpumask_of(boot_cpuid)); |
1da177e4 | 802 | |
757cbd46 | 803 | if (smp_ops && smp_ops->setup_cpu) |
8cffc6ac | 804 | smp_ops->setup_cpu(boot_cpuid); |
1da177e4 | 805 | |
bfb9126d AB |
806 | set_cpus_allowed_ptr(current, old_mask); |
807 | ||
808 | free_cpumask_var(old_mask); | |
4b703a23 | 809 | |
d7294445 BH |
810 | if (smp_ops && smp_ops->bringup_done) |
811 | smp_ops->bringup_done(); | |
812 | ||
4b703a23 | 813 | dump_numa_cpu_topology(); |
d7294445 | 814 | |
607b45e9 | 815 | set_sched_topology(powerpc_topology); |
1da177e4 | 816 | |
e1f0ece1 MN |
817 | } |
818 | ||
1da177e4 LT |
819 | #ifdef CONFIG_HOTPLUG_CPU |
820 | int __cpu_disable(void) | |
821 | { | |
e2075f79 NL |
822 | int cpu = smp_processor_id(); |
823 | int base, i; | |
824 | int err; | |
1da177e4 | 825 | |
e2075f79 NL |
826 | if (!smp_ops->cpu_disable) |
827 | return -ENOSYS; | |
828 | ||
829 | err = smp_ops->cpu_disable(); | |
830 | if (err) | |
831 | return err; | |
832 | ||
833 | /* Update sibling maps */ | |
99d86705 | 834 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 835 | for (i = 0; i < threads_per_core; i++) { |
cc1ba8ea AB |
836 | cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); |
837 | cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); | |
838 | cpumask_clear_cpu(cpu, cpu_core_mask(base + i)); | |
839 | cpumask_clear_cpu(base + i, cpu_core_mask(cpu)); | |
440a0857 | 840 | } |
a8a5356c | 841 | traverse_core_siblings(cpu, false); |
e2075f79 NL |
842 | |
843 | return 0; | |
1da177e4 LT |
844 | } |
845 | ||
846 | void __cpu_die(unsigned int cpu) | |
847 | { | |
848 | if (smp_ops->cpu_die) | |
849 | smp_ops->cpu_die(cpu); | |
850 | } | |
d0174c72 | 851 | |
abb17f9c MM |
852 | void cpu_die(void) |
853 | { | |
854 | if (ppc_md.cpu_die) | |
855 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
856 | |
857 | /* If we return, we re-enter start_secondary */ | |
858 | start_secondary_resume(); | |
abb17f9c | 859 | } |
fa3f82c8 | 860 | |
1da177e4 | 861 | #endif |