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[PATCH] powerpc: Consolidate asm compatibility macros
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
17#include <linux/config.h>
18#include <linux/errno.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
8dad3f92 24#include <linux/ptrace.h>
14cf11af
PM		 25#include <linux/slab.h>
26#include <linux/user.h>
27#include <linux/a.out.h>
28#include <linux/interrupt.h>
14cf11af
PM		 29#include <linux/init.h>
30#include <linux/module.h>
8dad3f92 31#include <linux/prctl.h>
14cf11af
PM		 32#include <linux/delay.h>
33#include <linux/kprobes.h>
14cf11af 34
86417780 35#include <asm/kdebug.h>
14cf11af
PM		 36#include <asm/pgtable.h>
37#include <asm/uaccess.h>
38#include <asm/system.h>
39#include <asm/io.h>
86417780
PM		 40#include <asm/machdep.h>
41#include <asm/rtas.h>
f7f6f4fe 42#include <asm/pmc.h>
dc1c1ca3 43#ifdef CONFIG_PPC32
14cf11af 44#include <asm/reg.h>
86417780 45#endif
14cf11af
PM		 46#ifdef CONFIG_PMAC_BACKLIGHT
47#include <asm/backlight.h>
48#endif
dc1c1ca3 49#ifdef CONFIG_PPC64
86417780 50#include <asm/firmware.h>
dc1c1ca3 51#include <asm/processor.h>
dc1c1ca3 52#include <asm/systemcfg.h>
dc1c1ca3
SR		 53#endif
54
86417780
PM		 55#ifdef CONFIG_PPC64 /* XXX */
56#define _IO_BASE pci_io_base
57#endif
58
14cf11af
PM		 59#ifdef CONFIG_DEBUGGER
60int (*__debugger)(struct pt_regs *regs);
61int (*__debugger_ipi)(struct pt_regs *regs);
62int (*__debugger_bpt)(struct pt_regs *regs);
63int (*__debugger_sstep)(struct pt_regs *regs);
64int (*__debugger_iabr_match)(struct pt_regs *regs);
65int (*__debugger_dabr_match)(struct pt_regs *regs);
66int (*__debugger_fault_handler)(struct pt_regs *regs);
67
68EXPORT_SYMBOL(__debugger);
69EXPORT_SYMBOL(__debugger_ipi);
70EXPORT_SYMBOL(__debugger_bpt);
71EXPORT_SYMBOL(__debugger_sstep);
72EXPORT_SYMBOL(__debugger_iabr_match);
73EXPORT_SYMBOL(__debugger_dabr_match);
74EXPORT_SYMBOL(__debugger_fault_handler);
75#endif
76
77struct notifier_block *powerpc_die_chain;
78static DEFINE_SPINLOCK(die_notifier_lock);
79
80int register_die_notifier(struct notifier_block *nb)
81{
82 int err = 0;
83 unsigned long flags;
84
85 spin_lock_irqsave(&die_notifier_lock, flags);
86 err = notifier_chain_register(&powerpc_die_chain, nb);
87 spin_unlock_irqrestore(&die_notifier_lock, flags);
88 return err;
89}
90
91/*
92 * Trap & Exception support
93 */
94
95static DEFINE_SPINLOCK(die_lock);
96
97int die(const char *str, struct pt_regs *regs, long err)
98{
99 static int die_counter;
100 int nl = 0;
101
102 if (debugger(regs))
103 return 1;
104
105 console_verbose();
106 spin_lock_irq(&die_lock);
107 bust_spinlocks(1);
8dad3f92 108#ifdef CONFIG_PMAC_BACKLIGHT
14cf11af
PM		 109 if (_machine == _MACH_Pmac) {
110 set_backlight_enable(1);
111 set_backlight_level(BACKLIGHT_MAX);
112 }
113#endif
114 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
115#ifdef CONFIG_PREEMPT
116 printk("PREEMPT ");
117 nl = 1;
118#endif
119#ifdef CONFIG_SMP
120 printk("SMP NR_CPUS=%d ", NR_CPUS);
121 nl = 1;
122#endif
123#ifdef CONFIG_DEBUG_PAGEALLOC
124 printk("DEBUG_PAGEALLOC ");
125 nl = 1;
126#endif
127#ifdef CONFIG_NUMA
128 printk("NUMA ");
129 nl = 1;
130#endif
131#ifdef CONFIG_PPC64
132 switch (systemcfg->platform) {
133 case PLATFORM_PSERIES:
134 printk("PSERIES ");
135 nl = 1;
136 break;
137 case PLATFORM_PSERIES_LPAR:
138 printk("PSERIES LPAR ");
139 nl = 1;
140 break;
141 case PLATFORM_ISERIES_LPAR:
142 printk("ISERIES LPAR ");
143 nl = 1;
144 break;
145 case PLATFORM_POWERMAC:
146 printk("POWERMAC ");
147 nl = 1;
148 break;
f3f66f59
AB		 149 case PLATFORM_CELL:
150 printk("CELL ");
14cf11af
PM		 151 nl = 1;
152 break;
153 }
154#endif
155 if (nl)
156 printk("\n");
157 print_modules();
158 show_regs(regs);
159 bust_spinlocks(0);
160 spin_unlock_irq(&die_lock);
161
162 if (in_interrupt())
163 panic("Fatal exception in interrupt");
164
165 if (panic_on_oops) {
dc1c1ca3
SR		 166#ifdef CONFIG_PPC64
167 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
168 ssleep(5);
169#endif
14cf11af
PM		 170 panic("Fatal exception");
171 }
172 do_exit(err);
173
174 return 0;
175}
176
177void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
178{
179 siginfo_t info;
180
181 if (!user_mode(regs)) {
182 if (die("Exception in kernel mode", regs, signr))
183 return;
184 }
185
186 memset(&info, 0, sizeof(info));
187 info.si_signo = signr;
188 info.si_code = code;
189 info.si_addr = (void __user *) addr;
190 force_sig_info(signr, &info, current);
191
192 /*
193 * Init gets no signals that it doesn't have a handler for.
194 * That's all very well, but if it has caused a synchronous
195 * exception and we ignore the resulting signal, it will just
196 * generate the same exception over and over again and we get
197 * nowhere. Better to kill it and let the kernel panic.
198 */
199 if (current->pid == 1) {
200 __sighandler_t handler;
201
202 spin_lock_irq(&current->sighand->siglock);
203 handler = current->sighand->action[signr-1].sa.sa_handler;
204 spin_unlock_irq(&current->sighand->siglock);
205 if (handler == SIG_DFL) {
206 /* init has generated a synchronous exception
207 and it doesn't have a handler for the signal */
208 printk(KERN_CRIT "init has generated signal %d "
209 "but has no handler for it\n", signr);
210 do_exit(signr);
211 }
212 }
213}
214
215#ifdef CONFIG_PPC64
216void system_reset_exception(struct pt_regs *regs)
217{
218 /* See if any machine dependent calls */
219 if (ppc_md.system_reset_exception)
220 ppc_md.system_reset_exception(regs);
221
8dad3f92 222 die("System Reset", regs, SIGABRT);
14cf11af
PM		 223
224 /* Must die if the interrupt is not recoverable */
225 if (!(regs->msr & MSR_RI))
226 panic("Unrecoverable System Reset");
227
228 /* What should we do here? We could issue a shutdown or hard reset. */
229}
230#endif
231
232/*
233 * I/O accesses can cause machine checks on powermacs.
234 * Check if the NIP corresponds to the address of a sync
235 * instruction for which there is an entry in the exception
236 * table.
237 * Note that the 601 only takes a machine check on TEA
238 * (transfer error ack) signal assertion, and does not
239 * set any of the top 16 bits of SRR1.
240 * -- paulus.
241 */
242static inline int check_io_access(struct pt_regs *regs)
243{
244#ifdef CONFIG_PPC_PMAC
245 unsigned long msr = regs->msr;
246 const struct exception_table_entry *entry;
247 unsigned int *nip = (unsigned int *)regs->nip;
248
249 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
250 && (entry = search_exception_tables(regs->nip)) != NULL) {
251 /*
252 * Check that it's a sync instruction, or somewhere
253 * in the twi; isync; nop sequence that inb/inw/inl uses.
254 * As the address is in the exception table
255 * we should be able to read the instr there.
256 * For the debug message, we look at the preceding
257 * load or store.
258 */
259 if (*nip == 0x60000000) /* nop */
260 nip -= 2;
261 else if (*nip == 0x4c00012c) /* isync */
262 --nip;
263 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
264 /* sync or twi */
265 unsigned int rb;
266
267 --nip;
268 rb = (*nip >> 11) & 0x1f;
269 printk(KERN_DEBUG "%s bad port %lx at %p\n",
270 (*nip & 0x100)? "OUT to": "IN from",
271 regs->gpr[rb] - _IO_BASE, nip);
272 regs->msr |= MSR_RI;
273 regs->nip = entry->fixup;
274 return 1;
275 }
276 }
277#endif /* CONFIG_PPC_PMAC */
278 return 0;
279}
280
281#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
282/* On 4xx, the reason for the machine check or program exception
283 is in the ESR. */
284#define get_reason(regs) ((regs)->dsisr)
285#ifndef CONFIG_FSL_BOOKE
286#define get_mc_reason(regs) ((regs)->dsisr)
287#else
288#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
289#endif
290#define REASON_FP ESR_FP
291#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
292#define REASON_PRIVILEGED ESR_PPR
293#define REASON_TRAP ESR_PTR
294
295/* single-step stuff */
296#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
297#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
298
299#else
300/* On non-4xx, the reason for the machine check or program
301 exception is in the MSR. */
302#define get_reason(regs) ((regs)->msr)
303#define get_mc_reason(regs) ((regs)->msr)
304#define REASON_FP 0x100000
305#define REASON_ILLEGAL 0x80000
306#define REASON_PRIVILEGED 0x40000
307#define REASON_TRAP 0x20000
308
309#define single_stepping(regs) ((regs)->msr & MSR_SE)
310#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
311#endif
312
313/*
314 * This is "fall-back" implementation for configurations
315 * which don't provide platform-specific machine check info
316 */
317void __attribute__ ((weak))
318platform_machine_check(struct pt_regs *regs)
319{
320}
321
dc1c1ca3 322void machine_check_exception(struct pt_regs *regs)
14cf11af
PM		 323{
324#ifdef CONFIG_PPC64
325 int recover = 0;
326
327 /* See if any machine dependent calls */
328 if (ppc_md.machine_check_exception)
329 recover = ppc_md.machine_check_exception(regs);
330
331 if (recover)
332 return;
333#else
334 unsigned long reason = get_mc_reason(regs);
335
336 if (user_mode(regs)) {
337 regs->msr |= MSR_RI;
338 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
339 return;
340 }
341
342#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
343 /* the qspan pci read routines can cause machine checks -- Cort */
344 bad_page_fault(regs, regs->dar, SIGBUS);
345 return;
346#endif
347
348 if (debugger_fault_handler(regs)) {
349 regs->msr |= MSR_RI;
350 return;
351 }
352
353 if (check_io_access(regs))
354 return;
355
356#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
357 if (reason & ESR_IMCP) {
358 printk("Instruction");
359 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
360 } else
361 printk("Data");
362 printk(" machine check in kernel mode.\n");
363#elif defined(CONFIG_440A)
364 printk("Machine check in kernel mode.\n");
365 if (reason & ESR_IMCP){
366 printk("Instruction Synchronous Machine Check exception\n");
367 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
368 }
369 else {
370 u32 mcsr = mfspr(SPRN_MCSR);
371 if (mcsr & MCSR_IB)
372 printk("Instruction Read PLB Error\n");
373 if (mcsr & MCSR_DRB)
374 printk("Data Read PLB Error\n");
375 if (mcsr & MCSR_DWB)
376 printk("Data Write PLB Error\n");
377 if (mcsr & MCSR_TLBP)
378 printk("TLB Parity Error\n");
379 if (mcsr & MCSR_ICP){
380 flush_instruction_cache();
381 printk("I-Cache Parity Error\n");
382 }
383 if (mcsr & MCSR_DCSP)
384 printk("D-Cache Search Parity Error\n");
385 if (mcsr & MCSR_DCFP)
386 printk("D-Cache Flush Parity Error\n");
387 if (mcsr & MCSR_IMPE)
388 printk("Machine Check exception is imprecise\n");
389
390 /* Clear MCSR */
391 mtspr(SPRN_MCSR, mcsr);
392 }
393#elif defined (CONFIG_E500)
394 printk("Machine check in kernel mode.\n");
395 printk("Caused by (from MCSR=%lx): ", reason);
396
397 if (reason & MCSR_MCP)
398 printk("Machine Check Signal\n");
399 if (reason & MCSR_ICPERR)
400 printk("Instruction Cache Parity Error\n");
401 if (reason & MCSR_DCP_PERR)
402 printk("Data Cache Push Parity Error\n");
403 if (reason & MCSR_DCPERR)
404 printk("Data Cache Parity Error\n");
405 if (reason & MCSR_GL_CI)
406 printk("Guarded Load or Cache-Inhibited stwcx.\n");
407 if (reason & MCSR_BUS_IAERR)
408 printk("Bus - Instruction Address Error\n");
409 if (reason & MCSR_BUS_RAERR)
410 printk("Bus - Read Address Error\n");
411 if (reason & MCSR_BUS_WAERR)
412 printk("Bus - Write Address Error\n");
413 if (reason & MCSR_BUS_IBERR)
414 printk("Bus - Instruction Data Error\n");
415 if (reason & MCSR_BUS_RBERR)
416 printk("Bus - Read Data Bus Error\n");
417 if (reason & MCSR_BUS_WBERR)
418 printk("Bus - Read Data Bus Error\n");
419 if (reason & MCSR_BUS_IPERR)
420 printk("Bus - Instruction Parity Error\n");
421 if (reason & MCSR_BUS_RPERR)
422 printk("Bus - Read Parity Error\n");
423#elif defined (CONFIG_E200)
424 printk("Machine check in kernel mode.\n");
425 printk("Caused by (from MCSR=%lx): ", reason);
426
427 if (reason & MCSR_MCP)
428 printk("Machine Check Signal\n");
429 if (reason & MCSR_CP_PERR)
430 printk("Cache Push Parity Error\n");
431 if (reason & MCSR_CPERR)
432 printk("Cache Parity Error\n");
433 if (reason & MCSR_EXCP_ERR)
434 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
435 if (reason & MCSR_BUS_IRERR)
436 printk("Bus - Read Bus Error on instruction fetch\n");
437 if (reason & MCSR_BUS_DRERR)
438 printk("Bus - Read Bus Error on data load\n");
439 if (reason & MCSR_BUS_WRERR)
440 printk("Bus - Write Bus Error on buffered store or cache line push\n");
441#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
442 printk("Machine check in kernel mode.\n");
443 printk("Caused by (from SRR1=%lx): ", reason);
444 switch (reason & 0x601F0000) {
445 case 0x80000:
446 printk("Machine check signal\n");
447 break;
448 case 0: /* for 601 */
449 case 0x40000:
450 case 0x140000: /* 7450 MSS error and TEA */
451 printk("Transfer error ack signal\n");
452 break;
453 case 0x20000:
454 printk("Data parity error signal\n");
455 break;
456 case 0x10000:
457 printk("Address parity error signal\n");
458 break;
459 case 0x20000000:
460 printk("L1 Data Cache error\n");
461 break;
462 case 0x40000000:
463 printk("L1 Instruction Cache error\n");
464 break;
465 case 0x00100000:
466 printk("L2 data cache parity error\n");
467 break;
468 default:
469 printk("Unknown values in msr\n");
470 }
471#endif /* CONFIG_4xx */
472
473 /*
474 * Optional platform-provided routine to print out
475 * additional info, e.g. bus error registers.
476 */
477 platform_machine_check(regs);
86417780 478#endif /* CONFIG_PPC64 */
14cf11af
PM		 479
480 if (debugger_fault_handler(regs))
481 return;
8dad3f92 482 die("Machine check", regs, SIGBUS);
14cf11af
PM		 483
484 /* Must die if the interrupt is not recoverable */
485 if (!(regs->msr & MSR_RI))
486 panic("Unrecoverable Machine check");
487}
488
489void SMIException(struct pt_regs *regs)
490{
491 die("System Management Interrupt", regs, SIGABRT);
492}
493
dc1c1ca3 494void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 495{
496 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
497 regs->nip, regs->msr, regs->trap);
498
499 _exception(SIGTRAP, regs, 0, 0);
500}
501
dc1c1ca3 502void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 503{
504 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
505 5, SIGTRAP) == NOTIFY_STOP)
506 return;
507 if (debugger_iabr_match(regs))
508 return;
509 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
510}
511
512void RunModeException(struct pt_regs *regs)
513{
514 _exception(SIGTRAP, regs, 0, 0);
515}
516
8dad3f92 517void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af
PM		 518{
519 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
520
521 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
522 5, SIGTRAP) == NOTIFY_STOP)
523 return;
524 if (debugger_sstep(regs))
525 return;
526
527 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
528}
529
530/*
531 * After we have successfully emulated an instruction, we have to
532 * check if the instruction was being single-stepped, and if so,
533 * pretend we got a single-step exception. This was pointed out
534 * by Kumar Gala. -- paulus
535 */
8dad3f92 536static void emulate_single_step(struct pt_regs *regs)
14cf11af
PM		 537{
538 if (single_stepping(regs)) {
539 clear_single_step(regs);
540 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
541 }
542}
543
dc1c1ca3
SR		 544static void parse_fpe(struct pt_regs *regs)
545{
546 int code = 0;
547 unsigned long fpscr;
548
dc1c1ca3 549 flush_fp_to_thread(current);
dc1c1ca3 550
25c8a78b 551 fpscr = current->thread.fpscr.val;
dc1c1ca3
SR		 552
553 /* Invalid operation */
554 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
555 code = FPE_FLTINV;
556
557 /* Overflow */
558 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
559 code = FPE_FLTOVF;
560
561 /* Underflow */
562 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
563 code = FPE_FLTUND;
564
565 /* Divide by zero */
566 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
567 code = FPE_FLTDIV;
568
569 /* Inexact result */
570 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
571 code = FPE_FLTRES;
572
573 _exception(SIGFPE, regs, code, regs->nip);
574}
575
576/*
577 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 578 * provide the PVR to user applications using the mfspr rd, PVR.
579 * Return non-zero if we can't emulate, or -EFAULT if the associated
580 * memory access caused an access fault. Return zero on success.
581 *
582 * There are a couple of ways to do this, either "decode" the instruction
583 * or directly match lots of bits. In this case, matching lots of
584 * bits is faster and easier.
86417780 585 *
14cf11af
PM		 586 */
587#define INST_MFSPR_PVR 0x7c1f42a6
588#define INST_MFSPR_PVR_MASK 0xfc1fffff
589
590#define INST_DCBA 0x7c0005ec
591#define INST_DCBA_MASK 0x7c0007fe
592
593#define INST_MCRXR 0x7c000400
594#define INST_MCRXR_MASK 0x7c0007fe
595
596#define INST_STRING 0x7c00042a
597#define INST_STRING_MASK 0x7c0007fe
598#define INST_STRING_GEN_MASK 0x7c00067e
599#define INST_LSWI 0x7c0004aa
600#define INST_LSWX 0x7c00042a
601#define INST_STSWI 0x7c0005aa
602#define INST_STSWX 0x7c00052a
603
604static int emulate_string_inst(struct pt_regs *regs, u32 instword)
605{
606 u8 rT = (instword >> 21) & 0x1f;
607 u8 rA = (instword >> 16) & 0x1f;
608 u8 NB_RB = (instword >> 11) & 0x1f;
609 u32 num_bytes;
610 unsigned long EA;
611 int pos = 0;
612
613 /* Early out if we are an invalid form of lswx */
614 if ((instword & INST_STRING_MASK) == INST_LSWX)
615 if ((rT == rA) || (rT == NB_RB))
616 return -EINVAL;
617
618 EA = (rA == 0) ? 0 : regs->gpr[rA];
619
620 switch (instword & INST_STRING_MASK) {
621 case INST_LSWX:
622 case INST_STSWX:
623 EA += NB_RB;
624 num_bytes = regs->xer & 0x7f;
625 break;
626 case INST_LSWI:
627 case INST_STSWI:
628 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
629 break;
630 default:
631 return -EINVAL;
632 }
633
634 while (num_bytes != 0)
635 {
636 u8 val;
637 u32 shift = 8 * (3 - (pos & 0x3));
638
639 switch ((instword & INST_STRING_MASK)) {
640 case INST_LSWX:
641 case INST_LSWI:
642 if (get_user(val, (u8 __user *)EA))
643 return -EFAULT;
644 /* first time updating this reg,
645 * zero it out */
646 if (pos == 0)
647 regs->gpr[rT] = 0;
648 regs->gpr[rT] |= val << shift;
649 break;
650 case INST_STSWI:
651 case INST_STSWX:
652 val = regs->gpr[rT] >> shift;
653 if (put_user(val, (u8 __user *)EA))
654 return -EFAULT;
655 break;
656 }
657 /* move EA to next address */
658 EA += 1;
659 num_bytes--;
660
661 /* manage our position within the register */
662 if (++pos == 4) {
663 pos = 0;
664 if (++rT == 32)
665 rT = 0;
666 }
667 }
668
669 return 0;
670}
671
672static int emulate_instruction(struct pt_regs *regs)
673{
674 u32 instword;
675 u32 rd;
676
677 if (!user_mode(regs))
678 return -EINVAL;
679 CHECK_FULL_REGS(regs);
680
681 if (get_user(instword, (u32 __user *)(regs->nip)))
682 return -EFAULT;
683
684 /* Emulate the mfspr rD, PVR. */
685 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
686 rd = (instword >> 21) & 0x1f;
687 regs->gpr[rd] = mfspr(SPRN_PVR);
688 return 0;
689 }
690
691 /* Emulating the dcba insn is just a no-op. */
8dad3f92 692 if ((instword & INST_DCBA_MASK) == INST_DCBA)
14cf11af
PM		 693 return 0;
694
695 /* Emulate the mcrxr insn. */
696 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
86417780 697 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 698 unsigned long msk = 0xf0000000UL >> shift;
699
700 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
701 regs->xer &= ~0xf0000000UL;
702 return 0;
703 }
704
705 /* Emulate load/store string insn. */
706 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
707 return emulate_string_inst(regs, instword);
708
709 return -EINVAL;
710}
711
712/*
713 * Look through the list of trap instructions that are used for BUG(),
714 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know
715 * that the exception was caused by a trap instruction of some kind.
716 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
717 * otherwise.
718 */
719extern struct bug_entry __start___bug_table[], __stop___bug_table[];
720
721#ifndef CONFIG_MODULES
722#define module_find_bug(x) NULL
723#endif
724
725struct bug_entry *find_bug(unsigned long bugaddr)
726{
727 struct bug_entry *bug;
728
729 for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
730 if (bugaddr == bug->bug_addr)
731 return bug;
732 return module_find_bug(bugaddr);
733}
734
dc1c1ca3 735static int check_bug_trap(struct pt_regs *regs)
14cf11af
PM		 736{
737 struct bug_entry *bug;
738 unsigned long addr;
739
740 if (regs->msr & MSR_PR)
741 return 0; /* not in kernel */
742 addr = regs->nip; /* address of trap instruction */
743 if (addr < PAGE_OFFSET)
744 return 0;
745 bug = find_bug(regs->nip);
746 if (bug == NULL)
747 return 0;
748 if (bug->line & BUG_WARNING_TRAP) {
749 /* this is a WARN_ON rather than BUG/BUG_ON */
104dd65f 750 printk(KERN_ERR "Badness in %s at %s:%ld\n",
14cf11af
PM		 751 bug->function, bug->file,
752 bug->line & ~BUG_WARNING_TRAP);
753 dump_stack();
754 return 1;
755 }
104dd65f 756 printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
14cf11af
PM		 757 bug->function, bug->file, bug->line);
758
759 return 0;
760}
761
8dad3f92 762void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 763{
764 unsigned int reason = get_reason(regs);
765 extern int do_mathemu(struct pt_regs *regs);
766
8dad3f92 767#ifdef CONFIG_MATH_EMULATION
14cf11af
PM		 768 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
769 * but there seems to be a hardware bug on the 405GP (RevD)
770 * that means ESR is sometimes set incorrectly - either to
771 * ESR_DST (!?) or 0. In the process of chasing this with the
772 * hardware people - not sure if it can happen on any illegal
773 * instruction or only on FP instructions, whether there is a
774 * pattern to occurences etc. -dgibson 31/Mar/2003 */
775 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
776 emulate_single_step(regs);
777 return;
778 }
8dad3f92 779#endif /* CONFIG_MATH_EMULATION */
14cf11af 780
dc1c1ca3
SR		 781 if (reason & REASON_FP) {
782 /* IEEE FP exception */
783 parse_fpe(regs);
8dad3f92
PM		 784 return;
785 }
786 if (reason & REASON_TRAP) {
14cf11af 787 /* trap exception */
dc1c1ca3
SR		 788 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
789 == NOTIFY_STOP)
790 return;
14cf11af
PM		 791 if (debugger_bpt(regs))
792 return;
793 if (check_bug_trap(regs)) {
794 regs->nip += 4;
795 return;
796 }
8dad3f92
PM		 797 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
798 return;
799 }
800
801 /* Try to emulate it if we should. */
802 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 803 switch (emulate_instruction(regs)) {
804 case 0:
805 regs->nip += 4;
806 emulate_single_step(regs);
8dad3f92 807 return;
14cf11af
PM		 808 case -EFAULT:
809 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 810 return;
14cf11af
PM		 811 }
812 }
8dad3f92
PM		 813
814 if (reason & REASON_PRIVILEGED)
815 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
816 else
817 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 818}
819
dc1c1ca3 820void alignment_exception(struct pt_regs *regs)
14cf11af
PM		 821{
822 int fixed;
823
824 fixed = fix_alignment(regs);
825
826 if (fixed == 1) {
827 regs->nip += 4; /* skip over emulated instruction */
828 emulate_single_step(regs);
829 return;
830 }
831
dc1c1ca3 832 /* Operand address was bad */
14cf11af
PM		 833 if (fixed == -EFAULT) {
834 if (user_mode(regs))
8dad3f92 835 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
14cf11af
PM		 836 else
837 /* Search exception table */
838 bad_page_fault(regs, regs->dar, SIGSEGV);
839 return;
840 }
8dad3f92 841 _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
14cf11af
PM		 842}
843
844void StackOverflow(struct pt_regs *regs)
845{
846 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
847 current, regs->gpr[1]);
848 debugger(regs);
849 show_regs(regs);
850 panic("kernel stack overflow");
851}
852
853void nonrecoverable_exception(struct pt_regs *regs)
854{
855 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
856 regs->nip, regs->msr);
857 debugger(regs);
858 die("nonrecoverable exception", regs, SIGKILL);
859}
860
861void trace_syscall(struct pt_regs *regs)
862{
863 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
864 current, current->pid, regs->nip, regs->link, regs->gpr[0],
865 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
866}
dc1c1ca3 867
dc1c1ca3
SR		 868void kernel_fp_unavailable_exception(struct pt_regs *regs)
869{
870 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
871 "%lx at %lx\n", regs->trap, regs->nip);
872 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
873}
dc1c1ca3
SR		 874
875void altivec_unavailable_exception(struct pt_regs *regs)
876{
8dad3f92 877#if !defined(CONFIG_ALTIVEC)
dc1c1ca3
SR		 878 if (user_mode(regs)) {
879 /* A user program has executed an altivec instruction,
880 but this kernel doesn't support altivec. */
881 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
882 return;
883 }
884#endif
dc1c1ca3
SR		 885 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
886 "%lx at %lx\n", regs->trap, regs->nip);
887 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 888}
889
dc1c1ca3
SR		 890#if defined(CONFIG_PPC64) || defined(CONFIG_E500)
891void performance_monitor_exception(struct pt_regs *regs)
892{
893 perf_irq(regs);
894}
895#endif
896
8dad3f92 897#ifdef CONFIG_8xx
14cf11af
PM		 898void SoftwareEmulation(struct pt_regs *regs)
899{
900 extern int do_mathemu(struct pt_regs *);
901 extern int Soft_emulate_8xx(struct pt_regs *);
902 int errcode;
903
904 CHECK_FULL_REGS(regs);
905
906 if (!user_mode(regs)) {
907 debugger(regs);
908 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
909 }
910
911#ifdef CONFIG_MATH_EMULATION
912 errcode = do_mathemu(regs);
913#else
914 errcode = Soft_emulate_8xx(regs);
915#endif
916 if (errcode) {
917 if (errcode > 0)
918 _exception(SIGFPE, regs, 0, 0);
919 else if (errcode == -EFAULT)
920 _exception(SIGSEGV, regs, 0, 0);
921 else
922 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
923 } else
924 emulate_single_step(regs);
925}
8dad3f92 926#endif /* CONFIG_8xx */
14cf11af
PM		 927
928#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
929
930void DebugException(struct pt_regs *regs, unsigned long debug_status)
931{
932 if (debug_status & DBSR_IC) { /* instruction completion */
933 regs->msr &= ~MSR_DE;
934 if (user_mode(regs)) {
935 current->thread.dbcr0 &= ~DBCR0_IC;
936 } else {
937 /* Disable instruction completion */
938 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
939 /* Clear the instruction completion event */
940 mtspr(SPRN_DBSR, DBSR_IC);
941 if (debugger_sstep(regs))
942 return;
943 }
944 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
945 }
946}
947#endif /* CONFIG_4xx || CONFIG_BOOKE */
948
949#if !defined(CONFIG_TAU_INT)
950void TAUException(struct pt_regs *regs)
951{
952 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
953 regs->nip, regs->msr, regs->trap, print_tainted());
954}
955#endif /* CONFIG_INT_TAU */
14cf11af
PM		 956
957#ifdef CONFIG_ALTIVEC
dc1c1ca3 958void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 959{
960 int err;
961
14cf11af
PM		 962 if (!user_mode(regs)) {
963 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
964 " at %lx\n", regs->nip);
8dad3f92 965 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 966 }
967
dc1c1ca3 968 flush_altivec_to_thread(current);
dc1c1ca3 969
14cf11af
PM		 970 err = emulate_altivec(regs);
971 if (err == 0) {
972 regs->nip += 4; /* skip emulated instruction */
973 emulate_single_step(regs);
974 return;
975 }
976
977 if (err == -EFAULT) {
978 /* got an error reading the instruction */
979 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
980 } else {
981 /* didn't recognize the instruction */
982 /* XXX quick hack for now: set the non-Java bit in the VSCR */
983 if (printk_ratelimit())
984 printk(KERN_ERR "Unrecognized altivec instruction "
985 "in %s at %lx\n", current->comm, regs->nip);
986 current->thread.vscr.u[3] |= 0x10000;
987 }
988}
989#endif /* CONFIG_ALTIVEC */
990
14cf11af
PM		 991#ifdef CONFIG_FSL_BOOKE
992void CacheLockingException(struct pt_regs *regs, unsigned long address,
993 unsigned long error_code)
994{
995 /* We treat cache locking instructions from the user
996 * as priv ops, in the future we could try to do
997 * something smarter
998 */
999 if (error_code & (ESR_DLK|ESR_ILK))
1000 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1001 return;
1002}
1003#endif /* CONFIG_FSL_BOOKE */
1004
1005#ifdef CONFIG_SPE
1006void SPEFloatingPointException(struct pt_regs *regs)
1007{
1008 unsigned long spefscr;
1009 int fpexc_mode;
1010 int code = 0;
1011
1012 spefscr = current->thread.spefscr;
1013 fpexc_mode = current->thread.fpexc_mode;
1014
1015 /* Hardware does not neccessarily set sticky
1016 * underflow/overflow/invalid flags */
1017 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1018 code = FPE_FLTOVF;
1019 spefscr |= SPEFSCR_FOVFS;
1020 }
1021 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1022 code = FPE_FLTUND;
1023 spefscr |= SPEFSCR_FUNFS;
1024 }
1025 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1026 code = FPE_FLTDIV;
1027 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1028 code = FPE_FLTINV;
1029 spefscr |= SPEFSCR_FINVS;
1030 }
1031 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1032 code = FPE_FLTRES;
1033
1034 current->thread.spefscr = spefscr;
1035
1036 _exception(SIGFPE, regs, code, regs->nip);
1037 return;
1038}
1039#endif
1040
dc1c1ca3
SR		 1041/*
1042 * We enter here if we get an unrecoverable exception, that is, one
1043 * that happened at a point where the RI (recoverable interrupt) bit
1044 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1045 * we therefore lost state by taking this exception.
1046 */
1047void unrecoverable_exception(struct pt_regs *regs)
1048{
1049 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1050 regs->trap, regs->nip);
1051 die("Unrecoverable exception", regs, SIGABRT);
1052}
dc1c1ca3 1053
14cf11af
PM		 1054#ifdef CONFIG_BOOKE_WDT
1055/*
1056 * Default handler for a Watchdog exception,
1057 * spins until a reboot occurs
1058 */
1059void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1060{
1061 /* Generic WatchdogHandler, implement your own */
1062 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1063 return;
1064}
1065
1066void WatchdogException(struct pt_regs *regs)
1067{
1068 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1069 WatchdogHandler(regs);
1070}
1071#endif
dc1c1ca3 1072
dc1c1ca3
SR		 1073/*
1074 * We enter here if we discover during exception entry that we are
1075 * running in supervisor mode with a userspace value in the stack pointer.
1076 */
1077void kernel_bad_stack(struct pt_regs *regs)
1078{
1079 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1080 regs->gpr[1], regs->nip);
1081 die("Bad kernel stack pointer", regs, SIGABRT);
1082}
14cf11af
PM		 1083
1084void __init trap_init(void)
1085{
1086}
Linux kernel - Deliverables
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