Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af PM |
24 | #include <linux/slab.h> |
25 | #include <linux/user.h> | |
26 | #include <linux/a.out.h> | |
27 | #include <linux/interrupt.h> | |
14cf11af PM |
28 | #include <linux/init.h> |
29 | #include <linux/module.h> | |
8dad3f92 | 30 | #include <linux/prctl.h> |
14cf11af PM |
31 | #include <linux/delay.h> |
32 | #include <linux/kprobes.h> | |
cc532915 | 33 | #include <linux/kexec.h> |
5474c120 | 34 | #include <linux/backlight.h> |
73c9ceab | 35 | #include <linux/bug.h> |
14cf11af | 36 | |
86417780 | 37 | #include <asm/kdebug.h> |
14cf11af PM |
38 | #include <asm/pgtable.h> |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/system.h> | |
41 | #include <asm/io.h> | |
86417780 PM |
42 | #include <asm/machdep.h> |
43 | #include <asm/rtas.h> | |
f7f6f4fe | 44 | #include <asm/pmc.h> |
dc1c1ca3 | 45 | #ifdef CONFIG_PPC32 |
14cf11af | 46 | #include <asm/reg.h> |
86417780 | 47 | #endif |
14cf11af PM |
48 | #ifdef CONFIG_PMAC_BACKLIGHT |
49 | #include <asm/backlight.h> | |
50 | #endif | |
dc1c1ca3 | 51 | #ifdef CONFIG_PPC64 |
86417780 | 52 | #include <asm/firmware.h> |
dc1c1ca3 | 53 | #include <asm/processor.h> |
dc1c1ca3 | 54 | #endif |
c0ce7d08 | 55 | #include <asm/kexec.h> |
dc1c1ca3 | 56 | |
14cf11af PM |
57 | #ifdef CONFIG_DEBUGGER |
58 | int (*__debugger)(struct pt_regs *regs); | |
59 | int (*__debugger_ipi)(struct pt_regs *regs); | |
60 | int (*__debugger_bpt)(struct pt_regs *regs); | |
61 | int (*__debugger_sstep)(struct pt_regs *regs); | |
62 | int (*__debugger_iabr_match)(struct pt_regs *regs); | |
63 | int (*__debugger_dabr_match)(struct pt_regs *regs); | |
64 | int (*__debugger_fault_handler)(struct pt_regs *regs); | |
65 | ||
66 | EXPORT_SYMBOL(__debugger); | |
67 | EXPORT_SYMBOL(__debugger_ipi); | |
68 | EXPORT_SYMBOL(__debugger_bpt); | |
69 | EXPORT_SYMBOL(__debugger_sstep); | |
70 | EXPORT_SYMBOL(__debugger_iabr_match); | |
71 | EXPORT_SYMBOL(__debugger_dabr_match); | |
72 | EXPORT_SYMBOL(__debugger_fault_handler); | |
73 | #endif | |
74 | ||
e041c683 | 75 | ATOMIC_NOTIFIER_HEAD(powerpc_die_chain); |
14cf11af PM |
76 | |
77 | int register_die_notifier(struct notifier_block *nb) | |
78 | { | |
e041c683 AS |
79 | return atomic_notifier_chain_register(&powerpc_die_chain, nb); |
80 | } | |
81 | EXPORT_SYMBOL(register_die_notifier); | |
14cf11af | 82 | |
e041c683 AS |
83 | int unregister_die_notifier(struct notifier_block *nb) |
84 | { | |
85 | return atomic_notifier_chain_unregister(&powerpc_die_chain, nb); | |
14cf11af | 86 | } |
e041c683 | 87 | EXPORT_SYMBOL(unregister_die_notifier); |
14cf11af PM |
88 | |
89 | /* | |
90 | * Trap & Exception support | |
91 | */ | |
92 | ||
93 | static DEFINE_SPINLOCK(die_lock); | |
94 | ||
95 | int die(const char *str, struct pt_regs *regs, long err) | |
96 | { | |
c0ce7d08 | 97 | static int die_counter; |
14cf11af PM |
98 | |
99 | if (debugger(regs)) | |
100 | return 1; | |
101 | ||
102 | console_verbose(); | |
103 | spin_lock_irq(&die_lock); | |
104 | bust_spinlocks(1); | |
8dad3f92 | 105 | #ifdef CONFIG_PMAC_BACKLIGHT |
5474c120 MH |
106 | mutex_lock(&pmac_backlight_mutex); |
107 | if (machine_is(powermac) && pmac_backlight) { | |
108 | struct backlight_properties *props; | |
109 | ||
599a52d1 | 110 | props = &pmac_backlight->props; |
5474c120 MH |
111 | props->brightness = props->max_brightness; |
112 | props->power = FB_BLANK_UNBLANK; | |
28ee086d | 113 | backlight_update_status(pmac_backlight); |
14cf11af | 114 | } |
5474c120 | 115 | mutex_unlock(&pmac_backlight_mutex); |
14cf11af PM |
116 | #endif |
117 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
118 | #ifdef CONFIG_PREEMPT | |
119 | printk("PREEMPT "); | |
14cf11af PM |
120 | #endif |
121 | #ifdef CONFIG_SMP | |
122 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
14cf11af PM |
123 | #endif |
124 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
125 | printk("DEBUG_PAGEALLOC "); | |
14cf11af PM |
126 | #endif |
127 | #ifdef CONFIG_NUMA | |
128 | printk("NUMA "); | |
14cf11af | 129 | #endif |
e8222502 BH |
130 | printk("%s\n", ppc_md.name ? "" : ppc_md.name); |
131 | ||
14cf11af PM |
132 | print_modules(); |
133 | show_regs(regs); | |
134 | bust_spinlocks(0); | |
c0ce7d08 | 135 | spin_unlock_irq(&die_lock); |
cc532915 | 136 | |
c0ce7d08 DW |
137 | if (kexec_should_crash(current) || |
138 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 139 | crash_kexec(regs); |
c0ce7d08 | 140 | crash_kexec_secondary(regs); |
14cf11af PM |
141 | |
142 | if (in_interrupt()) | |
143 | panic("Fatal exception in interrupt"); | |
144 | ||
cea6a4ba | 145 | if (panic_on_oops) |
012c437d | 146 | panic("Fatal exception"); |
cea6a4ba | 147 | |
14cf11af PM |
148 | do_exit(err); |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
154 | { | |
155 | siginfo_t info; | |
156 | ||
157 | if (!user_mode(regs)) { | |
158 | if (die("Exception in kernel mode", regs, signr)) | |
159 | return; | |
160 | } | |
161 | ||
162 | memset(&info, 0, sizeof(info)); | |
163 | info.si_signo = signr; | |
164 | info.si_code = code; | |
165 | info.si_addr = (void __user *) addr; | |
166 | force_sig_info(signr, &info, current); | |
167 | ||
168 | /* | |
169 | * Init gets no signals that it doesn't have a handler for. | |
170 | * That's all very well, but if it has caused a synchronous | |
171 | * exception and we ignore the resulting signal, it will just | |
172 | * generate the same exception over and over again and we get | |
173 | * nowhere. Better to kill it and let the kernel panic. | |
174 | */ | |
60bccbed | 175 | if (is_init(current)) { |
14cf11af PM |
176 | __sighandler_t handler; |
177 | ||
178 | spin_lock_irq(¤t->sighand->siglock); | |
179 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
180 | spin_unlock_irq(¤t->sighand->siglock); | |
181 | if (handler == SIG_DFL) { | |
182 | /* init has generated a synchronous exception | |
183 | and it doesn't have a handler for the signal */ | |
184 | printk(KERN_CRIT "init has generated signal %d " | |
185 | "but has no handler for it\n", signr); | |
186 | do_exit(signr); | |
187 | } | |
188 | } | |
189 | } | |
190 | ||
191 | #ifdef CONFIG_PPC64 | |
192 | void system_reset_exception(struct pt_regs *regs) | |
193 | { | |
194 | /* See if any machine dependent calls */ | |
c902be71 AB |
195 | if (ppc_md.system_reset_exception) { |
196 | if (ppc_md.system_reset_exception(regs)) | |
197 | return; | |
198 | } | |
14cf11af | 199 | |
c0ce7d08 DW |
200 | #ifdef CONFIG_KEXEC |
201 | cpu_set(smp_processor_id(), cpus_in_sr); | |
202 | #endif | |
203 | ||
8dad3f92 | 204 | die("System Reset", regs, SIGABRT); |
14cf11af | 205 | |
eac8392f DW |
206 | /* |
207 | * Some CPUs when released from the debugger will execute this path. | |
208 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
209 | * hung before entering the debugger it will return to the hung | |
210 | * state when exiting this function. This causes a problem in | |
211 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
212 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
213 | * here. If a kdump had not been initiated or we exit the debugger | |
214 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
215 | * will return after 5ms and the CPU returns to its previous state. | |
216 | */ | |
217 | crash_kexec_secondary(regs); | |
218 | ||
14cf11af PM |
219 | /* Must die if the interrupt is not recoverable */ |
220 | if (!(regs->msr & MSR_RI)) | |
221 | panic("Unrecoverable System Reset"); | |
222 | ||
223 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
224 | } | |
225 | #endif | |
226 | ||
227 | /* | |
228 | * I/O accesses can cause machine checks on powermacs. | |
229 | * Check if the NIP corresponds to the address of a sync | |
230 | * instruction for which there is an entry in the exception | |
231 | * table. | |
232 | * Note that the 601 only takes a machine check on TEA | |
233 | * (transfer error ack) signal assertion, and does not | |
234 | * set any of the top 16 bits of SRR1. | |
235 | * -- paulus. | |
236 | */ | |
237 | static inline int check_io_access(struct pt_regs *regs) | |
238 | { | |
68a64357 | 239 | #ifdef CONFIG_PPC32 |
14cf11af PM |
240 | unsigned long msr = regs->msr; |
241 | const struct exception_table_entry *entry; | |
242 | unsigned int *nip = (unsigned int *)regs->nip; | |
243 | ||
244 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
245 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
246 | /* | |
247 | * Check that it's a sync instruction, or somewhere | |
248 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
249 | * As the address is in the exception table | |
250 | * we should be able to read the instr there. | |
251 | * For the debug message, we look at the preceding | |
252 | * load or store. | |
253 | */ | |
254 | if (*nip == 0x60000000) /* nop */ | |
255 | nip -= 2; | |
256 | else if (*nip == 0x4c00012c) /* isync */ | |
257 | --nip; | |
258 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
259 | /* sync or twi */ | |
260 | unsigned int rb; | |
261 | ||
262 | --nip; | |
263 | rb = (*nip >> 11) & 0x1f; | |
264 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
265 | (*nip & 0x100)? "OUT to": "IN from", | |
266 | regs->gpr[rb] - _IO_BASE, nip); | |
267 | regs->msr |= MSR_RI; | |
268 | regs->nip = entry->fixup; | |
269 | return 1; | |
270 | } | |
271 | } | |
68a64357 | 272 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
273 | return 0; |
274 | } | |
275 | ||
276 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
277 | /* On 4xx, the reason for the machine check or program exception | |
278 | is in the ESR. */ | |
279 | #define get_reason(regs) ((regs)->dsisr) | |
280 | #ifndef CONFIG_FSL_BOOKE | |
281 | #define get_mc_reason(regs) ((regs)->dsisr) | |
282 | #else | |
283 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | |
284 | #endif | |
285 | #define REASON_FP ESR_FP | |
286 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
287 | #define REASON_PRIVILEGED ESR_PPR | |
288 | #define REASON_TRAP ESR_PTR | |
289 | ||
290 | /* single-step stuff */ | |
291 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
292 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
293 | ||
294 | #else | |
295 | /* On non-4xx, the reason for the machine check or program | |
296 | exception is in the MSR. */ | |
297 | #define get_reason(regs) ((regs)->msr) | |
298 | #define get_mc_reason(regs) ((regs)->msr) | |
299 | #define REASON_FP 0x100000 | |
300 | #define REASON_ILLEGAL 0x80000 | |
301 | #define REASON_PRIVILEGED 0x40000 | |
302 | #define REASON_TRAP 0x20000 | |
303 | ||
304 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
305 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
306 | #endif | |
307 | ||
308 | /* | |
309 | * This is "fall-back" implementation for configurations | |
310 | * which don't provide platform-specific machine check info | |
311 | */ | |
312 | void __attribute__ ((weak)) | |
313 | platform_machine_check(struct pt_regs *regs) | |
314 | { | |
315 | } | |
316 | ||
dc1c1ca3 | 317 | void machine_check_exception(struct pt_regs *regs) |
14cf11af | 318 | { |
14cf11af | 319 | int recover = 0; |
1a6a4ffe | 320 | unsigned long reason = get_mc_reason(regs); |
14cf11af PM |
321 | |
322 | /* See if any machine dependent calls */ | |
323 | if (ppc_md.machine_check_exception) | |
324 | recover = ppc_md.machine_check_exception(regs); | |
325 | ||
326 | if (recover) | |
327 | return; | |
14cf11af PM |
328 | |
329 | if (user_mode(regs)) { | |
330 | regs->msr |= MSR_RI; | |
331 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
332 | return; | |
333 | } | |
334 | ||
335 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
336 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
337 | bad_page_fault(regs, regs->dar, SIGBUS); | |
338 | return; | |
339 | #endif | |
340 | ||
341 | if (debugger_fault_handler(regs)) { | |
342 | regs->msr |= MSR_RI; | |
343 | return; | |
344 | } | |
345 | ||
346 | if (check_io_access(regs)) | |
347 | return; | |
348 | ||
349 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) | |
350 | if (reason & ESR_IMCP) { | |
351 | printk("Instruction"); | |
352 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
353 | } else | |
354 | printk("Data"); | |
355 | printk(" machine check in kernel mode.\n"); | |
356 | #elif defined(CONFIG_440A) | |
357 | printk("Machine check in kernel mode.\n"); | |
358 | if (reason & ESR_IMCP){ | |
359 | printk("Instruction Synchronous Machine Check exception\n"); | |
360 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
361 | } | |
362 | else { | |
363 | u32 mcsr = mfspr(SPRN_MCSR); | |
364 | if (mcsr & MCSR_IB) | |
365 | printk("Instruction Read PLB Error\n"); | |
366 | if (mcsr & MCSR_DRB) | |
367 | printk("Data Read PLB Error\n"); | |
368 | if (mcsr & MCSR_DWB) | |
369 | printk("Data Write PLB Error\n"); | |
370 | if (mcsr & MCSR_TLBP) | |
371 | printk("TLB Parity Error\n"); | |
372 | if (mcsr & MCSR_ICP){ | |
373 | flush_instruction_cache(); | |
374 | printk("I-Cache Parity Error\n"); | |
375 | } | |
376 | if (mcsr & MCSR_DCSP) | |
377 | printk("D-Cache Search Parity Error\n"); | |
378 | if (mcsr & MCSR_DCFP) | |
379 | printk("D-Cache Flush Parity Error\n"); | |
380 | if (mcsr & MCSR_IMPE) | |
381 | printk("Machine Check exception is imprecise\n"); | |
382 | ||
383 | /* Clear MCSR */ | |
384 | mtspr(SPRN_MCSR, mcsr); | |
385 | } | |
386 | #elif defined (CONFIG_E500) | |
387 | printk("Machine check in kernel mode.\n"); | |
388 | printk("Caused by (from MCSR=%lx): ", reason); | |
389 | ||
390 | if (reason & MCSR_MCP) | |
391 | printk("Machine Check Signal\n"); | |
392 | if (reason & MCSR_ICPERR) | |
393 | printk("Instruction Cache Parity Error\n"); | |
394 | if (reason & MCSR_DCP_PERR) | |
395 | printk("Data Cache Push Parity Error\n"); | |
396 | if (reason & MCSR_DCPERR) | |
397 | printk("Data Cache Parity Error\n"); | |
398 | if (reason & MCSR_GL_CI) | |
399 | printk("Guarded Load or Cache-Inhibited stwcx.\n"); | |
400 | if (reason & MCSR_BUS_IAERR) | |
401 | printk("Bus - Instruction Address Error\n"); | |
402 | if (reason & MCSR_BUS_RAERR) | |
403 | printk("Bus - Read Address Error\n"); | |
404 | if (reason & MCSR_BUS_WAERR) | |
405 | printk("Bus - Write Address Error\n"); | |
406 | if (reason & MCSR_BUS_IBERR) | |
407 | printk("Bus - Instruction Data Error\n"); | |
408 | if (reason & MCSR_BUS_RBERR) | |
409 | printk("Bus - Read Data Bus Error\n"); | |
410 | if (reason & MCSR_BUS_WBERR) | |
411 | printk("Bus - Read Data Bus Error\n"); | |
412 | if (reason & MCSR_BUS_IPERR) | |
413 | printk("Bus - Instruction Parity Error\n"); | |
414 | if (reason & MCSR_BUS_RPERR) | |
415 | printk("Bus - Read Parity Error\n"); | |
416 | #elif defined (CONFIG_E200) | |
417 | printk("Machine check in kernel mode.\n"); | |
418 | printk("Caused by (from MCSR=%lx): ", reason); | |
419 | ||
420 | if (reason & MCSR_MCP) | |
421 | printk("Machine Check Signal\n"); | |
422 | if (reason & MCSR_CP_PERR) | |
423 | printk("Cache Push Parity Error\n"); | |
424 | if (reason & MCSR_CPERR) | |
425 | printk("Cache Parity Error\n"); | |
426 | if (reason & MCSR_EXCP_ERR) | |
427 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
428 | if (reason & MCSR_BUS_IRERR) | |
429 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
430 | if (reason & MCSR_BUS_DRERR) | |
431 | printk("Bus - Read Bus Error on data load\n"); | |
432 | if (reason & MCSR_BUS_WRERR) | |
433 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
434 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | |
435 | printk("Machine check in kernel mode.\n"); | |
436 | printk("Caused by (from SRR1=%lx): ", reason); | |
437 | switch (reason & 0x601F0000) { | |
438 | case 0x80000: | |
439 | printk("Machine check signal\n"); | |
440 | break; | |
441 | case 0: /* for 601 */ | |
442 | case 0x40000: | |
443 | case 0x140000: /* 7450 MSS error and TEA */ | |
444 | printk("Transfer error ack signal\n"); | |
445 | break; | |
446 | case 0x20000: | |
447 | printk("Data parity error signal\n"); | |
448 | break; | |
449 | case 0x10000: | |
450 | printk("Address parity error signal\n"); | |
451 | break; | |
452 | case 0x20000000: | |
453 | printk("L1 Data Cache error\n"); | |
454 | break; | |
455 | case 0x40000000: | |
456 | printk("L1 Instruction Cache error\n"); | |
457 | break; | |
458 | case 0x00100000: | |
459 | printk("L2 data cache parity error\n"); | |
460 | break; | |
461 | default: | |
462 | printk("Unknown values in msr\n"); | |
463 | } | |
464 | #endif /* CONFIG_4xx */ | |
465 | ||
466 | /* | |
467 | * Optional platform-provided routine to print out | |
468 | * additional info, e.g. bus error registers. | |
469 | */ | |
470 | platform_machine_check(regs); | |
14cf11af PM |
471 | |
472 | if (debugger_fault_handler(regs)) | |
473 | return; | |
8dad3f92 | 474 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
475 | |
476 | /* Must die if the interrupt is not recoverable */ | |
477 | if (!(regs->msr & MSR_RI)) | |
478 | panic("Unrecoverable Machine check"); | |
479 | } | |
480 | ||
481 | void SMIException(struct pt_regs *regs) | |
482 | { | |
483 | die("System Management Interrupt", regs, SIGABRT); | |
484 | } | |
485 | ||
dc1c1ca3 | 486 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
487 | { |
488 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
489 | regs->nip, regs->msr, regs->trap); | |
490 | ||
491 | _exception(SIGTRAP, regs, 0, 0); | |
492 | } | |
493 | ||
dc1c1ca3 | 494 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
495 | { |
496 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
497 | 5, SIGTRAP) == NOTIFY_STOP) | |
498 | return; | |
499 | if (debugger_iabr_match(regs)) | |
500 | return; | |
501 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
502 | } | |
503 | ||
504 | void RunModeException(struct pt_regs *regs) | |
505 | { | |
506 | _exception(SIGTRAP, regs, 0, 0); | |
507 | } | |
508 | ||
8dad3f92 | 509 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
510 | { |
511 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
512 | ||
513 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
514 | 5, SIGTRAP) == NOTIFY_STOP) | |
515 | return; | |
516 | if (debugger_sstep(regs)) | |
517 | return; | |
518 | ||
519 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
520 | } | |
521 | ||
522 | /* | |
523 | * After we have successfully emulated an instruction, we have to | |
524 | * check if the instruction was being single-stepped, and if so, | |
525 | * pretend we got a single-step exception. This was pointed out | |
526 | * by Kumar Gala. -- paulus | |
527 | */ | |
8dad3f92 | 528 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
529 | { |
530 | if (single_stepping(regs)) { | |
531 | clear_single_step(regs); | |
532 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
533 | } | |
534 | } | |
535 | ||
5fad293b | 536 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 537 | { |
5fad293b | 538 | int ret = 0; |
dc1c1ca3 SR |
539 | |
540 | /* Invalid operation */ | |
541 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 542 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
543 | |
544 | /* Overflow */ | |
545 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 546 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
547 | |
548 | /* Underflow */ | |
549 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 550 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
551 | |
552 | /* Divide by zero */ | |
553 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 554 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
555 | |
556 | /* Inexact result */ | |
557 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
558 | ret = FPE_FLTRES; |
559 | ||
560 | return ret; | |
561 | } | |
562 | ||
563 | static void parse_fpe(struct pt_regs *regs) | |
564 | { | |
565 | int code = 0; | |
566 | ||
567 | flush_fp_to_thread(current); | |
568 | ||
569 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
570 | |
571 | _exception(SIGFPE, regs, code, regs->nip); | |
572 | } | |
573 | ||
574 | /* | |
575 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
576 | * provide the PVR to user applications using the mfspr rd, PVR. |
577 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
578 | * memory access caused an access fault. Return zero on success. | |
579 | * | |
580 | * There are a couple of ways to do this, either "decode" the instruction | |
581 | * or directly match lots of bits. In this case, matching lots of | |
582 | * bits is faster and easier. | |
86417780 | 583 | * |
14cf11af PM |
584 | */ |
585 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
586 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
587 | ||
588 | #define INST_DCBA 0x7c0005ec | |
87589f08 | 589 | #define INST_DCBA_MASK 0xfc0007fe |
14cf11af PM |
590 | |
591 | #define INST_MCRXR 0x7c000400 | |
87589f08 | 592 | #define INST_MCRXR_MASK 0xfc0007fe |
14cf11af PM |
593 | |
594 | #define INST_STRING 0x7c00042a | |
87589f08 PM |
595 | #define INST_STRING_MASK 0xfc0007fe |
596 | #define INST_STRING_GEN_MASK 0xfc00067e | |
14cf11af PM |
597 | #define INST_LSWI 0x7c0004aa |
598 | #define INST_LSWX 0x7c00042a | |
599 | #define INST_STSWI 0x7c0005aa | |
600 | #define INST_STSWX 0x7c00052a | |
601 | ||
c3412dcb WS |
602 | #define INST_POPCNTB 0x7c0000f4 |
603 | #define INST_POPCNTB_MASK 0xfc0007fe | |
604 | ||
14cf11af PM |
605 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
606 | { | |
607 | u8 rT = (instword >> 21) & 0x1f; | |
608 | u8 rA = (instword >> 16) & 0x1f; | |
609 | u8 NB_RB = (instword >> 11) & 0x1f; | |
610 | u32 num_bytes; | |
611 | unsigned long EA; | |
612 | int pos = 0; | |
613 | ||
614 | /* Early out if we are an invalid form of lswx */ | |
615 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
616 | if ((rT == rA) || (rT == NB_RB)) | |
617 | return -EINVAL; | |
618 | ||
619 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
620 | ||
621 | switch (instword & INST_STRING_MASK) { | |
622 | case INST_LSWX: | |
623 | case INST_STSWX: | |
624 | EA += NB_RB; | |
625 | num_bytes = regs->xer & 0x7f; | |
626 | break; | |
627 | case INST_LSWI: | |
628 | case INST_STSWI: | |
629 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
630 | break; | |
631 | default: | |
632 | return -EINVAL; | |
633 | } | |
634 | ||
635 | while (num_bytes != 0) | |
636 | { | |
637 | u8 val; | |
638 | u32 shift = 8 * (3 - (pos & 0x3)); | |
639 | ||
640 | switch ((instword & INST_STRING_MASK)) { | |
641 | case INST_LSWX: | |
642 | case INST_LSWI: | |
643 | if (get_user(val, (u8 __user *)EA)) | |
644 | return -EFAULT; | |
645 | /* first time updating this reg, | |
646 | * zero it out */ | |
647 | if (pos == 0) | |
648 | regs->gpr[rT] = 0; | |
649 | regs->gpr[rT] |= val << shift; | |
650 | break; | |
651 | case INST_STSWI: | |
652 | case INST_STSWX: | |
653 | val = regs->gpr[rT] >> shift; | |
654 | if (put_user(val, (u8 __user *)EA)) | |
655 | return -EFAULT; | |
656 | break; | |
657 | } | |
658 | /* move EA to next address */ | |
659 | EA += 1; | |
660 | num_bytes--; | |
661 | ||
662 | /* manage our position within the register */ | |
663 | if (++pos == 4) { | |
664 | pos = 0; | |
665 | if (++rT == 32) | |
666 | rT = 0; | |
667 | } | |
668 | } | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
c3412dcb WS |
673 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
674 | { | |
675 | u32 ra,rs; | |
676 | unsigned long tmp; | |
677 | ||
678 | ra = (instword >> 16) & 0x1f; | |
679 | rs = (instword >> 21) & 0x1f; | |
680 | ||
681 | tmp = regs->gpr[rs]; | |
682 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
683 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
684 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
685 | regs->gpr[ra] = tmp; | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
14cf11af PM |
690 | static int emulate_instruction(struct pt_regs *regs) |
691 | { | |
692 | u32 instword; | |
693 | u32 rd; | |
694 | ||
fab5db97 | 695 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
696 | return -EINVAL; |
697 | CHECK_FULL_REGS(regs); | |
698 | ||
699 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
700 | return -EFAULT; | |
701 | ||
702 | /* Emulate the mfspr rD, PVR. */ | |
703 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
704 | rd = (instword >> 21) & 0x1f; | |
705 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
706 | return 0; | |
707 | } | |
708 | ||
709 | /* Emulating the dcba insn is just a no-op. */ | |
8dad3f92 | 710 | if ((instword & INST_DCBA_MASK) == INST_DCBA) |
14cf11af PM |
711 | return 0; |
712 | ||
713 | /* Emulate the mcrxr insn. */ | |
714 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
86417780 | 715 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
716 | unsigned long msk = 0xf0000000UL >> shift; |
717 | ||
718 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
719 | regs->xer &= ~0xf0000000UL; | |
720 | return 0; | |
721 | } | |
722 | ||
723 | /* Emulate load/store string insn. */ | |
724 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
725 | return emulate_string_inst(regs, instword); | |
726 | ||
c3412dcb WS |
727 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
728 | if ((instword & INST_POPCNTB_MASK) == INST_POPCNTB) { | |
729 | return emulate_popcntb_inst(regs, instword); | |
730 | } | |
731 | ||
14cf11af PM |
732 | return -EINVAL; |
733 | } | |
734 | ||
73c9ceab | 735 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 736 | { |
73c9ceab | 737 | return is_kernel_addr(addr); |
14cf11af PM |
738 | } |
739 | ||
8dad3f92 | 740 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
741 | { |
742 | unsigned int reason = get_reason(regs); | |
743 | extern int do_mathemu(struct pt_regs *regs); | |
744 | ||
aa42c69c | 745 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 746 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 747 | |
dc1c1ca3 SR |
748 | if (reason & REASON_FP) { |
749 | /* IEEE FP exception */ | |
750 | parse_fpe(regs); | |
8dad3f92 PM |
751 | return; |
752 | } | |
753 | if (reason & REASON_TRAP) { | |
14cf11af | 754 | /* trap exception */ |
dc1c1ca3 SR |
755 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
756 | == NOTIFY_STOP) | |
757 | return; | |
14cf11af PM |
758 | if (debugger_bpt(regs)) |
759 | return; | |
73c9ceab JF |
760 | |
761 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
762 | report_bug(regs->nip) == BUG_TRAP_TYPE_WARN) { | |
14cf11af PM |
763 | regs->nip += 4; |
764 | return; | |
765 | } | |
8dad3f92 PM |
766 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
767 | return; | |
768 | } | |
769 | ||
cd8a5673 PM |
770 | local_irq_enable(); |
771 | ||
04903a30 KG |
772 | #ifdef CONFIG_MATH_EMULATION |
773 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
774 | * but there seems to be a hardware bug on the 405GP (RevD) | |
775 | * that means ESR is sometimes set incorrectly - either to | |
776 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
777 | * hardware people - not sure if it can happen on any illegal | |
778 | * instruction or only on FP instructions, whether there is a | |
779 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
780 | switch (do_mathemu(regs)) { |
781 | case 0: | |
04903a30 KG |
782 | emulate_single_step(regs); |
783 | return; | |
5fad293b KG |
784 | case 1: { |
785 | int code = 0; | |
786 | code = __parse_fpscr(current->thread.fpscr.val); | |
787 | _exception(SIGFPE, regs, code, regs->nip); | |
788 | return; | |
789 | } | |
790 | case -EFAULT: | |
791 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
792 | return; | |
04903a30 | 793 | } |
5fad293b | 794 | /* fall through on any other errors */ |
04903a30 KG |
795 | #endif /* CONFIG_MATH_EMULATION */ |
796 | ||
8dad3f92 PM |
797 | /* Try to emulate it if we should. */ |
798 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
799 | switch (emulate_instruction(regs)) { |
800 | case 0: | |
801 | regs->nip += 4; | |
802 | emulate_single_step(regs); | |
8dad3f92 | 803 | return; |
14cf11af PM |
804 | case -EFAULT: |
805 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 806 | return; |
14cf11af PM |
807 | } |
808 | } | |
8dad3f92 PM |
809 | |
810 | if (reason & REASON_PRIVILEGED) | |
811 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
812 | else | |
813 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
814 | } |
815 | ||
dc1c1ca3 | 816 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 817 | { |
4393c4f6 | 818 | int sig, code, fixed = 0; |
14cf11af | 819 | |
e9370ae1 PM |
820 | /* we don't implement logging of alignment exceptions */ |
821 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
822 | fixed = fix_alignment(regs); | |
14cf11af PM |
823 | |
824 | if (fixed == 1) { | |
825 | regs->nip += 4; /* skip over emulated instruction */ | |
826 | emulate_single_step(regs); | |
827 | return; | |
828 | } | |
829 | ||
dc1c1ca3 | 830 | /* Operand address was bad */ |
14cf11af | 831 | if (fixed == -EFAULT) { |
4393c4f6 BH |
832 | sig = SIGSEGV; |
833 | code = SEGV_ACCERR; | |
834 | } else { | |
835 | sig = SIGBUS; | |
836 | code = BUS_ADRALN; | |
14cf11af | 837 | } |
4393c4f6 BH |
838 | if (user_mode(regs)) |
839 | _exception(sig, regs, code, regs->dar); | |
840 | else | |
841 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
842 | } |
843 | ||
844 | void StackOverflow(struct pt_regs *regs) | |
845 | { | |
846 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
847 | current, regs->gpr[1]); | |
848 | debugger(regs); | |
849 | show_regs(regs); | |
850 | panic("kernel stack overflow"); | |
851 | } | |
852 | ||
853 | void nonrecoverable_exception(struct pt_regs *regs) | |
854 | { | |
855 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
856 | regs->nip, regs->msr); | |
857 | debugger(regs); | |
858 | die("nonrecoverable exception", regs, SIGKILL); | |
859 | } | |
860 | ||
861 | void trace_syscall(struct pt_regs *regs) | |
862 | { | |
863 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
864 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
865 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
866 | } | |
dc1c1ca3 | 867 | |
dc1c1ca3 SR |
868 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
869 | { | |
870 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
871 | "%lx at %lx\n", regs->trap, regs->nip); | |
872 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
873 | } | |
dc1c1ca3 SR |
874 | |
875 | void altivec_unavailable_exception(struct pt_regs *regs) | |
876 | { | |
dc1c1ca3 SR |
877 | if (user_mode(regs)) { |
878 | /* A user program has executed an altivec instruction, | |
879 | but this kernel doesn't support altivec. */ | |
880 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
881 | return; | |
882 | } | |
6c4841c2 | 883 | |
dc1c1ca3 SR |
884 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
885 | "%lx at %lx\n", regs->trap, regs->nip); | |
886 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
887 | } |
888 | ||
dc1c1ca3 SR |
889 | void performance_monitor_exception(struct pt_regs *regs) |
890 | { | |
891 | perf_irq(regs); | |
892 | } | |
dc1c1ca3 | 893 | |
8dad3f92 | 894 | #ifdef CONFIG_8xx |
14cf11af PM |
895 | void SoftwareEmulation(struct pt_regs *regs) |
896 | { | |
897 | extern int do_mathemu(struct pt_regs *); | |
898 | extern int Soft_emulate_8xx(struct pt_regs *); | |
899 | int errcode; | |
900 | ||
901 | CHECK_FULL_REGS(regs); | |
902 | ||
903 | if (!user_mode(regs)) { | |
904 | debugger(regs); | |
905 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
906 | } | |
907 | ||
908 | #ifdef CONFIG_MATH_EMULATION | |
909 | errcode = do_mathemu(regs); | |
5fad293b KG |
910 | |
911 | switch (errcode) { | |
912 | case 0: | |
913 | emulate_single_step(regs); | |
914 | return; | |
915 | case 1: { | |
916 | int code = 0; | |
917 | code = __parse_fpscr(current->thread.fpscr.val); | |
918 | _exception(SIGFPE, regs, code, regs->nip); | |
919 | return; | |
920 | } | |
921 | case -EFAULT: | |
922 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
923 | return; | |
924 | default: | |
925 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
926 | return; | |
927 | } | |
928 | ||
14cf11af PM |
929 | #else |
930 | errcode = Soft_emulate_8xx(regs); | |
5fad293b KG |
931 | switch (errcode) { |
932 | case 0: | |
14cf11af | 933 | emulate_single_step(regs); |
5fad293b KG |
934 | return; |
935 | case 1: | |
936 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
937 | return; | |
938 | case -EFAULT: | |
939 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
940 | return; | |
941 | } | |
942 | #endif | |
14cf11af | 943 | } |
8dad3f92 | 944 | #endif /* CONFIG_8xx */ |
14cf11af PM |
945 | |
946 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
947 | ||
948 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
949 | { | |
950 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
951 | regs->msr &= ~MSR_DE; | |
952 | if (user_mode(regs)) { | |
953 | current->thread.dbcr0 &= ~DBCR0_IC; | |
954 | } else { | |
955 | /* Disable instruction completion */ | |
956 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
957 | /* Clear the instruction completion event */ | |
958 | mtspr(SPRN_DBSR, DBSR_IC); | |
959 | if (debugger_sstep(regs)) | |
960 | return; | |
961 | } | |
962 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
963 | } | |
964 | } | |
965 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
966 | ||
967 | #if !defined(CONFIG_TAU_INT) | |
968 | void TAUException(struct pt_regs *regs) | |
969 | { | |
970 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
971 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
972 | } | |
973 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
974 | |
975 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 976 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
977 | { |
978 | int err; | |
979 | ||
14cf11af PM |
980 | if (!user_mode(regs)) { |
981 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
982 | " at %lx\n", regs->nip); | |
8dad3f92 | 983 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
984 | } |
985 | ||
dc1c1ca3 | 986 | flush_altivec_to_thread(current); |
dc1c1ca3 | 987 | |
14cf11af PM |
988 | err = emulate_altivec(regs); |
989 | if (err == 0) { | |
990 | regs->nip += 4; /* skip emulated instruction */ | |
991 | emulate_single_step(regs); | |
992 | return; | |
993 | } | |
994 | ||
995 | if (err == -EFAULT) { | |
996 | /* got an error reading the instruction */ | |
997 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
998 | } else { | |
999 | /* didn't recognize the instruction */ | |
1000 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1001 | if (printk_ratelimit()) | |
1002 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1003 | "in %s at %lx\n", current->comm, regs->nip); | |
1004 | current->thread.vscr.u[3] |= 0x10000; | |
1005 | } | |
1006 | } | |
1007 | #endif /* CONFIG_ALTIVEC */ | |
1008 | ||
14cf11af PM |
1009 | #ifdef CONFIG_FSL_BOOKE |
1010 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1011 | unsigned long error_code) | |
1012 | { | |
1013 | /* We treat cache locking instructions from the user | |
1014 | * as priv ops, in the future we could try to do | |
1015 | * something smarter | |
1016 | */ | |
1017 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1018 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1019 | return; | |
1020 | } | |
1021 | #endif /* CONFIG_FSL_BOOKE */ | |
1022 | ||
1023 | #ifdef CONFIG_SPE | |
1024 | void SPEFloatingPointException(struct pt_regs *regs) | |
1025 | { | |
1026 | unsigned long spefscr; | |
1027 | int fpexc_mode; | |
1028 | int code = 0; | |
1029 | ||
1030 | spefscr = current->thread.spefscr; | |
1031 | fpexc_mode = current->thread.fpexc_mode; | |
1032 | ||
1033 | /* Hardware does not neccessarily set sticky | |
1034 | * underflow/overflow/invalid flags */ | |
1035 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
1036 | code = FPE_FLTOVF; | |
1037 | spefscr |= SPEFSCR_FOVFS; | |
1038 | } | |
1039 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1040 | code = FPE_FLTUND; | |
1041 | spefscr |= SPEFSCR_FUNFS; | |
1042 | } | |
1043 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1044 | code = FPE_FLTDIV; | |
1045 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1046 | code = FPE_FLTINV; | |
1047 | spefscr |= SPEFSCR_FINVS; | |
1048 | } | |
1049 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1050 | code = FPE_FLTRES; | |
1051 | ||
1052 | current->thread.spefscr = spefscr; | |
1053 | ||
1054 | _exception(SIGFPE, regs, code, regs->nip); | |
1055 | return; | |
1056 | } | |
1057 | #endif | |
1058 | ||
dc1c1ca3 SR |
1059 | /* |
1060 | * We enter here if we get an unrecoverable exception, that is, one | |
1061 | * that happened at a point where the RI (recoverable interrupt) bit | |
1062 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1063 | * we therefore lost state by taking this exception. | |
1064 | */ | |
1065 | void unrecoverable_exception(struct pt_regs *regs) | |
1066 | { | |
1067 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1068 | regs->trap, regs->nip); | |
1069 | die("Unrecoverable exception", regs, SIGABRT); | |
1070 | } | |
dc1c1ca3 | 1071 | |
14cf11af PM |
1072 | #ifdef CONFIG_BOOKE_WDT |
1073 | /* | |
1074 | * Default handler for a Watchdog exception, | |
1075 | * spins until a reboot occurs | |
1076 | */ | |
1077 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1078 | { | |
1079 | /* Generic WatchdogHandler, implement your own */ | |
1080 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1081 | return; | |
1082 | } | |
1083 | ||
1084 | void WatchdogException(struct pt_regs *regs) | |
1085 | { | |
1086 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1087 | WatchdogHandler(regs); | |
1088 | } | |
1089 | #endif | |
dc1c1ca3 | 1090 | |
dc1c1ca3 SR |
1091 | /* |
1092 | * We enter here if we discover during exception entry that we are | |
1093 | * running in supervisor mode with a userspace value in the stack pointer. | |
1094 | */ | |
1095 | void kernel_bad_stack(struct pt_regs *regs) | |
1096 | { | |
1097 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1098 | regs->gpr[1], regs->nip); | |
1099 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1100 | } | |
14cf11af PM |
1101 | |
1102 | void __init trap_init(void) | |
1103 | { | |
1104 | } |