projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] Add a prctl to change the endianness of a process.
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
17#include <linux/config.h>
18#include <linux/errno.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
8dad3f92 24#include <linux/ptrace.h>
14cf11af
PM		 25#include <linux/slab.h>
26#include <linux/user.h>
27#include <linux/a.out.h>
28#include <linux/interrupt.h>
14cf11af
PM		 29#include <linux/init.h>
30#include <linux/module.h>
8dad3f92 31#include <linux/prctl.h>
14cf11af
PM		 32#include <linux/delay.h>
33#include <linux/kprobes.h>
cc532915 34#include <linux/kexec.h>
14cf11af 35
86417780 36#include <asm/kdebug.h>
14cf11af
PM		 37#include <asm/pgtable.h>
38#include <asm/uaccess.h>
39#include <asm/system.h>
40#include <asm/io.h>
86417780
PM		 41#include <asm/machdep.h>
42#include <asm/rtas.h>
f7f6f4fe 43#include <asm/pmc.h>
dc1c1ca3 44#ifdef CONFIG_PPC32
14cf11af 45#include <asm/reg.h>
86417780 46#endif
14cf11af
PM		 47#ifdef CONFIG_PMAC_BACKLIGHT
48#include <asm/backlight.h>
49#endif
dc1c1ca3 50#ifdef CONFIG_PPC64
86417780 51#include <asm/firmware.h>
dc1c1ca3 52#include <asm/processor.h>
dc1c1ca3
SR		 53#endif
54
86417780
PM		 55#ifdef CONFIG_PPC64 /* XXX */
56#define _IO_BASE pci_io_base
57#endif
58
14cf11af
PM		 59#ifdef CONFIG_DEBUGGER
60int (*__debugger)(struct pt_regs *regs);
61int (*__debugger_ipi)(struct pt_regs *regs);
62int (*__debugger_bpt)(struct pt_regs *regs);
63int (*__debugger_sstep)(struct pt_regs *regs);
64int (*__debugger_iabr_match)(struct pt_regs *regs);
65int (*__debugger_dabr_match)(struct pt_regs *regs);
66int (*__debugger_fault_handler)(struct pt_regs *regs);
67
68EXPORT_SYMBOL(__debugger);
69EXPORT_SYMBOL(__debugger_ipi);
70EXPORT_SYMBOL(__debugger_bpt);
71EXPORT_SYMBOL(__debugger_sstep);
72EXPORT_SYMBOL(__debugger_iabr_match);
73EXPORT_SYMBOL(__debugger_dabr_match);
74EXPORT_SYMBOL(__debugger_fault_handler);
75#endif
76
e041c683 77ATOMIC_NOTIFIER_HEAD(powerpc_die_chain);
14cf11af
PM		 78
79int register_die_notifier(struct notifier_block *nb)
80{
e041c683
AS		 81 return atomic_notifier_chain_register(&powerpc_die_chain, nb);
82}
83EXPORT_SYMBOL(register_die_notifier);
14cf11af 84
e041c683
AS		 85int unregister_die_notifier(struct notifier_block *nb)
86{
87 return atomic_notifier_chain_unregister(&powerpc_die_chain, nb);
14cf11af 88}
e041c683 89EXPORT_SYMBOL(unregister_die_notifier);
14cf11af
PM		 90
91/*
92 * Trap & Exception support
93 */
94
95static DEFINE_SPINLOCK(die_lock);
96
97int die(const char *str, struct pt_regs *regs, long err)
98{
cc532915 99 static int die_counter, crash_dump_start = 0;
14cf11af
PM		 100
101 if (debugger(regs))
102 return 1;
103
104 console_verbose();
105 spin_lock_irq(&die_lock);
106 bust_spinlocks(1);
8dad3f92 107#ifdef CONFIG_PMAC_BACKLIGHT
e8222502 108 if (machine_is(powermac)) {
14cf11af
PM		 109 set_backlight_enable(1);
110 set_backlight_level(BACKLIGHT_MAX);
111 }
112#endif
113 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
114#ifdef CONFIG_PREEMPT
115 printk("PREEMPT ");
14cf11af
PM		 116#endif
117#ifdef CONFIG_SMP
118 printk("SMP NR_CPUS=%d ", NR_CPUS);
14cf11af
PM		 119#endif
120#ifdef CONFIG_DEBUG_PAGEALLOC
121 printk("DEBUG_PAGEALLOC ");
14cf11af
PM		 122#endif
123#ifdef CONFIG_NUMA
124 printk("NUMA ");
14cf11af 125#endif
e8222502
BH		 126 printk("%s\n", ppc_md.name ? "" : ppc_md.name);
127
14cf11af
PM		 128 print_modules();
129 show_regs(regs);
130 bust_spinlocks(0);
cc532915
ME		 131
132 if (!crash_dump_start && kexec_should_crash(current)) {
133 crash_dump_start = 1;
134 spin_unlock_irq(&die_lock);
135 crash_kexec(regs);
136 /* NOTREACHED */
137 }
14cf11af 138 spin_unlock_irq(&die_lock);
cc532915
ME		 139 if (crash_dump_start)
140 /*
141 * Only for soft-reset: Other CPUs will be responded to an IPI
142 * sent by first kexec CPU.
143 */
144 for(;;)
145 ;
14cf11af
PM		 146
147 if (in_interrupt())
148 panic("Fatal exception in interrupt");
149
150 if (panic_on_oops) {
dc1c1ca3
SR		 151#ifdef CONFIG_PPC64
152 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
153 ssleep(5);
154#endif
14cf11af
PM		 155 panic("Fatal exception");
156 }
157 do_exit(err);
158
159 return 0;
160}
161
162void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
163{
164 siginfo_t info;
165
166 if (!user_mode(regs)) {
167 if (die("Exception in kernel mode", regs, signr))
168 return;
169 }
170
171 memset(&info, 0, sizeof(info));
172 info.si_signo = signr;
173 info.si_code = code;
174 info.si_addr = (void __user *) addr;
175 force_sig_info(signr, &info, current);
176
177 /*
178 * Init gets no signals that it doesn't have a handler for.
179 * That's all very well, but if it has caused a synchronous
180 * exception and we ignore the resulting signal, it will just
181 * generate the same exception over and over again and we get
182 * nowhere. Better to kill it and let the kernel panic.
183 */
184 if (current->pid == 1) {
185 __sighandler_t handler;
186
187 spin_lock_irq(&current->sighand->siglock);
188 handler = current->sighand->action[signr-1].sa.sa_handler;
189 spin_unlock_irq(&current->sighand->siglock);
190 if (handler == SIG_DFL) {
191 /* init has generated a synchronous exception
192 and it doesn't have a handler for the signal */
193 printk(KERN_CRIT "init has generated signal %d "
194 "but has no handler for it\n", signr);
195 do_exit(signr);
196 }
197 }
198}
199
200#ifdef CONFIG_PPC64
201void system_reset_exception(struct pt_regs *regs)
202{
203 /* See if any machine dependent calls */
c902be71
AB		 204 if (ppc_md.system_reset_exception) {
205 if (ppc_md.system_reset_exception(regs))
206 return;
207 }
14cf11af 208
8dad3f92 209 die("System Reset", regs, SIGABRT);
14cf11af
PM		 210
211 /* Must die if the interrupt is not recoverable */
212 if (!(regs->msr & MSR_RI))
213 panic("Unrecoverable System Reset");
214
215 /* What should we do here? We could issue a shutdown or hard reset. */
216}
217#endif
218
219/*
220 * I/O accesses can cause machine checks on powermacs.
221 * Check if the NIP corresponds to the address of a sync
222 * instruction for which there is an entry in the exception
223 * table.
224 * Note that the 601 only takes a machine check on TEA
225 * (transfer error ack) signal assertion, and does not
226 * set any of the top 16 bits of SRR1.
227 * -- paulus.
228 */
229static inline int check_io_access(struct pt_regs *regs)
230{
1a6a4ffe 231#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
14cf11af
PM		 232 unsigned long msr = regs->msr;
233 const struct exception_table_entry *entry;
234 unsigned int *nip = (unsigned int *)regs->nip;
235
236 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
237 && (entry = search_exception_tables(regs->nip)) != NULL) {
238 /*
239 * Check that it's a sync instruction, or somewhere
240 * in the twi; isync; nop sequence that inb/inw/inl uses.
241 * As the address is in the exception table
242 * we should be able to read the instr there.
243 * For the debug message, we look at the preceding
244 * load or store.
245 */
246 if (*nip == 0x60000000) /* nop */
247 nip -= 2;
248 else if (*nip == 0x4c00012c) /* isync */
249 --nip;
250 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
251 /* sync or twi */
252 unsigned int rb;
253
254 --nip;
255 rb = (*nip >> 11) & 0x1f;
256 printk(KERN_DEBUG "%s bad port %lx at %p\n",
257 (*nip & 0x100)? "OUT to": "IN from",
258 regs->gpr[rb] - _IO_BASE, nip);
259 regs->msr |= MSR_RI;
260 regs->nip = entry->fixup;
261 return 1;
262 }
263 }
1a6a4ffe 264#endif /* CONFIG_PPC_PMAC && CONFIG_PPC32 */
14cf11af
PM		 265 return 0;
266}
267
268#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
269/* On 4xx, the reason for the machine check or program exception
270 is in the ESR. */
271#define get_reason(regs) ((regs)->dsisr)
272#ifndef CONFIG_FSL_BOOKE
273#define get_mc_reason(regs) ((regs)->dsisr)
274#else
275#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
276#endif
277#define REASON_FP ESR_FP
278#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
279#define REASON_PRIVILEGED ESR_PPR
280#define REASON_TRAP ESR_PTR
281
282/* single-step stuff */
283#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
284#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
285
286#else
287/* On non-4xx, the reason for the machine check or program
288 exception is in the MSR. */
289#define get_reason(regs) ((regs)->msr)
290#define get_mc_reason(regs) ((regs)->msr)
291#define REASON_FP 0x100000
292#define REASON_ILLEGAL 0x80000
293#define REASON_PRIVILEGED 0x40000
294#define REASON_TRAP 0x20000
295
296#define single_stepping(regs) ((regs)->msr & MSR_SE)
297#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
298#endif
299
300/*
301 * This is "fall-back" implementation for configurations
302 * which don't provide platform-specific machine check info
303 */
304void __attribute__ ((weak))
305platform_machine_check(struct pt_regs *regs)
306{
307}
308
dc1c1ca3 309void machine_check_exception(struct pt_regs *regs)
14cf11af 310{
14cf11af 311 int recover = 0;
1a6a4ffe 312 unsigned long reason = get_mc_reason(regs);
14cf11af
PM		 313
314 /* See if any machine dependent calls */
315 if (ppc_md.machine_check_exception)
316 recover = ppc_md.machine_check_exception(regs);
317
318 if (recover)
319 return;
14cf11af
PM		 320
321 if (user_mode(regs)) {
322 regs->msr |= MSR_RI;
323 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
324 return;
325 }
326
327#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
328 /* the qspan pci read routines can cause machine checks -- Cort */
329 bad_page_fault(regs, regs->dar, SIGBUS);
330 return;
331#endif
332
333 if (debugger_fault_handler(regs)) {
334 regs->msr |= MSR_RI;
335 return;
336 }
337
338 if (check_io_access(regs))
339 return;
340
341#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
342 if (reason & ESR_IMCP) {
343 printk("Instruction");
344 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
345 } else
346 printk("Data");
347 printk(" machine check in kernel mode.\n");
348#elif defined(CONFIG_440A)
349 printk("Machine check in kernel mode.\n");
350 if (reason & ESR_IMCP){
351 printk("Instruction Synchronous Machine Check exception\n");
352 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
353 }
354 else {
355 u32 mcsr = mfspr(SPRN_MCSR);
356 if (mcsr & MCSR_IB)
357 printk("Instruction Read PLB Error\n");
358 if (mcsr & MCSR_DRB)
359 printk("Data Read PLB Error\n");
360 if (mcsr & MCSR_DWB)
361 printk("Data Write PLB Error\n");
362 if (mcsr & MCSR_TLBP)
363 printk("TLB Parity Error\n");
364 if (mcsr & MCSR_ICP){
365 flush_instruction_cache();
366 printk("I-Cache Parity Error\n");
367 }
368 if (mcsr & MCSR_DCSP)
369 printk("D-Cache Search Parity Error\n");
370 if (mcsr & MCSR_DCFP)
371 printk("D-Cache Flush Parity Error\n");
372 if (mcsr & MCSR_IMPE)
373 printk("Machine Check exception is imprecise\n");
374
375 /* Clear MCSR */
376 mtspr(SPRN_MCSR, mcsr);
377 }
378#elif defined (CONFIG_E500)
379 printk("Machine check in kernel mode.\n");
380 printk("Caused by (from MCSR=%lx): ", reason);
381
382 if (reason & MCSR_MCP)
383 printk("Machine Check Signal\n");
384 if (reason & MCSR_ICPERR)
385 printk("Instruction Cache Parity Error\n");
386 if (reason & MCSR_DCP_PERR)
387 printk("Data Cache Push Parity Error\n");
388 if (reason & MCSR_DCPERR)
389 printk("Data Cache Parity Error\n");
390 if (reason & MCSR_GL_CI)
391 printk("Guarded Load or Cache-Inhibited stwcx.\n");
392 if (reason & MCSR_BUS_IAERR)
393 printk("Bus - Instruction Address Error\n");
394 if (reason & MCSR_BUS_RAERR)
395 printk("Bus - Read Address Error\n");
396 if (reason & MCSR_BUS_WAERR)
397 printk("Bus - Write Address Error\n");
398 if (reason & MCSR_BUS_IBERR)
399 printk("Bus - Instruction Data Error\n");
400 if (reason & MCSR_BUS_RBERR)
401 printk("Bus - Read Data Bus Error\n");
402 if (reason & MCSR_BUS_WBERR)
403 printk("Bus - Read Data Bus Error\n");
404 if (reason & MCSR_BUS_IPERR)
405 printk("Bus - Instruction Parity Error\n");
406 if (reason & MCSR_BUS_RPERR)
407 printk("Bus - Read Parity Error\n");
408#elif defined (CONFIG_E200)
409 printk("Machine check in kernel mode.\n");
410 printk("Caused by (from MCSR=%lx): ", reason);
411
412 if (reason & MCSR_MCP)
413 printk("Machine Check Signal\n");
414 if (reason & MCSR_CP_PERR)
415 printk("Cache Push Parity Error\n");
416 if (reason & MCSR_CPERR)
417 printk("Cache Parity Error\n");
418 if (reason & MCSR_EXCP_ERR)
419 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
420 if (reason & MCSR_BUS_IRERR)
421 printk("Bus - Read Bus Error on instruction fetch\n");
422 if (reason & MCSR_BUS_DRERR)
423 printk("Bus - Read Bus Error on data load\n");
424 if (reason & MCSR_BUS_WRERR)
425 printk("Bus - Write Bus Error on buffered store or cache line push\n");
426#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
427 printk("Machine check in kernel mode.\n");
428 printk("Caused by (from SRR1=%lx): ", reason);
429 switch (reason & 0x601F0000) {
430 case 0x80000:
431 printk("Machine check signal\n");
432 break;
433 case 0: /* for 601 */
434 case 0x40000:
435 case 0x140000: /* 7450 MSS error and TEA */
436 printk("Transfer error ack signal\n");
437 break;
438 case 0x20000:
439 printk("Data parity error signal\n");
440 break;
441 case 0x10000:
442 printk("Address parity error signal\n");
443 break;
444 case 0x20000000:
445 printk("L1 Data Cache error\n");
446 break;
447 case 0x40000000:
448 printk("L1 Instruction Cache error\n");
449 break;
450 case 0x00100000:
451 printk("L2 data cache parity error\n");
452 break;
453 default:
454 printk("Unknown values in msr\n");
455 }
456#endif /* CONFIG_4xx */
457
458 /*
459 * Optional platform-provided routine to print out
460 * additional info, e.g. bus error registers.
461 */
462 platform_machine_check(regs);
14cf11af
PM		 463
464 if (debugger_fault_handler(regs))
465 return;
8dad3f92 466 die("Machine check", regs, SIGBUS);
14cf11af
PM		 467
468 /* Must die if the interrupt is not recoverable */
469 if (!(regs->msr & MSR_RI))
470 panic("Unrecoverable Machine check");
471}
472
473void SMIException(struct pt_regs *regs)
474{
475 die("System Management Interrupt", regs, SIGABRT);
476}
477
dc1c1ca3 478void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 479{
480 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
481 regs->nip, regs->msr, regs->trap);
482
483 _exception(SIGTRAP, regs, 0, 0);
484}
485
dc1c1ca3 486void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 487{
488 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
489 5, SIGTRAP) == NOTIFY_STOP)
490 return;
491 if (debugger_iabr_match(regs))
492 return;
493 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
494}
495
496void RunModeException(struct pt_regs *regs)
497{
498 _exception(SIGTRAP, regs, 0, 0);
499}
500
8dad3f92 501void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af
PM		 502{
503 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
504
505 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
506 5, SIGTRAP) == NOTIFY_STOP)
507 return;
508 if (debugger_sstep(regs))
509 return;
510
511 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
512}
513
514/*
515 * After we have successfully emulated an instruction, we have to
516 * check if the instruction was being single-stepped, and if so,
517 * pretend we got a single-step exception. This was pointed out
518 * by Kumar Gala. -- paulus
519 */
8dad3f92 520static void emulate_single_step(struct pt_regs *regs)
14cf11af
PM		 521{
522 if (single_stepping(regs)) {
523 clear_single_step(regs);
524 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
525 }
526}
527
dc1c1ca3
SR		 528static void parse_fpe(struct pt_regs *regs)
529{
530 int code = 0;
531 unsigned long fpscr;
532
dc1c1ca3 533 flush_fp_to_thread(current);
dc1c1ca3 534
25c8a78b 535 fpscr = current->thread.fpscr.val;
dc1c1ca3
SR		 536
537 /* Invalid operation */
538 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
539 code = FPE_FLTINV;
540
541 /* Overflow */
542 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
543 code = FPE_FLTOVF;
544
545 /* Underflow */
546 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
547 code = FPE_FLTUND;
548
549 /* Divide by zero */
550 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
551 code = FPE_FLTDIV;
552
553 /* Inexact result */
554 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
555 code = FPE_FLTRES;
556
557 _exception(SIGFPE, regs, code, regs->nip);
558}
559
560/*
561 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 562 * provide the PVR to user applications using the mfspr rd, PVR.
563 * Return non-zero if we can't emulate, or -EFAULT if the associated
564 * memory access caused an access fault. Return zero on success.
565 *
566 * There are a couple of ways to do this, either "decode" the instruction
567 * or directly match lots of bits. In this case, matching lots of
568 * bits is faster and easier.
86417780 569 *
14cf11af
PM		 570 */
571#define INST_MFSPR_PVR 0x7c1f42a6
572#define INST_MFSPR_PVR_MASK 0xfc1fffff
573
574#define INST_DCBA 0x7c0005ec
575#define INST_DCBA_MASK 0x7c0007fe
576
577#define INST_MCRXR 0x7c000400
578#define INST_MCRXR_MASK 0x7c0007fe
579
580#define INST_STRING 0x7c00042a
581#define INST_STRING_MASK 0x7c0007fe
582#define INST_STRING_GEN_MASK 0x7c00067e
583#define INST_LSWI 0x7c0004aa
584#define INST_LSWX 0x7c00042a
585#define INST_STSWI 0x7c0005aa
586#define INST_STSWX 0x7c00052a
587
588static int emulate_string_inst(struct pt_regs *regs, u32 instword)
589{
590 u8 rT = (instword >> 21) & 0x1f;
591 u8 rA = (instword >> 16) & 0x1f;
592 u8 NB_RB = (instword >> 11) & 0x1f;
593 u32 num_bytes;
594 unsigned long EA;
595 int pos = 0;
596
597 /* Early out if we are an invalid form of lswx */
598 if ((instword & INST_STRING_MASK) == INST_LSWX)
599 if ((rT == rA) || (rT == NB_RB))
600 return -EINVAL;
601
602 EA = (rA == 0) ? 0 : regs->gpr[rA];
603
604 switch (instword & INST_STRING_MASK) {
605 case INST_LSWX:
606 case INST_STSWX:
607 EA += NB_RB;
608 num_bytes = regs->xer & 0x7f;
609 break;
610 case INST_LSWI:
611 case INST_STSWI:
612 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 while (num_bytes != 0)
619 {
620 u8 val;
621 u32 shift = 8 * (3 - (pos & 0x3));
622
623 switch ((instword & INST_STRING_MASK)) {
624 case INST_LSWX:
625 case INST_LSWI:
626 if (get_user(val, (u8 __user *)EA))
627 return -EFAULT;
628 /* first time updating this reg,
629 * zero it out */
630 if (pos == 0)
631 regs->gpr[rT] = 0;
632 regs->gpr[rT] |= val << shift;
633 break;
634 case INST_STSWI:
635 case INST_STSWX:
636 val = regs->gpr[rT] >> shift;
637 if (put_user(val, (u8 __user *)EA))
638 return -EFAULT;
639 break;
640 }
641 /* move EA to next address */
642 EA += 1;
643 num_bytes--;
644
645 /* manage our position within the register */
646 if (++pos == 4) {
647 pos = 0;
648 if (++rT == 32)
649 rT = 0;
650 }
651 }
652
653 return 0;
654}
655
656static int emulate_instruction(struct pt_regs *regs)
657{
658 u32 instword;
659 u32 rd;
660
661 if (!user_mode(regs))
662 return -EINVAL;
663 CHECK_FULL_REGS(regs);
664
665 if (get_user(instword, (u32 __user *)(regs->nip)))
666 return -EFAULT;
667
668 /* Emulate the mfspr rD, PVR. */
669 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
670 rd = (instword >> 21) & 0x1f;
671 regs->gpr[rd] = mfspr(SPRN_PVR);
672 return 0;
673 }
674
675 /* Emulating the dcba insn is just a no-op. */
8dad3f92 676 if ((instword & INST_DCBA_MASK) == INST_DCBA)
14cf11af
PM		 677 return 0;
678
679 /* Emulate the mcrxr insn. */
680 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
86417780 681 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 682 unsigned long msk = 0xf0000000UL >> shift;
683
684 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
685 regs->xer &= ~0xf0000000UL;
686 return 0;
687 }
688
689 /* Emulate load/store string insn. */
690 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
691 return emulate_string_inst(regs, instword);
692
693 return -EINVAL;
694}
695
696/*
697 * Look through the list of trap instructions that are used for BUG(),
698 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know
699 * that the exception was caused by a trap instruction of some kind.
700 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
701 * otherwise.
702 */
703extern struct bug_entry __start___bug_table[], __stop___bug_table[];
704
705#ifndef CONFIG_MODULES
706#define module_find_bug(x) NULL
707#endif
708
709struct bug_entry *find_bug(unsigned long bugaddr)
710{
711 struct bug_entry *bug;
712
713 for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
714 if (bugaddr == bug->bug_addr)
715 return bug;
716 return module_find_bug(bugaddr);
717}
718
dc1c1ca3 719static int check_bug_trap(struct pt_regs *regs)
14cf11af
PM		 720{
721 struct bug_entry *bug;
722 unsigned long addr;
723
724 if (regs->msr & MSR_PR)
725 return 0; /* not in kernel */
726 addr = regs->nip; /* address of trap instruction */
727 if (addr < PAGE_OFFSET)
728 return 0;
729 bug = find_bug(regs->nip);
730 if (bug == NULL)
731 return 0;
732 if (bug->line & BUG_WARNING_TRAP) {
733 /* this is a WARN_ON rather than BUG/BUG_ON */
104dd65f 734 printk(KERN_ERR "Badness in %s at %s:%ld\n",
14cf11af
PM		 735 bug->function, bug->file,
736 bug->line & ~BUG_WARNING_TRAP);
737 dump_stack();
738 return 1;
739 }
104dd65f 740 printk(KERN_CRIT "kernel BUG in %s at %s:%ld!\n",
14cf11af
PM		 741 bug->function, bug->file, bug->line);
742
743 return 0;
744}
745
8dad3f92 746void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 747{
748 unsigned int reason = get_reason(regs);
749 extern int do_mathemu(struct pt_regs *regs);
750
8dad3f92 751#ifdef CONFIG_MATH_EMULATION
14cf11af
PM		 752 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
753 * but there seems to be a hardware bug on the 405GP (RevD)
754 * that means ESR is sometimes set incorrectly - either to
755 * ESR_DST (!?) or 0. In the process of chasing this with the
756 * hardware people - not sure if it can happen on any illegal
757 * instruction or only on FP instructions, whether there is a
758 * pattern to occurences etc. -dgibson 31/Mar/2003 */
759 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
760 emulate_single_step(regs);
761 return;
762 }
8dad3f92 763#endif /* CONFIG_MATH_EMULATION */
14cf11af 764
dc1c1ca3
SR		 765 if (reason & REASON_FP) {
766 /* IEEE FP exception */
767 parse_fpe(regs);
8dad3f92
PM		 768 return;
769 }
770 if (reason & REASON_TRAP) {
14cf11af 771 /* trap exception */
dc1c1ca3
SR		 772 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
773 == NOTIFY_STOP)
774 return;
14cf11af
PM		 775 if (debugger_bpt(regs))
776 return;
777 if (check_bug_trap(regs)) {
778 regs->nip += 4;
779 return;
780 }
8dad3f92
PM		 781 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
782 return;
783 }
784
cd8a5673
PM		 785 local_irq_enable();
786
8dad3f92
PM		 787 /* Try to emulate it if we should. */
788 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 789 switch (emulate_instruction(regs)) {
790 case 0:
791 regs->nip += 4;
792 emulate_single_step(regs);
8dad3f92 793 return;
14cf11af
PM		 794 case -EFAULT:
795 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 796 return;
14cf11af
PM		 797 }
798 }
8dad3f92
PM		 799
800 if (reason & REASON_PRIVILEGED)
801 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
802 else
803 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 804}
805
dc1c1ca3 806void alignment_exception(struct pt_regs *regs)
14cf11af
PM		 807{
808 int fixed;
809
810 fixed = fix_alignment(regs);
811
812 if (fixed == 1) {
813 regs->nip += 4; /* skip over emulated instruction */
814 emulate_single_step(regs);
815 return;
816 }
817
dc1c1ca3 818 /* Operand address was bad */
14cf11af
PM		 819 if (fixed == -EFAULT) {
820 if (user_mode(regs))
8dad3f92 821 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
14cf11af
PM		 822 else
823 /* Search exception table */
824 bad_page_fault(regs, regs->dar, SIGSEGV);
825 return;
826 }
8dad3f92 827 _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
14cf11af
PM		 828}
829
830void StackOverflow(struct pt_regs *regs)
831{
832 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
833 current, regs->gpr[1]);
834 debugger(regs);
835 show_regs(regs);
836 panic("kernel stack overflow");
837}
838
839void nonrecoverable_exception(struct pt_regs *regs)
840{
841 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
842 regs->nip, regs->msr);
843 debugger(regs);
844 die("nonrecoverable exception", regs, SIGKILL);
845}
846
847void trace_syscall(struct pt_regs *regs)
848{
849 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
850 current, current->pid, regs->nip, regs->link, regs->gpr[0],
851 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
852}
dc1c1ca3 853
dc1c1ca3
SR		 854void kernel_fp_unavailable_exception(struct pt_regs *regs)
855{
856 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
857 "%lx at %lx\n", regs->trap, regs->nip);
858 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
859}
dc1c1ca3
SR		 860
861void altivec_unavailable_exception(struct pt_regs *regs)
862{
8dad3f92 863#if !defined(CONFIG_ALTIVEC)
dc1c1ca3
SR		 864 if (user_mode(regs)) {
865 /* A user program has executed an altivec instruction,
866 but this kernel doesn't support altivec. */
867 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
868 return;
869 }
870#endif
dc1c1ca3
SR		 871 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
872 "%lx at %lx\n", regs->trap, regs->nip);
873 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 874}
875
dc1c1ca3
SR		 876void performance_monitor_exception(struct pt_regs *regs)
877{
878 perf_irq(regs);
879}
dc1c1ca3 880
8dad3f92 881#ifdef CONFIG_8xx
14cf11af
PM		 882void SoftwareEmulation(struct pt_regs *regs)
883{
884 extern int do_mathemu(struct pt_regs *);
885 extern int Soft_emulate_8xx(struct pt_regs *);
886 int errcode;
887
888 CHECK_FULL_REGS(regs);
889
890 if (!user_mode(regs)) {
891 debugger(regs);
892 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
893 }
894
895#ifdef CONFIG_MATH_EMULATION
896 errcode = do_mathemu(regs);
897#else
898 errcode = Soft_emulate_8xx(regs);
899#endif
900 if (errcode) {
901 if (errcode > 0)
902 _exception(SIGFPE, regs, 0, 0);
903 else if (errcode == -EFAULT)
904 _exception(SIGSEGV, regs, 0, 0);
905 else
906 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
907 } else
908 emulate_single_step(regs);
909}
8dad3f92 910#endif /* CONFIG_8xx */
14cf11af
PM		 911
912#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
913
914void DebugException(struct pt_regs *regs, unsigned long debug_status)
915{
916 if (debug_status & DBSR_IC) { /* instruction completion */
917 regs->msr &= ~MSR_DE;
918 if (user_mode(regs)) {
919 current->thread.dbcr0 &= ~DBCR0_IC;
920 } else {
921 /* Disable instruction completion */
922 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
923 /* Clear the instruction completion event */
924 mtspr(SPRN_DBSR, DBSR_IC);
925 if (debugger_sstep(regs))
926 return;
927 }
928 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
929 }
930}
931#endif /* CONFIG_4xx || CONFIG_BOOKE */
932
933#if !defined(CONFIG_TAU_INT)
934void TAUException(struct pt_regs *regs)
935{
936 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
937 regs->nip, regs->msr, regs->trap, print_tainted());
938}
939#endif /* CONFIG_INT_TAU */
14cf11af
PM		 940
941#ifdef CONFIG_ALTIVEC
dc1c1ca3 942void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 943{
944 int err;
945
14cf11af
PM		 946 if (!user_mode(regs)) {
947 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
948 " at %lx\n", regs->nip);
8dad3f92 949 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 950 }
951
dc1c1ca3 952 flush_altivec_to_thread(current);
dc1c1ca3 953
14cf11af
PM		 954 err = emulate_altivec(regs);
955 if (err == 0) {
956 regs->nip += 4; /* skip emulated instruction */
957 emulate_single_step(regs);
958 return;
959 }
960
961 if (err == -EFAULT) {
962 /* got an error reading the instruction */
963 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
964 } else {
965 /* didn't recognize the instruction */
966 /* XXX quick hack for now: set the non-Java bit in the VSCR */
967 if (printk_ratelimit())
968 printk(KERN_ERR "Unrecognized altivec instruction "
969 "in %s at %lx\n", current->comm, regs->nip);
970 current->thread.vscr.u[3] |= 0x10000;
971 }
972}
973#endif /* CONFIG_ALTIVEC */
974
14cf11af
PM		 975#ifdef CONFIG_FSL_BOOKE
976void CacheLockingException(struct pt_regs *regs, unsigned long address,
977 unsigned long error_code)
978{
979 /* We treat cache locking instructions from the user
980 * as priv ops, in the future we could try to do
981 * something smarter
982 */
983 if (error_code & (ESR_DLK|ESR_ILK))
984 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
985 return;
986}
987#endif /* CONFIG_FSL_BOOKE */
988
989#ifdef CONFIG_SPE
990void SPEFloatingPointException(struct pt_regs *regs)
991{
992 unsigned long spefscr;
993 int fpexc_mode;
994 int code = 0;
995
996 spefscr = current->thread.spefscr;
997 fpexc_mode = current->thread.fpexc_mode;
998
999 /* Hardware does not neccessarily set sticky
1000 * underflow/overflow/invalid flags */
1001 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1002 code = FPE_FLTOVF;
1003 spefscr |= SPEFSCR_FOVFS;
1004 }
1005 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1006 code = FPE_FLTUND;
1007 spefscr |= SPEFSCR_FUNFS;
1008 }
1009 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1010 code = FPE_FLTDIV;
1011 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1012 code = FPE_FLTINV;
1013 spefscr |= SPEFSCR_FINVS;
1014 }
1015 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1016 code = FPE_FLTRES;
1017
1018 current->thread.spefscr = spefscr;
1019
1020 _exception(SIGFPE, regs, code, regs->nip);
1021 return;
1022}
1023#endif
1024
dc1c1ca3
SR		 1025/*
1026 * We enter here if we get an unrecoverable exception, that is, one
1027 * that happened at a point where the RI (recoverable interrupt) bit
1028 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1029 * we therefore lost state by taking this exception.
1030 */
1031void unrecoverable_exception(struct pt_regs *regs)
1032{
1033 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1034 regs->trap, regs->nip);
1035 die("Unrecoverable exception", regs, SIGABRT);
1036}
dc1c1ca3 1037
14cf11af
PM		 1038#ifdef CONFIG_BOOKE_WDT
1039/*
1040 * Default handler for a Watchdog exception,
1041 * spins until a reboot occurs
1042 */
1043void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1044{
1045 /* Generic WatchdogHandler, implement your own */
1046 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1047 return;
1048}
1049
1050void WatchdogException(struct pt_regs *regs)
1051{
1052 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1053 WatchdogHandler(regs);
1054}
1055#endif
dc1c1ca3 1056
dc1c1ca3
SR		 1057/*
1058 * We enter here if we discover during exception entry that we are
1059 * running in supervisor mode with a userspace value in the stack pointer.
1060 */
1061void kernel_bad_stack(struct pt_regs *regs)
1062{
1063 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1064 regs->gpr[1], regs->nip);
1065 die("Bad kernel stack pointer", regs, SIGABRT);
1066}
14cf11af
PM		 1067
1068void __init trap_init(void)
1069{
1070}
Linux kernel - Deliverables
This page took 0.127333 seconds and 5 git commands to generate.