Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/stddef.h> | |
23 | #include <linux/unistd.h> | |
8dad3f92 | 24 | #include <linux/ptrace.h> |
14cf11af | 25 | #include <linux/user.h> |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
76462232 | 37 | #include <linux/ratelimit.h> |
ba12eede | 38 | #include <linux/context_tracking.h> |
14cf11af | 39 | |
80947e7c | 40 | #include <asm/emulated_ops.h> |
14cf11af PM |
41 | #include <asm/pgtable.h> |
42 | #include <asm/uaccess.h> | |
14cf11af | 43 | #include <asm/io.h> |
86417780 PM |
44 | #include <asm/machdep.h> |
45 | #include <asm/rtas.h> | |
f7f6f4fe | 46 | #include <asm/pmc.h> |
dc1c1ca3 | 47 | #ifdef CONFIG_PPC32 |
14cf11af | 48 | #include <asm/reg.h> |
86417780 | 49 | #endif |
14cf11af PM |
50 | #ifdef CONFIG_PMAC_BACKLIGHT |
51 | #include <asm/backlight.h> | |
52 | #endif | |
dc1c1ca3 | 53 | #ifdef CONFIG_PPC64 |
86417780 | 54 | #include <asm/firmware.h> |
dc1c1ca3 | 55 | #include <asm/processor.h> |
6ce6c629 | 56 | #include <asm/tm.h> |
dc1c1ca3 | 57 | #endif |
c0ce7d08 | 58 | #include <asm/kexec.h> |
16c57b36 | 59 | #include <asm/ppc-opcode.h> |
cce1f106 | 60 | #include <asm/rio.h> |
ebaeb5ae | 61 | #include <asm/fadump.h> |
ae3a197e | 62 | #include <asm/switch_to.h> |
f54db641 | 63 | #include <asm/tm.h> |
ae3a197e | 64 | #include <asm/debug.h> |
dc1c1ca3 | 65 | |
7dbb922c | 66 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
67 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
68 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
69 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
70 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
71 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 72 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 73 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
74 | |
75 | EXPORT_SYMBOL(__debugger); | |
76 | EXPORT_SYMBOL(__debugger_ipi); | |
77 | EXPORT_SYMBOL(__debugger_bpt); | |
78 | EXPORT_SYMBOL(__debugger_sstep); | |
79 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 80 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
81 | EXPORT_SYMBOL(__debugger_fault_handler); |
82 | #endif | |
83 | ||
8b3c34cf MN |
84 | /* Transactional Memory trap debug */ |
85 | #ifdef TM_DEBUG_SW | |
86 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
87 | #else | |
88 | #define TM_DEBUG(x...) do { } while(0) | |
89 | #endif | |
90 | ||
14cf11af PM |
91 | /* |
92 | * Trap & Exception support | |
93 | */ | |
94 | ||
6031d9d9 | 95 | #ifdef CONFIG_PMAC_BACKLIGHT |
96 | static void pmac_backlight_unblank(void) | |
97 | { | |
98 | mutex_lock(&pmac_backlight_mutex); | |
99 | if (pmac_backlight) { | |
100 | struct backlight_properties *props; | |
101 | ||
102 | props = &pmac_backlight->props; | |
103 | props->brightness = props->max_brightness; | |
104 | props->power = FB_BLANK_UNBLANK; | |
105 | backlight_update_status(pmac_backlight); | |
106 | } | |
107 | mutex_unlock(&pmac_backlight_mutex); | |
108 | } | |
109 | #else | |
110 | static inline void pmac_backlight_unblank(void) { } | |
111 | #endif | |
112 | ||
760ca4dc AB |
113 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
114 | static int die_owner = -1; | |
115 | static unsigned int die_nest_count; | |
116 | static int die_counter; | |
117 | ||
118 | static unsigned __kprobes long oops_begin(struct pt_regs *regs) | |
14cf11af | 119 | { |
760ca4dc | 120 | int cpu; |
34c2a14f | 121 | unsigned long flags; |
14cf11af PM |
122 | |
123 | if (debugger(regs)) | |
124 | return 1; | |
125 | ||
293e4688 | 126 | oops_enter(); |
127 | ||
760ca4dc AB |
128 | /* racy, but better than risking deadlock. */ |
129 | raw_local_irq_save(flags); | |
130 | cpu = smp_processor_id(); | |
131 | if (!arch_spin_trylock(&die_lock)) { | |
132 | if (cpu == die_owner) | |
133 | /* nested oops. should stop eventually */; | |
134 | else | |
135 | arch_spin_lock(&die_lock); | |
34c2a14f | 136 | } |
760ca4dc AB |
137 | die_nest_count++; |
138 | die_owner = cpu; | |
139 | console_verbose(); | |
140 | bust_spinlocks(1); | |
141 | if (machine_is(powermac)) | |
142 | pmac_backlight_unblank(); | |
143 | return flags; | |
144 | } | |
e8222502 | 145 | |
760ca4dc AB |
146 | static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs, |
147 | int signr) | |
148 | { | |
14cf11af | 149 | bust_spinlocks(0); |
760ca4dc | 150 | die_owner = -1; |
373d4d09 | 151 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 152 | die_nest_count--; |
58154c8c AB |
153 | oops_exit(); |
154 | printk("\n"); | |
760ca4dc AB |
155 | if (!die_nest_count) |
156 | /* Nest count reaches zero, release the lock. */ | |
157 | arch_spin_unlock(&die_lock); | |
158 | raw_local_irq_restore(flags); | |
cc532915 | 159 | |
ebaeb5ae MS |
160 | crash_fadump(regs, "die oops"); |
161 | ||
9b00ac06 AB |
162 | /* |
163 | * A system reset (0x100) is a request to dump, so we always send | |
164 | * it through the crashdump code. | |
165 | */ | |
166 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 167 | crash_kexec(regs); |
9b00ac06 AB |
168 | |
169 | /* | |
170 | * We aren't the primary crash CPU. We need to send it | |
171 | * to a holding pattern to avoid it ending up in the panic | |
172 | * code. | |
173 | */ | |
174 | crash_kexec_secondary(regs); | |
175 | } | |
14cf11af | 176 | |
760ca4dc AB |
177 | if (!signr) |
178 | return; | |
179 | ||
58154c8c AB |
180 | /* |
181 | * While our oops output is serialised by a spinlock, output | |
182 | * from panic() called below can race and corrupt it. If we | |
183 | * know we are going to panic, delay for 1 second so we have a | |
184 | * chance to get clean backtraces from all CPUs that are oopsing. | |
185 | */ | |
186 | if (in_interrupt() || panic_on_oops || !current->pid || | |
187 | is_global_init(current)) { | |
188 | mdelay(MSEC_PER_SEC); | |
189 | } | |
190 | ||
14cf11af PM |
191 | if (in_interrupt()) |
192 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 193 | if (panic_on_oops) |
012c437d | 194 | panic("Fatal exception"); |
760ca4dc AB |
195 | do_exit(signr); |
196 | } | |
cea6a4ba | 197 | |
760ca4dc AB |
198 | static int __kprobes __die(const char *str, struct pt_regs *regs, long err) |
199 | { | |
200 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
201 | #ifdef CONFIG_PREEMPT | |
202 | printk("PREEMPT "); | |
203 | #endif | |
204 | #ifdef CONFIG_SMP | |
205 | printk("SMP NR_CPUS=%d ", NR_CPUS); | |
206 | #endif | |
207 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
208 | printk("DEBUG_PAGEALLOC "); | |
209 | #endif | |
210 | #ifdef CONFIG_NUMA | |
211 | printk("NUMA "); | |
212 | #endif | |
213 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); | |
214 | ||
215 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
216 | return 1; | |
217 | ||
218 | print_modules(); | |
219 | show_regs(regs); | |
14cf11af PM |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
760ca4dc AB |
224 | void die(const char *str, struct pt_regs *regs, long err) |
225 | { | |
226 | unsigned long flags = oops_begin(regs); | |
227 | ||
228 | if (__die(str, regs, err)) | |
229 | err = 0; | |
230 | oops_end(flags, regs, err); | |
231 | } | |
232 | ||
25baa35b ON |
233 | void user_single_step_siginfo(struct task_struct *tsk, |
234 | struct pt_regs *regs, siginfo_t *info) | |
235 | { | |
236 | memset(info, 0, sizeof(*info)); | |
237 | info->si_signo = SIGTRAP; | |
238 | info->si_code = TRAP_TRACE; | |
239 | info->si_addr = (void __user *)regs->nip; | |
240 | } | |
241 | ||
14cf11af PM |
242 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
243 | { | |
244 | siginfo_t info; | |
d0c3d534 OJ |
245 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
246 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
247 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
248 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
249 | |
250 | if (!user_mode(regs)) { | |
760ca4dc AB |
251 | die("Exception in kernel mode", regs, signr); |
252 | return; | |
253 | } | |
254 | ||
255 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
256 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
257 | current->comm, current->pid, signr, | |
258 | addr, regs->nip, regs->link, code); | |
259 | } | |
14cf11af | 260 | |
a3512b2d | 261 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
262 | local_irq_enable(); |
263 | ||
41ab5266 | 264 | current->thread.trap_nr = code; |
14cf11af PM |
265 | memset(&info, 0, sizeof(info)); |
266 | info.si_signo = signr; | |
267 | info.si_code = code; | |
268 | info.si_addr = (void __user *) addr; | |
269 | force_sig_info(signr, &info, current); | |
14cf11af PM |
270 | } |
271 | ||
272 | #ifdef CONFIG_PPC64 | |
273 | void system_reset_exception(struct pt_regs *regs) | |
274 | { | |
275 | /* See if any machine dependent calls */ | |
c902be71 AB |
276 | if (ppc_md.system_reset_exception) { |
277 | if (ppc_md.system_reset_exception(regs)) | |
278 | return; | |
279 | } | |
14cf11af | 280 | |
8dad3f92 | 281 | die("System Reset", regs, SIGABRT); |
14cf11af PM |
282 | |
283 | /* Must die if the interrupt is not recoverable */ | |
284 | if (!(regs->msr & MSR_RI)) | |
285 | panic("Unrecoverable System Reset"); | |
286 | ||
287 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
288 | } | |
289 | #endif | |
290 | ||
291 | /* | |
292 | * I/O accesses can cause machine checks on powermacs. | |
293 | * Check if the NIP corresponds to the address of a sync | |
294 | * instruction for which there is an entry in the exception | |
295 | * table. | |
296 | * Note that the 601 only takes a machine check on TEA | |
297 | * (transfer error ack) signal assertion, and does not | |
298 | * set any of the top 16 bits of SRR1. | |
299 | * -- paulus. | |
300 | */ | |
301 | static inline int check_io_access(struct pt_regs *regs) | |
302 | { | |
68a64357 | 303 | #ifdef CONFIG_PPC32 |
14cf11af PM |
304 | unsigned long msr = regs->msr; |
305 | const struct exception_table_entry *entry; | |
306 | unsigned int *nip = (unsigned int *)regs->nip; | |
307 | ||
308 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
309 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
310 | /* | |
311 | * Check that it's a sync instruction, or somewhere | |
312 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
313 | * As the address is in the exception table | |
314 | * we should be able to read the instr there. | |
315 | * For the debug message, we look at the preceding | |
316 | * load or store. | |
317 | */ | |
318 | if (*nip == 0x60000000) /* nop */ | |
319 | nip -= 2; | |
320 | else if (*nip == 0x4c00012c) /* isync */ | |
321 | --nip; | |
322 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
323 | /* sync or twi */ | |
324 | unsigned int rb; | |
325 | ||
326 | --nip; | |
327 | rb = (*nip >> 11) & 0x1f; | |
328 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
329 | (*nip & 0x100)? "OUT to": "IN from", | |
330 | regs->gpr[rb] - _IO_BASE, nip); | |
331 | regs->msr |= MSR_RI; | |
332 | regs->nip = entry->fixup; | |
333 | return 1; | |
334 | } | |
335 | } | |
68a64357 | 336 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
337 | return 0; |
338 | } | |
339 | ||
172ae2e7 | 340 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
341 | /* On 4xx, the reason for the machine check or program exception |
342 | is in the ESR. */ | |
343 | #define get_reason(regs) ((regs)->dsisr) | |
344 | #ifndef CONFIG_FSL_BOOKE | |
345 | #define get_mc_reason(regs) ((regs)->dsisr) | |
346 | #else | |
fe04b112 | 347 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
14cf11af PM |
348 | #endif |
349 | #define REASON_FP ESR_FP | |
350 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
351 | #define REASON_PRIVILEGED ESR_PPR | |
352 | #define REASON_TRAP ESR_PTR | |
353 | ||
354 | /* single-step stuff */ | |
355 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
356 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
357 | ||
358 | #else | |
359 | /* On non-4xx, the reason for the machine check or program | |
360 | exception is in the MSR. */ | |
361 | #define get_reason(regs) ((regs)->msr) | |
362 | #define get_mc_reason(regs) ((regs)->msr) | |
8b3c34cf | 363 | #define REASON_TM 0x200000 |
14cf11af PM |
364 | #define REASON_FP 0x100000 |
365 | #define REASON_ILLEGAL 0x80000 | |
366 | #define REASON_PRIVILEGED 0x40000 | |
367 | #define REASON_TRAP 0x20000 | |
368 | ||
369 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
370 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
371 | #endif | |
372 | ||
47c0bd1a BH |
373 | #if defined(CONFIG_4xx) |
374 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 375 | { |
1a6a4ffe | 376 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 377 | |
14cf11af PM |
378 | if (reason & ESR_IMCP) { |
379 | printk("Instruction"); | |
380 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
381 | } else | |
382 | printk("Data"); | |
383 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
388 | int machine_check_440A(struct pt_regs *regs) | |
389 | { | |
390 | unsigned long reason = get_mc_reason(regs); | |
391 | ||
14cf11af PM |
392 | printk("Machine check in kernel mode.\n"); |
393 | if (reason & ESR_IMCP){ | |
394 | printk("Instruction Synchronous Machine Check exception\n"); | |
395 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
396 | } | |
397 | else { | |
398 | u32 mcsr = mfspr(SPRN_MCSR); | |
399 | if (mcsr & MCSR_IB) | |
400 | printk("Instruction Read PLB Error\n"); | |
401 | if (mcsr & MCSR_DRB) | |
402 | printk("Data Read PLB Error\n"); | |
403 | if (mcsr & MCSR_DWB) | |
404 | printk("Data Write PLB Error\n"); | |
405 | if (mcsr & MCSR_TLBP) | |
406 | printk("TLB Parity Error\n"); | |
407 | if (mcsr & MCSR_ICP){ | |
408 | flush_instruction_cache(); | |
409 | printk("I-Cache Parity Error\n"); | |
410 | } | |
411 | if (mcsr & MCSR_DCSP) | |
412 | printk("D-Cache Search Parity Error\n"); | |
413 | if (mcsr & MCSR_DCFP) | |
414 | printk("D-Cache Flush Parity Error\n"); | |
415 | if (mcsr & MCSR_IMPE) | |
416 | printk("Machine Check exception is imprecise\n"); | |
417 | ||
418 | /* Clear MCSR */ | |
419 | mtspr(SPRN_MCSR, mcsr); | |
420 | } | |
47c0bd1a BH |
421 | return 0; |
422 | } | |
fc5e7097 DK |
423 | |
424 | int machine_check_47x(struct pt_regs *regs) | |
425 | { | |
426 | unsigned long reason = get_mc_reason(regs); | |
427 | u32 mcsr; | |
428 | ||
429 | printk(KERN_ERR "Machine check in kernel mode.\n"); | |
430 | if (reason & ESR_IMCP) { | |
431 | printk(KERN_ERR | |
432 | "Instruction Synchronous Machine Check exception\n"); | |
433 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
434 | return 0; | |
435 | } | |
436 | mcsr = mfspr(SPRN_MCSR); | |
437 | if (mcsr & MCSR_IB) | |
438 | printk(KERN_ERR "Instruction Read PLB Error\n"); | |
439 | if (mcsr & MCSR_DRB) | |
440 | printk(KERN_ERR "Data Read PLB Error\n"); | |
441 | if (mcsr & MCSR_DWB) | |
442 | printk(KERN_ERR "Data Write PLB Error\n"); | |
443 | if (mcsr & MCSR_TLBP) | |
444 | printk(KERN_ERR "TLB Parity Error\n"); | |
445 | if (mcsr & MCSR_ICP) { | |
446 | flush_instruction_cache(); | |
447 | printk(KERN_ERR "I-Cache Parity Error\n"); | |
448 | } | |
449 | if (mcsr & MCSR_DCSP) | |
450 | printk(KERN_ERR "D-Cache Search Parity Error\n"); | |
451 | if (mcsr & PPC47x_MCSR_GPR) | |
452 | printk(KERN_ERR "GPR Parity Error\n"); | |
453 | if (mcsr & PPC47x_MCSR_FPR) | |
454 | printk(KERN_ERR "FPR Parity Error\n"); | |
455 | if (mcsr & PPC47x_MCSR_IPR) | |
456 | printk(KERN_ERR "Machine Check exception is imprecise\n"); | |
457 | ||
458 | /* Clear MCSR */ | |
459 | mtspr(SPRN_MCSR, mcsr); | |
460 | ||
461 | return 0; | |
462 | } | |
47c0bd1a | 463 | #elif defined(CONFIG_E500) |
fe04b112 SW |
464 | int machine_check_e500mc(struct pt_regs *regs) |
465 | { | |
466 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
467 | unsigned long reason = mcsr; | |
468 | int recoverable = 1; | |
469 | ||
82a9a480 | 470 | if (reason & MCSR_LD) { |
cce1f106 SX |
471 | recoverable = fsl_rio_mcheck_exception(regs); |
472 | if (recoverable == 1) | |
473 | goto silent_out; | |
474 | } | |
475 | ||
fe04b112 SW |
476 | printk("Machine check in kernel mode.\n"); |
477 | printk("Caused by (from MCSR=%lx): ", reason); | |
478 | ||
479 | if (reason & MCSR_MCP) | |
480 | printk("Machine Check Signal\n"); | |
481 | ||
482 | if (reason & MCSR_ICPERR) { | |
483 | printk("Instruction Cache Parity Error\n"); | |
484 | ||
485 | /* | |
486 | * This is recoverable by invalidating the i-cache. | |
487 | */ | |
488 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
489 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
490 | ; | |
491 | ||
492 | /* | |
493 | * This will generally be accompanied by an instruction | |
494 | * fetch error report -- only treat MCSR_IF as fatal | |
495 | * if it wasn't due to an L1 parity error. | |
496 | */ | |
497 | reason &= ~MCSR_IF; | |
498 | } | |
499 | ||
500 | if (reason & MCSR_DCPERR_MC) { | |
501 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
502 | |
503 | /* | |
504 | * In write shadow mode we auto-recover from the error, but it | |
505 | * may still get logged and cause a machine check. We should | |
506 | * only treat the non-write shadow case as non-recoverable. | |
507 | */ | |
508 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
509 | recoverable = 0; | |
fe04b112 SW |
510 | } |
511 | ||
512 | if (reason & MCSR_L2MMU_MHIT) { | |
513 | printk("Hit on multiple TLB entries\n"); | |
514 | recoverable = 0; | |
515 | } | |
516 | ||
517 | if (reason & MCSR_NMI) | |
518 | printk("Non-maskable interrupt\n"); | |
519 | ||
520 | if (reason & MCSR_IF) { | |
521 | printk("Instruction Fetch Error Report\n"); | |
522 | recoverable = 0; | |
523 | } | |
524 | ||
525 | if (reason & MCSR_LD) { | |
526 | printk("Load Error Report\n"); | |
527 | recoverable = 0; | |
528 | } | |
529 | ||
530 | if (reason & MCSR_ST) { | |
531 | printk("Store Error Report\n"); | |
532 | recoverable = 0; | |
533 | } | |
534 | ||
535 | if (reason & MCSR_LDG) { | |
536 | printk("Guarded Load Error Report\n"); | |
537 | recoverable = 0; | |
538 | } | |
539 | ||
540 | if (reason & MCSR_TLBSYNC) | |
541 | printk("Simultaneous tlbsync operations\n"); | |
542 | ||
543 | if (reason & MCSR_BSL2_ERR) { | |
544 | printk("Level 2 Cache Error\n"); | |
545 | recoverable = 0; | |
546 | } | |
547 | ||
548 | if (reason & MCSR_MAV) { | |
549 | u64 addr; | |
550 | ||
551 | addr = mfspr(SPRN_MCAR); | |
552 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
553 | ||
554 | printk("Machine Check %s Address: %#llx\n", | |
555 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
556 | } | |
557 | ||
cce1f106 | 558 | silent_out: |
fe04b112 SW |
559 | mtspr(SPRN_MCSR, mcsr); |
560 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
561 | } | |
562 | ||
47c0bd1a BH |
563 | int machine_check_e500(struct pt_regs *regs) |
564 | { | |
565 | unsigned long reason = get_mc_reason(regs); | |
566 | ||
cce1f106 SX |
567 | if (reason & MCSR_BUS_RBERR) { |
568 | if (fsl_rio_mcheck_exception(regs)) | |
569 | return 1; | |
570 | } | |
571 | ||
14cf11af PM |
572 | printk("Machine check in kernel mode.\n"); |
573 | printk("Caused by (from MCSR=%lx): ", reason); | |
574 | ||
575 | if (reason & MCSR_MCP) | |
576 | printk("Machine Check Signal\n"); | |
577 | if (reason & MCSR_ICPERR) | |
578 | printk("Instruction Cache Parity Error\n"); | |
579 | if (reason & MCSR_DCP_PERR) | |
580 | printk("Data Cache Push Parity Error\n"); | |
581 | if (reason & MCSR_DCPERR) | |
582 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
583 | if (reason & MCSR_BUS_IAERR) |
584 | printk("Bus - Instruction Address Error\n"); | |
585 | if (reason & MCSR_BUS_RAERR) | |
586 | printk("Bus - Read Address Error\n"); | |
587 | if (reason & MCSR_BUS_WAERR) | |
588 | printk("Bus - Write Address Error\n"); | |
589 | if (reason & MCSR_BUS_IBERR) | |
590 | printk("Bus - Instruction Data Error\n"); | |
591 | if (reason & MCSR_BUS_RBERR) | |
592 | printk("Bus - Read Data Bus Error\n"); | |
593 | if (reason & MCSR_BUS_WBERR) | |
594 | printk("Bus - Read Data Bus Error\n"); | |
595 | if (reason & MCSR_BUS_IPERR) | |
596 | printk("Bus - Instruction Parity Error\n"); | |
597 | if (reason & MCSR_BUS_RPERR) | |
598 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
599 | |
600 | return 0; | |
601 | } | |
4490c06b KG |
602 | |
603 | int machine_check_generic(struct pt_regs *regs) | |
604 | { | |
605 | return 0; | |
606 | } | |
47c0bd1a BH |
607 | #elif defined(CONFIG_E200) |
608 | int machine_check_e200(struct pt_regs *regs) | |
609 | { | |
610 | unsigned long reason = get_mc_reason(regs); | |
611 | ||
14cf11af PM |
612 | printk("Machine check in kernel mode.\n"); |
613 | printk("Caused by (from MCSR=%lx): ", reason); | |
614 | ||
615 | if (reason & MCSR_MCP) | |
616 | printk("Machine Check Signal\n"); | |
617 | if (reason & MCSR_CP_PERR) | |
618 | printk("Cache Push Parity Error\n"); | |
619 | if (reason & MCSR_CPERR) | |
620 | printk("Cache Parity Error\n"); | |
621 | if (reason & MCSR_EXCP_ERR) | |
622 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
623 | if (reason & MCSR_BUS_IRERR) | |
624 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
625 | if (reason & MCSR_BUS_DRERR) | |
626 | printk("Bus - Read Bus Error on data load\n"); | |
627 | if (reason & MCSR_BUS_WRERR) | |
628 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
629 | |
630 | return 0; | |
631 | } | |
632 | #else | |
633 | int machine_check_generic(struct pt_regs *regs) | |
634 | { | |
635 | unsigned long reason = get_mc_reason(regs); | |
636 | ||
14cf11af PM |
637 | printk("Machine check in kernel mode.\n"); |
638 | printk("Caused by (from SRR1=%lx): ", reason); | |
639 | switch (reason & 0x601F0000) { | |
640 | case 0x80000: | |
641 | printk("Machine check signal\n"); | |
642 | break; | |
643 | case 0: /* for 601 */ | |
644 | case 0x40000: | |
645 | case 0x140000: /* 7450 MSS error and TEA */ | |
646 | printk("Transfer error ack signal\n"); | |
647 | break; | |
648 | case 0x20000: | |
649 | printk("Data parity error signal\n"); | |
650 | break; | |
651 | case 0x10000: | |
652 | printk("Address parity error signal\n"); | |
653 | break; | |
654 | case 0x20000000: | |
655 | printk("L1 Data Cache error\n"); | |
656 | break; | |
657 | case 0x40000000: | |
658 | printk("L1 Instruction Cache error\n"); | |
659 | break; | |
660 | case 0x00100000: | |
661 | printk("L2 data cache parity error\n"); | |
662 | break; | |
663 | default: | |
664 | printk("Unknown values in msr\n"); | |
665 | } | |
75918a4b OJ |
666 | return 0; |
667 | } | |
47c0bd1a | 668 | #endif /* everything else */ |
75918a4b OJ |
669 | |
670 | void machine_check_exception(struct pt_regs *regs) | |
671 | { | |
ba12eede | 672 | enum ctx_state prev_state = exception_enter(); |
75918a4b OJ |
673 | int recover = 0; |
674 | ||
89713ed1 AB |
675 | __get_cpu_var(irq_stat).mce_exceptions++; |
676 | ||
47c0bd1a BH |
677 | /* See if any machine dependent calls. In theory, we would want |
678 | * to call the CPU first, and call the ppc_md. one if the CPU | |
679 | * one returns a positive number. However there is existing code | |
680 | * that assumes the board gets a first chance, so let's keep it | |
681 | * that way for now and fix things later. --BenH. | |
682 | */ | |
75918a4b OJ |
683 | if (ppc_md.machine_check_exception) |
684 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
685 | else if (cur_cpu_spec->machine_check) |
686 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 687 | |
47c0bd1a | 688 | if (recover > 0) |
ba12eede | 689 | goto bail; |
75918a4b | 690 | |
75918a4b | 691 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) |
47c0bd1a BH |
692 | /* the qspan pci read routines can cause machine checks -- Cort |
693 | * | |
694 | * yuck !!! that totally needs to go away ! There are better ways | |
695 | * to deal with that than having a wart in the mcheck handler. | |
696 | * -- BenH | |
697 | */ | |
75918a4b | 698 | bad_page_fault(regs, regs->dar, SIGBUS); |
ba12eede | 699 | goto bail; |
75918a4b OJ |
700 | #endif |
701 | ||
a443506b | 702 | if (debugger_fault_handler(regs)) |
ba12eede | 703 | goto bail; |
75918a4b OJ |
704 | |
705 | if (check_io_access(regs)) | |
ba12eede | 706 | goto bail; |
75918a4b | 707 | |
8dad3f92 | 708 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
709 | |
710 | /* Must die if the interrupt is not recoverable */ | |
711 | if (!(regs->msr & MSR_RI)) | |
712 | panic("Unrecoverable Machine check"); | |
ba12eede LZ |
713 | |
714 | bail: | |
715 | exception_exit(prev_state); | |
14cf11af PM |
716 | } |
717 | ||
718 | void SMIException(struct pt_regs *regs) | |
719 | { | |
720 | die("System Management Interrupt", regs, SIGABRT); | |
721 | } | |
722 | ||
dc1c1ca3 | 723 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 724 | { |
ba12eede LZ |
725 | enum ctx_state prev_state = exception_enter(); |
726 | ||
14cf11af PM |
727 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
728 | regs->nip, regs->msr, regs->trap); | |
729 | ||
730 | _exception(SIGTRAP, regs, 0, 0); | |
ba12eede LZ |
731 | |
732 | exception_exit(prev_state); | |
14cf11af PM |
733 | } |
734 | ||
dc1c1ca3 | 735 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 736 | { |
ba12eede LZ |
737 | enum ctx_state prev_state = exception_enter(); |
738 | ||
14cf11af PM |
739 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
740 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 741 | goto bail; |
14cf11af | 742 | if (debugger_iabr_match(regs)) |
ba12eede | 743 | goto bail; |
14cf11af | 744 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
745 | |
746 | bail: | |
747 | exception_exit(prev_state); | |
14cf11af PM |
748 | } |
749 | ||
750 | void RunModeException(struct pt_regs *regs) | |
751 | { | |
752 | _exception(SIGTRAP, regs, 0, 0); | |
753 | } | |
754 | ||
8dad3f92 | 755 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af | 756 | { |
ba12eede LZ |
757 | enum ctx_state prev_state = exception_enter(); |
758 | ||
2538c2d0 | 759 | clear_single_step(regs); |
14cf11af PM |
760 | |
761 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
762 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 763 | goto bail; |
14cf11af | 764 | if (debugger_sstep(regs)) |
ba12eede | 765 | goto bail; |
14cf11af PM |
766 | |
767 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
768 | |
769 | bail: | |
770 | exception_exit(prev_state); | |
14cf11af PM |
771 | } |
772 | ||
773 | /* | |
774 | * After we have successfully emulated an instruction, we have to | |
775 | * check if the instruction was being single-stepped, and if so, | |
776 | * pretend we got a single-step exception. This was pointed out | |
777 | * by Kumar Gala. -- paulus | |
778 | */ | |
8dad3f92 | 779 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 780 | { |
2538c2d0 P |
781 | if (single_stepping(regs)) |
782 | single_step_exception(regs); | |
14cf11af PM |
783 | } |
784 | ||
5fad293b | 785 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 786 | { |
5fad293b | 787 | int ret = 0; |
dc1c1ca3 SR |
788 | |
789 | /* Invalid operation */ | |
790 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 791 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
792 | |
793 | /* Overflow */ | |
794 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 795 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
796 | |
797 | /* Underflow */ | |
798 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 799 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
800 | |
801 | /* Divide by zero */ | |
802 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 803 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
804 | |
805 | /* Inexact result */ | |
806 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
807 | ret = FPE_FLTRES; |
808 | ||
809 | return ret; | |
810 | } | |
811 | ||
812 | static void parse_fpe(struct pt_regs *regs) | |
813 | { | |
814 | int code = 0; | |
815 | ||
816 | flush_fp_to_thread(current); | |
817 | ||
818 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
819 | |
820 | _exception(SIGFPE, regs, code, regs->nip); | |
821 | } | |
822 | ||
823 | /* | |
824 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
825 | * provide the PVR to user applications using the mfspr rd, PVR. |
826 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
827 | * memory access caused an access fault. Return zero on success. | |
828 | * | |
829 | * There are a couple of ways to do this, either "decode" the instruction | |
830 | * or directly match lots of bits. In this case, matching lots of | |
831 | * bits is faster and easier. | |
86417780 | 832 | * |
14cf11af | 833 | */ |
14cf11af PM |
834 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
835 | { | |
836 | u8 rT = (instword >> 21) & 0x1f; | |
837 | u8 rA = (instword >> 16) & 0x1f; | |
838 | u8 NB_RB = (instword >> 11) & 0x1f; | |
839 | u32 num_bytes; | |
840 | unsigned long EA; | |
841 | int pos = 0; | |
842 | ||
843 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 844 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
845 | if ((rT == rA) || (rT == NB_RB)) |
846 | return -EINVAL; | |
847 | ||
848 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
849 | ||
16c57b36 KG |
850 | switch (instword & PPC_INST_STRING_MASK) { |
851 | case PPC_INST_LSWX: | |
852 | case PPC_INST_STSWX: | |
14cf11af PM |
853 | EA += NB_RB; |
854 | num_bytes = regs->xer & 0x7f; | |
855 | break; | |
16c57b36 KG |
856 | case PPC_INST_LSWI: |
857 | case PPC_INST_STSWI: | |
14cf11af PM |
858 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
859 | break; | |
860 | default: | |
861 | return -EINVAL; | |
862 | } | |
863 | ||
864 | while (num_bytes != 0) | |
865 | { | |
866 | u8 val; | |
867 | u32 shift = 8 * (3 - (pos & 0x3)); | |
868 | ||
16c57b36 KG |
869 | switch ((instword & PPC_INST_STRING_MASK)) { |
870 | case PPC_INST_LSWX: | |
871 | case PPC_INST_LSWI: | |
14cf11af PM |
872 | if (get_user(val, (u8 __user *)EA)) |
873 | return -EFAULT; | |
874 | /* first time updating this reg, | |
875 | * zero it out */ | |
876 | if (pos == 0) | |
877 | regs->gpr[rT] = 0; | |
878 | regs->gpr[rT] |= val << shift; | |
879 | break; | |
16c57b36 KG |
880 | case PPC_INST_STSWI: |
881 | case PPC_INST_STSWX: | |
14cf11af PM |
882 | val = regs->gpr[rT] >> shift; |
883 | if (put_user(val, (u8 __user *)EA)) | |
884 | return -EFAULT; | |
885 | break; | |
886 | } | |
887 | /* move EA to next address */ | |
888 | EA += 1; | |
889 | num_bytes--; | |
890 | ||
891 | /* manage our position within the register */ | |
892 | if (++pos == 4) { | |
893 | pos = 0; | |
894 | if (++rT == 32) | |
895 | rT = 0; | |
896 | } | |
897 | } | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
c3412dcb WS |
902 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
903 | { | |
904 | u32 ra,rs; | |
905 | unsigned long tmp; | |
906 | ||
907 | ra = (instword >> 16) & 0x1f; | |
908 | rs = (instword >> 21) & 0x1f; | |
909 | ||
910 | tmp = regs->gpr[rs]; | |
911 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
912 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
913 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
914 | regs->gpr[ra] = tmp; | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
c1469f13 KG |
919 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
920 | { | |
921 | u8 rT = (instword >> 21) & 0x1f; | |
922 | u8 rA = (instword >> 16) & 0x1f; | |
923 | u8 rB = (instword >> 11) & 0x1f; | |
924 | u8 BC = (instword >> 6) & 0x1f; | |
925 | u8 bit; | |
926 | unsigned long tmp; | |
927 | ||
928 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
929 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
930 | ||
931 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
6ce6c629 MN |
936 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
937 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
938 | { | |
939 | /* If we're emulating a load/store in an active transaction, we cannot | |
940 | * emulate it as the kernel operates in transaction suspended context. | |
941 | * We need to abort the transaction. This creates a persistent TM | |
942 | * abort so tell the user what caused it with a new code. | |
943 | */ | |
944 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
945 | tm_enable(); | |
946 | tm_abort(cause); | |
947 | return true; | |
948 | } | |
949 | return false; | |
950 | } | |
951 | #else | |
952 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
953 | { | |
954 | return false; | |
955 | } | |
956 | #endif | |
957 | ||
14cf11af PM |
958 | static int emulate_instruction(struct pt_regs *regs) |
959 | { | |
960 | u32 instword; | |
961 | u32 rd; | |
962 | ||
fab5db97 | 963 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
964 | return -EINVAL; |
965 | CHECK_FULL_REGS(regs); | |
966 | ||
967 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
968 | return -EFAULT; | |
969 | ||
970 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 971 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 972 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
973 | rd = (instword >> 21) & 0x1f; |
974 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
975 | return 0; | |
976 | } | |
977 | ||
978 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 979 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 980 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 981 | return 0; |
80947e7c | 982 | } |
14cf11af PM |
983 | |
984 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 985 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 986 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
987 | unsigned long msk = 0xf0000000UL >> shift; |
988 | ||
eecff81d | 989 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
990 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
991 | regs->xer &= ~0xf0000000UL; | |
992 | return 0; | |
993 | } | |
994 | ||
995 | /* Emulate load/store string insn. */ | |
80947e7c | 996 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
997 | if (tm_abort_check(regs, |
998 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
999 | return -EINVAL; | |
eecff81d | 1000 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 1001 | return emulate_string_inst(regs, instword); |
80947e7c | 1002 | } |
14cf11af | 1003 | |
c3412dcb | 1004 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 1005 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 1006 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
1007 | return emulate_popcntb_inst(regs, instword); |
1008 | } | |
1009 | ||
c1469f13 | 1010 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 1011 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 1012 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
1013 | return emulate_isel(regs, instword); |
1014 | } | |
1015 | ||
efcac658 AK |
1016 | #ifdef CONFIG_PPC64 |
1017 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
1018 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
1019 | PPC_INST_MFSPR_DSCR_USER) || | |
1020 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
1021 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
1022 | cpu_has_feature(CPU_FTR_DSCR)) { |
1023 | PPC_WARN_EMULATED(mfdscr, regs); | |
1024 | rd = (instword >> 21) & 0x1f; | |
1025 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
1026 | return 0; | |
1027 | } | |
1028 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
1029 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
1030 | PPC_INST_MTSPR_DSCR_USER) || | |
1031 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
1032 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
1033 | cpu_has_feature(CPU_FTR_DSCR)) { |
1034 | PPC_WARN_EMULATED(mtdscr, regs); | |
1035 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 1036 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 1037 | current->thread.dscr_inherit = 1; |
00ca0de0 | 1038 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
1039 | return 0; |
1040 | } | |
1041 | #endif | |
1042 | ||
14cf11af PM |
1043 | return -EINVAL; |
1044 | } | |
1045 | ||
73c9ceab | 1046 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1047 | { |
73c9ceab | 1048 | return is_kernel_addr(addr); |
14cf11af PM |
1049 | } |
1050 | ||
8dad3f92 | 1051 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af | 1052 | { |
ba12eede | 1053 | enum ctx_state prev_state = exception_enter(); |
14cf11af PM |
1054 | unsigned int reason = get_reason(regs); |
1055 | extern int do_mathemu(struct pt_regs *regs); | |
1056 | ||
aa42c69c | 1057 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1058 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1059 | |
dc1c1ca3 SR |
1060 | if (reason & REASON_FP) { |
1061 | /* IEEE FP exception */ | |
1062 | parse_fpe(regs); | |
ba12eede | 1063 | goto bail; |
8dad3f92 PM |
1064 | } |
1065 | if (reason & REASON_TRAP) { | |
ba797b28 JW |
1066 | /* Debugger is first in line to stop recursive faults in |
1067 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1068 | if (debugger_bpt(regs)) | |
ba12eede | 1069 | goto bail; |
ba797b28 | 1070 | |
14cf11af | 1071 | /* trap exception */ |
dc1c1ca3 SR |
1072 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1073 | == NOTIFY_STOP) | |
ba12eede | 1074 | goto bail; |
73c9ceab JF |
1075 | |
1076 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 1077 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1078 | regs->nip += 4; |
ba12eede | 1079 | goto bail; |
14cf11af | 1080 | } |
8dad3f92 | 1081 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1082 | goto bail; |
8dad3f92 | 1083 | } |
bc2a9408 MN |
1084 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1085 | if (reason & REASON_TM) { | |
1086 | /* This is a TM "Bad Thing Exception" program check. | |
1087 | * This occurs when: | |
1088 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1089 | * transition in TM states. | |
1090 | * - A trechkpt is attempted when transactional. | |
1091 | * - A treclaim is attempted when non transactional. | |
1092 | * - A tend is illegally attempted. | |
1093 | * - writing a TM SPR when transactional. | |
1094 | */ | |
1095 | if (!user_mode(regs) && | |
1096 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { | |
1097 | regs->nip += 4; | |
ba12eede | 1098 | goto bail; |
bc2a9408 MN |
1099 | } |
1100 | /* If usermode caused this, it's done something illegal and | |
1101 | * gets a SIGILL slap on the wrist. We call it an illegal | |
1102 | * operand to distinguish from the instruction just being bad | |
1103 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1104 | * illegal /placement/ of a valid instruction. | |
1105 | */ | |
1106 | if (user_mode(regs)) { | |
1107 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1108 | goto bail; |
bc2a9408 MN |
1109 | } else { |
1110 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1111 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1112 | die("Unrecoverable exception", regs, SIGABRT); | |
1113 | } | |
1114 | } | |
1115 | #endif | |
8dad3f92 | 1116 | |
a3512b2d BH |
1117 | /* We restore the interrupt state now */ |
1118 | if (!arch_irq_disabled_regs(regs)) | |
1119 | local_irq_enable(); | |
cd8a5673 | 1120 | |
04903a30 KG |
1121 | #ifdef CONFIG_MATH_EMULATION |
1122 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
1123 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1124 | * that means ESR is sometimes set incorrectly - either to | |
1125 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1126 | * hardware people - not sure if it can happen on any illegal | |
1127 | * instruction or only on FP instructions, whether there is a | |
25985edc | 1128 | * pattern to occurrences etc. -dgibson 31/Mar/2003 */ |
5fad293b KG |
1129 | switch (do_mathemu(regs)) { |
1130 | case 0: | |
04903a30 | 1131 | emulate_single_step(regs); |
ba12eede | 1132 | goto bail; |
5fad293b KG |
1133 | case 1: { |
1134 | int code = 0; | |
1135 | code = __parse_fpscr(current->thread.fpscr.val); | |
1136 | _exception(SIGFPE, regs, code, regs->nip); | |
ba12eede | 1137 | goto bail; |
5fad293b KG |
1138 | } |
1139 | case -EFAULT: | |
1140 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1141 | goto bail; |
04903a30 | 1142 | } |
5fad293b | 1143 | /* fall through on any other errors */ |
04903a30 KG |
1144 | #endif /* CONFIG_MATH_EMULATION */ |
1145 | ||
8dad3f92 PM |
1146 | /* Try to emulate it if we should. */ |
1147 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1148 | switch (emulate_instruction(regs)) { |
1149 | case 0: | |
1150 | regs->nip += 4; | |
1151 | emulate_single_step(regs); | |
ba12eede | 1152 | goto bail; |
14cf11af PM |
1153 | case -EFAULT: |
1154 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1155 | goto bail; |
14cf11af PM |
1156 | } |
1157 | } | |
8dad3f92 PM |
1158 | |
1159 | if (reason & REASON_PRIVILEGED) | |
1160 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1161 | else | |
1162 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1163 | |
1164 | bail: | |
1165 | exception_exit(prev_state); | |
14cf11af PM |
1166 | } |
1167 | ||
dc1c1ca3 | 1168 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1169 | { |
ba12eede | 1170 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1171 | int sig, code, fixed = 0; |
14cf11af | 1172 | |
a3512b2d BH |
1173 | /* We restore the interrupt state now */ |
1174 | if (!arch_irq_disabled_regs(regs)) | |
1175 | local_irq_enable(); | |
1176 | ||
6ce6c629 MN |
1177 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1178 | goto bail; | |
1179 | ||
e9370ae1 PM |
1180 | /* we don't implement logging of alignment exceptions */ |
1181 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1182 | fixed = fix_alignment(regs); | |
14cf11af PM |
1183 | |
1184 | if (fixed == 1) { | |
1185 | regs->nip += 4; /* skip over emulated instruction */ | |
1186 | emulate_single_step(regs); | |
ba12eede | 1187 | goto bail; |
14cf11af PM |
1188 | } |
1189 | ||
dc1c1ca3 | 1190 | /* Operand address was bad */ |
14cf11af | 1191 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1192 | sig = SIGSEGV; |
1193 | code = SEGV_ACCERR; | |
1194 | } else { | |
1195 | sig = SIGBUS; | |
1196 | code = BUS_ADRALN; | |
14cf11af | 1197 | } |
4393c4f6 BH |
1198 | if (user_mode(regs)) |
1199 | _exception(sig, regs, code, regs->dar); | |
1200 | else | |
1201 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1202 | |
1203 | bail: | |
1204 | exception_exit(prev_state); | |
14cf11af PM |
1205 | } |
1206 | ||
1207 | void StackOverflow(struct pt_regs *regs) | |
1208 | { | |
1209 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1210 | current, regs->gpr[1]); | |
1211 | debugger(regs); | |
1212 | show_regs(regs); | |
1213 | panic("kernel stack overflow"); | |
1214 | } | |
1215 | ||
1216 | void nonrecoverable_exception(struct pt_regs *regs) | |
1217 | { | |
1218 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1219 | regs->nip, regs->msr); | |
1220 | debugger(regs); | |
1221 | die("nonrecoverable exception", regs, SIGKILL); | |
1222 | } | |
1223 | ||
1224 | void trace_syscall(struct pt_regs *regs) | |
1225 | { | |
1226 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 1227 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
1228 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
1229 | } | |
dc1c1ca3 | 1230 | |
dc1c1ca3 SR |
1231 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1232 | { | |
ba12eede LZ |
1233 | enum ctx_state prev_state = exception_enter(); |
1234 | ||
dc1c1ca3 SR |
1235 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1236 | "%lx at %lx\n", regs->trap, regs->nip); | |
1237 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1238 | |
1239 | exception_exit(prev_state); | |
dc1c1ca3 | 1240 | } |
dc1c1ca3 SR |
1241 | |
1242 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1243 | { | |
ba12eede LZ |
1244 | enum ctx_state prev_state = exception_enter(); |
1245 | ||
dc1c1ca3 SR |
1246 | if (user_mode(regs)) { |
1247 | /* A user program has executed an altivec instruction, | |
1248 | but this kernel doesn't support altivec. */ | |
1249 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1250 | goto bail; |
dc1c1ca3 | 1251 | } |
6c4841c2 | 1252 | |
dc1c1ca3 SR |
1253 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1254 | "%lx at %lx\n", regs->trap, regs->nip); | |
1255 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1256 | |
1257 | bail: | |
1258 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1259 | } |
1260 | ||
ce48b210 MN |
1261 | void vsx_unavailable_exception(struct pt_regs *regs) |
1262 | { | |
1263 | if (user_mode(regs)) { | |
1264 | /* A user program has executed an vsx instruction, | |
1265 | but this kernel doesn't support vsx. */ | |
1266 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1267 | return; | |
1268 | } | |
1269 | ||
1270 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1271 | "%lx at %lx\n", regs->trap, regs->nip); | |
1272 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1273 | } | |
1274 | ||
d0c0c9a1 MN |
1275 | void tm_unavailable_exception(struct pt_regs *regs) |
1276 | { | |
1277 | /* We restore the interrupt state now */ | |
1278 | if (!arch_irq_disabled_regs(regs)) | |
1279 | local_irq_enable(); | |
1280 | ||
1281 | /* Currently we never expect a TMU exception. Catch | |
1282 | * this and kill the process! | |
1283 | */ | |
1284 | printk(KERN_EMERG "Unexpected TM unavailable exception at %lx " | |
1285 | "(msr %lx)\n", | |
1286 | regs->nip, regs->msr); | |
1287 | ||
1288 | if (user_mode(regs)) { | |
1289 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1290 | return; | |
1291 | } | |
1292 | ||
1293 | die("Unexpected TM unavailable exception", regs, SIGABRT); | |
1294 | } | |
1295 | ||
f54db641 MN |
1296 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1297 | ||
1298 | extern void do_load_up_fpu(struct pt_regs *regs); | |
1299 | ||
1300 | void fp_unavailable_tm(struct pt_regs *regs) | |
1301 | { | |
1302 | /* Note: This does not handle any kind of FP laziness. */ | |
1303 | ||
1304 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1305 | regs->nip, regs->msr); | |
1306 | tm_enable(); | |
1307 | ||
1308 | /* We can only have got here if the task started using FP after | |
1309 | * beginning the transaction. So, the transactional regs are just a | |
1310 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1311 | * as we're enabling FP for the process; it will return, abort the | |
1312 | * transaction, and probably retry but now with FP enabled. So the | |
1313 | * checkpointed FP registers need to be loaded. | |
1314 | */ | |
1315 | tm_reclaim(¤t->thread, current->thread.regs->msr, | |
1316 | TM_CAUSE_FAC_UNAV); | |
1317 | /* Reclaim didn't save out any FPRs to transact_fprs. */ | |
1318 | ||
1319 | /* Enable FP for the task: */ | |
1320 | regs->msr |= (MSR_FP | current->thread.fpexc_mode); | |
1321 | ||
1322 | /* This loads and recheckpoints the FP registers from | |
1323 | * thread.fpr[]. They will remain in registers after the | |
1324 | * checkpoint so we don't need to reload them after. | |
1325 | */ | |
1326 | tm_recheckpoint(¤t->thread, regs->msr); | |
1327 | } | |
1328 | ||
1329 | #ifdef CONFIG_ALTIVEC | |
1330 | extern void do_load_up_altivec(struct pt_regs *regs); | |
1331 | ||
1332 | void altivec_unavailable_tm(struct pt_regs *regs) | |
1333 | { | |
1334 | /* See the comments in fp_unavailable_tm(). This function operates | |
1335 | * the same way. | |
1336 | */ | |
1337 | ||
1338 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1339 | "MSR=%lx\n", | |
1340 | regs->nip, regs->msr); | |
1341 | tm_enable(); | |
1342 | tm_reclaim(¤t->thread, current->thread.regs->msr, | |
1343 | TM_CAUSE_FAC_UNAV); | |
1344 | regs->msr |= MSR_VEC; | |
1345 | tm_recheckpoint(¤t->thread, regs->msr); | |
1346 | current->thread.used_vr = 1; | |
1347 | } | |
1348 | #endif | |
1349 | ||
1350 | #ifdef CONFIG_VSX | |
1351 | void vsx_unavailable_tm(struct pt_regs *regs) | |
1352 | { | |
1353 | /* See the comments in fp_unavailable_tm(). This works similarly, | |
1354 | * though we're loading both FP and VEC registers in here. | |
1355 | * | |
1356 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1357 | * regs. Either way, set MSR_VSX. | |
1358 | */ | |
1359 | ||
1360 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1361 | "MSR=%lx\n", | |
1362 | regs->nip, regs->msr); | |
1363 | ||
1364 | tm_enable(); | |
1365 | /* This reclaims FP and/or VR regs if they're already enabled */ | |
1366 | tm_reclaim(¤t->thread, current->thread.regs->msr, | |
1367 | TM_CAUSE_FAC_UNAV); | |
1368 | ||
1369 | regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | | |
1370 | MSR_VSX; | |
1371 | /* This loads & recheckpoints FP and VRs. */ | |
1372 | tm_recheckpoint(¤t->thread, regs->msr); | |
1373 | current->thread.used_vsr = 1; | |
1374 | } | |
1375 | #endif | |
1376 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
1377 | ||
dc1c1ca3 SR |
1378 | void performance_monitor_exception(struct pt_regs *regs) |
1379 | { | |
89713ed1 AB |
1380 | __get_cpu_var(irq_stat).pmu_irqs++; |
1381 | ||
dc1c1ca3 SR |
1382 | perf_irq(regs); |
1383 | } | |
dc1c1ca3 | 1384 | |
8dad3f92 | 1385 | #ifdef CONFIG_8xx |
14cf11af PM |
1386 | void SoftwareEmulation(struct pt_regs *regs) |
1387 | { | |
1388 | extern int do_mathemu(struct pt_regs *); | |
1389 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 1390 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1391 | int errcode; |
5dd57a13 | 1392 | #endif |
14cf11af PM |
1393 | |
1394 | CHECK_FULL_REGS(regs); | |
1395 | ||
1396 | if (!user_mode(regs)) { | |
1397 | debugger(regs); | |
1398 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
1399 | } | |
1400 | ||
1401 | #ifdef CONFIG_MATH_EMULATION | |
1402 | errcode = do_mathemu(regs); | |
80947e7c | 1403 | if (errcode >= 0) |
eecff81d | 1404 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
1405 | |
1406 | switch (errcode) { | |
1407 | case 0: | |
1408 | emulate_single_step(regs); | |
1409 | return; | |
1410 | case 1: { | |
1411 | int code = 0; | |
1412 | code = __parse_fpscr(current->thread.fpscr.val); | |
1413 | _exception(SIGFPE, regs, code, regs->nip); | |
1414 | return; | |
1415 | } | |
1416 | case -EFAULT: | |
1417 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1418 | return; | |
1419 | default: | |
1420 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1421 | return; | |
1422 | } | |
1423 | ||
5dd57a13 | 1424 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1425 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1426 | if (errcode >= 0) |
eecff81d | 1427 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1428 | |
5fad293b KG |
1429 | switch (errcode) { |
1430 | case 0: | |
14cf11af | 1431 | emulate_single_step(regs); |
5fad293b KG |
1432 | return; |
1433 | case 1: | |
1434 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1435 | return; | |
1436 | case -EFAULT: | |
1437 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1438 | return; | |
1439 | } | |
5dd57a13 SW |
1440 | #else |
1441 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1442 | #endif |
14cf11af | 1443 | } |
8dad3f92 | 1444 | #endif /* CONFIG_8xx */ |
14cf11af | 1445 | |
172ae2e7 | 1446 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1447 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1448 | { | |
1449 | int changed = 0; | |
1450 | /* | |
1451 | * Determine the cause of the debug event, clear the | |
1452 | * event flags and send a trap to the handler. Torez | |
1453 | */ | |
1454 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1455 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1456 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1457 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1458 | #endif | |
1459 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1460 | 5); | |
1461 | changed |= 0x01; | |
1462 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1463 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1464 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1465 | 6); | |
1466 | changed |= 0x01; | |
1467 | } else if (debug_status & DBSR_IAC1) { | |
1468 | current->thread.dbcr0 &= ~DBCR0_IAC1; | |
1469 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | |
1470 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1471 | 1); | |
1472 | changed |= 0x01; | |
1473 | } else if (debug_status & DBSR_IAC2) { | |
1474 | current->thread.dbcr0 &= ~DBCR0_IAC2; | |
1475 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | |
1476 | 2); | |
1477 | changed |= 0x01; | |
1478 | } else if (debug_status & DBSR_IAC3) { | |
1479 | current->thread.dbcr0 &= ~DBCR0_IAC3; | |
1480 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | |
1481 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1482 | 3); | |
1483 | changed |= 0x01; | |
1484 | } else if (debug_status & DBSR_IAC4) { | |
1485 | current->thread.dbcr0 &= ~DBCR0_IAC4; | |
1486 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | |
1487 | 4); | |
1488 | changed |= 0x01; | |
1489 | } | |
1490 | /* | |
1491 | * At the point this routine was called, the MSR(DE) was turned off. | |
1492 | * Check all other debug flags and see if that bit needs to be turned | |
1493 | * back on or not. | |
1494 | */ | |
1495 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | |
1496 | regs->msr |= MSR_DE; | |
1497 | else | |
1498 | /* Make sure the IDM flag is off */ | |
1499 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1500 | ||
1501 | if (changed & 0x01) | |
1502 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | |
1503 | } | |
14cf11af | 1504 | |
f8279621 | 1505 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1506 | { |
3bffb652 DK |
1507 | current->thread.dbsr = debug_status; |
1508 | ||
ec097c84 RM |
1509 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1510 | * on server, it stops on the target of the branch. In order to simulate | |
1511 | * the server behaviour, we thus restart right away with a single step | |
1512 | * instead of stopping here when hitting a BT | |
1513 | */ | |
1514 | if (debug_status & DBSR_BT) { | |
1515 | regs->msr &= ~MSR_DE; | |
1516 | ||
1517 | /* Disable BT */ | |
1518 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1519 | /* Clear the BT event */ | |
1520 | mtspr(SPRN_DBSR, DBSR_BT); | |
1521 | ||
1522 | /* Do the single step trick only when coming from userspace */ | |
1523 | if (user_mode(regs)) { | |
1524 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1525 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1526 | regs->msr |= MSR_DE; | |
1527 | return; | |
1528 | } | |
1529 | ||
1530 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1531 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1532 | return; | |
1533 | } | |
1534 | if (debugger_sstep(regs)) | |
1535 | return; | |
1536 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1537 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1538 | |
1539 | /* Disable instruction completion */ | |
1540 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1541 | /* Clear the instruction completion event */ | |
1542 | mtspr(SPRN_DBSR, DBSR_IC); | |
1543 | ||
1544 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1545 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1546 | return; | |
1547 | } | |
1548 | ||
1549 | if (debugger_sstep(regs)) | |
1550 | return; | |
1551 | ||
d6a61bfc | 1552 | if (user_mode(regs)) { |
3bffb652 | 1553 | current->thread.dbcr0 &= ~DBCR0_IC; |
3bffb652 DK |
1554 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, |
1555 | current->thread.dbcr1)) | |
1556 | regs->msr |= MSR_DE; | |
1557 | else | |
1558 | /* Make sure the IDM bit is off */ | |
1559 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
d6a61bfc | 1560 | } |
3bffb652 DK |
1561 | |
1562 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1563 | } else | |
1564 | handle_debug(regs, debug_status); | |
14cf11af | 1565 | } |
172ae2e7 | 1566 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1567 | |
1568 | #if !defined(CONFIG_TAU_INT) | |
1569 | void TAUException(struct pt_regs *regs) | |
1570 | { | |
1571 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1572 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1573 | } | |
1574 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1575 | |
1576 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1577 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1578 | { |
1579 | int err; | |
1580 | ||
14cf11af PM |
1581 | if (!user_mode(regs)) { |
1582 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1583 | " at %lx\n", regs->nip); | |
8dad3f92 | 1584 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1585 | } |
1586 | ||
dc1c1ca3 | 1587 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1588 | |
eecff81d | 1589 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1590 | err = emulate_altivec(regs); |
1591 | if (err == 0) { | |
1592 | regs->nip += 4; /* skip emulated instruction */ | |
1593 | emulate_single_step(regs); | |
1594 | return; | |
1595 | } | |
1596 | ||
1597 | if (err == -EFAULT) { | |
1598 | /* got an error reading the instruction */ | |
1599 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1600 | } else { | |
1601 | /* didn't recognize the instruction */ | |
1602 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1603 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1604 | "in %s at %lx\n", current->comm, regs->nip); | |
14cf11af PM |
1605 | current->thread.vscr.u[3] |= 0x10000; |
1606 | } | |
1607 | } | |
1608 | #endif /* CONFIG_ALTIVEC */ | |
1609 | ||
ce48b210 MN |
1610 | #ifdef CONFIG_VSX |
1611 | void vsx_assist_exception(struct pt_regs *regs) | |
1612 | { | |
1613 | if (!user_mode(regs)) { | |
1614 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1615 | " at %lx\n", regs->nip); | |
1616 | die("Kernel VSX assist exception", regs, SIGILL); | |
1617 | } | |
1618 | ||
1619 | flush_vsx_to_thread(current); | |
1620 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1621 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1622 | } | |
1623 | #endif /* CONFIG_VSX */ | |
1624 | ||
14cf11af PM |
1625 | #ifdef CONFIG_FSL_BOOKE |
1626 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1627 | unsigned long error_code) | |
1628 | { | |
1629 | /* We treat cache locking instructions from the user | |
1630 | * as priv ops, in the future we could try to do | |
1631 | * something smarter | |
1632 | */ | |
1633 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1634 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1635 | return; | |
1636 | } | |
1637 | #endif /* CONFIG_FSL_BOOKE */ | |
1638 | ||
1639 | #ifdef CONFIG_SPE | |
1640 | void SPEFloatingPointException(struct pt_regs *regs) | |
1641 | { | |
6a800f36 | 1642 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1643 | unsigned long spefscr; |
1644 | int fpexc_mode; | |
1645 | int code = 0; | |
6a800f36 LY |
1646 | int err; |
1647 | ||
685659ee | 1648 | flush_spe_to_thread(current); |
14cf11af PM |
1649 | |
1650 | spefscr = current->thread.spefscr; | |
1651 | fpexc_mode = current->thread.fpexc_mode; | |
1652 | ||
14cf11af PM |
1653 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1654 | code = FPE_FLTOVF; | |
14cf11af PM |
1655 | } |
1656 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1657 | code = FPE_FLTUND; | |
14cf11af PM |
1658 | } |
1659 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1660 | code = FPE_FLTDIV; | |
1661 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1662 | code = FPE_FLTINV; | |
14cf11af PM |
1663 | } |
1664 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1665 | code = FPE_FLTRES; | |
1666 | ||
6a800f36 LY |
1667 | err = do_spe_mathemu(regs); |
1668 | if (err == 0) { | |
1669 | regs->nip += 4; /* skip emulated instruction */ | |
1670 | emulate_single_step(regs); | |
1671 | return; | |
1672 | } | |
1673 | ||
1674 | if (err == -EFAULT) { | |
1675 | /* got an error reading the instruction */ | |
1676 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1677 | } else if (err == -EINVAL) { | |
1678 | /* didn't recognize the instruction */ | |
1679 | printk(KERN_ERR "unrecognized spe instruction " | |
1680 | "in %s at %lx\n", current->comm, regs->nip); | |
1681 | } else { | |
1682 | _exception(SIGFPE, regs, code, regs->nip); | |
1683 | } | |
14cf11af | 1684 | |
14cf11af PM |
1685 | return; |
1686 | } | |
6a800f36 LY |
1687 | |
1688 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1689 | { | |
1690 | extern int speround_handler(struct pt_regs *regs); | |
1691 | int err; | |
1692 | ||
1693 | preempt_disable(); | |
1694 | if (regs->msr & MSR_SPE) | |
1695 | giveup_spe(current); | |
1696 | preempt_enable(); | |
1697 | ||
1698 | regs->nip -= 4; | |
1699 | err = speround_handler(regs); | |
1700 | if (err == 0) { | |
1701 | regs->nip += 4; /* skip emulated instruction */ | |
1702 | emulate_single_step(regs); | |
1703 | return; | |
1704 | } | |
1705 | ||
1706 | if (err == -EFAULT) { | |
1707 | /* got an error reading the instruction */ | |
1708 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1709 | } else if (err == -EINVAL) { | |
1710 | /* didn't recognize the instruction */ | |
1711 | printk(KERN_ERR "unrecognized spe instruction " | |
1712 | "in %s at %lx\n", current->comm, regs->nip); | |
1713 | } else { | |
1714 | _exception(SIGFPE, regs, 0, regs->nip); | |
1715 | return; | |
1716 | } | |
1717 | } | |
14cf11af PM |
1718 | #endif |
1719 | ||
dc1c1ca3 SR |
1720 | /* |
1721 | * We enter here if we get an unrecoverable exception, that is, one | |
1722 | * that happened at a point where the RI (recoverable interrupt) bit | |
1723 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1724 | * we therefore lost state by taking this exception. | |
1725 | */ | |
1726 | void unrecoverable_exception(struct pt_regs *regs) | |
1727 | { | |
1728 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1729 | regs->trap, regs->nip); | |
1730 | die("Unrecoverable exception", regs, SIGABRT); | |
1731 | } | |
dc1c1ca3 | 1732 | |
1e18c17a | 1733 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
1734 | /* |
1735 | * Default handler for a Watchdog exception, | |
1736 | * spins until a reboot occurs | |
1737 | */ | |
1738 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1739 | { | |
1740 | /* Generic WatchdogHandler, implement your own */ | |
1741 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1742 | return; | |
1743 | } | |
1744 | ||
1745 | void WatchdogException(struct pt_regs *regs) | |
1746 | { | |
1747 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1748 | WatchdogHandler(regs); | |
1749 | } | |
1750 | #endif | |
dc1c1ca3 | 1751 | |
dc1c1ca3 SR |
1752 | /* |
1753 | * We enter here if we discover during exception entry that we are | |
1754 | * running in supervisor mode with a userspace value in the stack pointer. | |
1755 | */ | |
1756 | void kernel_bad_stack(struct pt_regs *regs) | |
1757 | { | |
1758 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1759 | regs->gpr[1], regs->nip); | |
1760 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1761 | } | |
14cf11af PM |
1762 | |
1763 | void __init trap_init(void) | |
1764 | { | |
1765 | } | |
80947e7c GU |
1766 | |
1767 | ||
1768 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1769 | ||
1770 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1771 | ||
1772 | struct ppc_emulated ppc_emulated = { | |
1773 | #ifdef CONFIG_ALTIVEC | |
1774 | WARN_EMULATED_SETUP(altivec), | |
1775 | #endif | |
1776 | WARN_EMULATED_SETUP(dcba), | |
1777 | WARN_EMULATED_SETUP(dcbz), | |
1778 | WARN_EMULATED_SETUP(fp_pair), | |
1779 | WARN_EMULATED_SETUP(isel), | |
1780 | WARN_EMULATED_SETUP(mcrxr), | |
1781 | WARN_EMULATED_SETUP(mfpvr), | |
1782 | WARN_EMULATED_SETUP(multiple), | |
1783 | WARN_EMULATED_SETUP(popcntb), | |
1784 | WARN_EMULATED_SETUP(spe), | |
1785 | WARN_EMULATED_SETUP(string), | |
1786 | WARN_EMULATED_SETUP(unaligned), | |
1787 | #ifdef CONFIG_MATH_EMULATION | |
1788 | WARN_EMULATED_SETUP(math), | |
1789 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1790 | WARN_EMULATED_SETUP(8xx), | |
1791 | #endif | |
1792 | #ifdef CONFIG_VSX | |
1793 | WARN_EMULATED_SETUP(vsx), | |
1794 | #endif | |
efcac658 AK |
1795 | #ifdef CONFIG_PPC64 |
1796 | WARN_EMULATED_SETUP(mfdscr), | |
1797 | WARN_EMULATED_SETUP(mtdscr), | |
1798 | #endif | |
80947e7c GU |
1799 | }; |
1800 | ||
1801 | u32 ppc_warn_emulated; | |
1802 | ||
1803 | void ppc_warn_emulated_print(const char *type) | |
1804 | { | |
76462232 CD |
1805 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
1806 | type); | |
80947e7c GU |
1807 | } |
1808 | ||
1809 | static int __init ppc_warn_emulated_init(void) | |
1810 | { | |
1811 | struct dentry *dir, *d; | |
1812 | unsigned int i; | |
1813 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1814 | ||
1815 | if (!powerpc_debugfs_root) | |
1816 | return -ENODEV; | |
1817 | ||
1818 | dir = debugfs_create_dir("emulated_instructions", | |
1819 | powerpc_debugfs_root); | |
1820 | if (!dir) | |
1821 | return -ENOMEM; | |
1822 | ||
1823 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1824 | &ppc_warn_emulated); | |
1825 | if (!d) | |
1826 | goto fail; | |
1827 | ||
1828 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1829 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1830 | (u32 *)&entries[i].val.counter); | |
1831 | if (!d) | |
1832 | goto fail; | |
1833 | } | |
1834 | ||
1835 | return 0; | |
1836 | ||
1837 | fail: | |
1838 | debugfs_remove_recursive(dir); | |
1839 | return -ENOMEM; | |
1840 | } | |
1841 | ||
1842 | device_initcall(ppc_warn_emulated_init); | |
1843 | ||
1844 | #endif /* CONFIG_PPC_EMULATED_STATS */ |