Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af PM |
24 | #include <linux/slab.h> |
25 | #include <linux/user.h> | |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
14cf11af | 37 | |
80947e7c | 38 | #include <asm/emulated_ops.h> |
14cf11af PM |
39 | #include <asm/pgtable.h> |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/io.h> | |
86417780 PM |
43 | #include <asm/machdep.h> |
44 | #include <asm/rtas.h> | |
f7f6f4fe | 45 | #include <asm/pmc.h> |
dc1c1ca3 | 46 | #ifdef CONFIG_PPC32 |
14cf11af | 47 | #include <asm/reg.h> |
86417780 | 48 | #endif |
14cf11af PM |
49 | #ifdef CONFIG_PMAC_BACKLIGHT |
50 | #include <asm/backlight.h> | |
51 | #endif | |
dc1c1ca3 | 52 | #ifdef CONFIG_PPC64 |
86417780 | 53 | #include <asm/firmware.h> |
dc1c1ca3 | 54 | #include <asm/processor.h> |
dc1c1ca3 | 55 | #endif |
c0ce7d08 | 56 | #include <asm/kexec.h> |
16c57b36 | 57 | #include <asm/ppc-opcode.h> |
620165f9 KG |
58 | #ifdef CONFIG_FSL_BOOKE |
59 | #include <asm/dbell.h> | |
60 | #endif | |
dc1c1ca3 | 61 | |
7dbb922c | 62 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
63 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
64 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
65 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
67 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
68 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
69 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
70 | |
71 | EXPORT_SYMBOL(__debugger); | |
72 | EXPORT_SYMBOL(__debugger_ipi); | |
73 | EXPORT_SYMBOL(__debugger_bpt); | |
74 | EXPORT_SYMBOL(__debugger_sstep); | |
75 | EXPORT_SYMBOL(__debugger_iabr_match); | |
76 | EXPORT_SYMBOL(__debugger_dabr_match); | |
77 | EXPORT_SYMBOL(__debugger_fault_handler); | |
78 | #endif | |
79 | ||
14cf11af PM |
80 | /* |
81 | * Trap & Exception support | |
82 | */ | |
83 | ||
6031d9d9 | 84 | #ifdef CONFIG_PMAC_BACKLIGHT |
85 | static void pmac_backlight_unblank(void) | |
86 | { | |
87 | mutex_lock(&pmac_backlight_mutex); | |
88 | if (pmac_backlight) { | |
89 | struct backlight_properties *props; | |
90 | ||
91 | props = &pmac_backlight->props; | |
92 | props->brightness = props->max_brightness; | |
93 | props->power = FB_BLANK_UNBLANK; | |
94 | backlight_update_status(pmac_backlight); | |
95 | } | |
96 | mutex_unlock(&pmac_backlight_mutex); | |
97 | } | |
98 | #else | |
99 | static inline void pmac_backlight_unblank(void) { } | |
100 | #endif | |
101 | ||
14cf11af PM |
102 | int die(const char *str, struct pt_regs *regs, long err) |
103 | { | |
34c2a14f | 104 | static struct { |
105 | spinlock_t lock; | |
106 | u32 lock_owner; | |
107 | int lock_owner_depth; | |
108 | } die = { | |
109 | .lock = __SPIN_LOCK_UNLOCKED(die.lock), | |
110 | .lock_owner = -1, | |
111 | .lock_owner_depth = 0 | |
112 | }; | |
c0ce7d08 | 113 | static int die_counter; |
34c2a14f | 114 | unsigned long flags; |
14cf11af PM |
115 | |
116 | if (debugger(regs)) | |
117 | return 1; | |
118 | ||
293e4688 | 119 | oops_enter(); |
120 | ||
34c2a14f | 121 | if (die.lock_owner != raw_smp_processor_id()) { |
122 | console_verbose(); | |
123 | spin_lock_irqsave(&die.lock, flags); | |
124 | die.lock_owner = smp_processor_id(); | |
125 | die.lock_owner_depth = 0; | |
126 | bust_spinlocks(1); | |
127 | if (machine_is(powermac)) | |
128 | pmac_backlight_unblank(); | |
129 | } else { | |
130 | local_save_flags(flags); | |
131 | } | |
5474c120 | 132 | |
34c2a14f | 133 | if (++die.lock_owner_depth < 3) { |
134 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 135 | #ifdef CONFIG_PREEMPT |
34c2a14f | 136 | printk("PREEMPT "); |
14cf11af PM |
137 | #endif |
138 | #ifdef CONFIG_SMP | |
34c2a14f | 139 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
140 | #endif |
141 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 142 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
143 | #endif |
144 | #ifdef CONFIG_NUMA | |
34c2a14f | 145 | printk("NUMA "); |
14cf11af | 146 | #endif |
ae7f4463 | 147 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 148 | |
66fcb105 AB |
149 | sysfs_printk_last_file(); |
150 | if (notify_die(DIE_OOPS, str, regs, err, 255, | |
151 | SIGSEGV) == NOTIFY_STOP) | |
152 | return 1; | |
153 | ||
34c2a14f | 154 | print_modules(); |
155 | show_regs(regs); | |
156 | } else { | |
157 | printk("Recursive die() failure, output suppressed\n"); | |
158 | } | |
e8222502 | 159 | |
14cf11af | 160 | bust_spinlocks(0); |
34c2a14f | 161 | die.lock_owner = -1; |
bcdcd8e7 | 162 | add_taint(TAINT_DIE); |
34c2a14f | 163 | spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 164 | |
c0ce7d08 DW |
165 | if (kexec_should_crash(current) || |
166 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 167 | crash_kexec(regs); |
c0ce7d08 | 168 | crash_kexec_secondary(regs); |
14cf11af PM |
169 | |
170 | if (in_interrupt()) | |
171 | panic("Fatal exception in interrupt"); | |
172 | ||
cea6a4ba | 173 | if (panic_on_oops) |
012c437d | 174 | panic("Fatal exception"); |
cea6a4ba | 175 | |
293e4688 | 176 | oops_exit(); |
14cf11af PM |
177 | do_exit(err); |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
25baa35b ON |
182 | void user_single_step_siginfo(struct task_struct *tsk, |
183 | struct pt_regs *regs, siginfo_t *info) | |
184 | { | |
185 | memset(info, 0, sizeof(*info)); | |
186 | info->si_signo = SIGTRAP; | |
187 | info->si_code = TRAP_TRACE; | |
188 | info->si_addr = (void __user *)regs->nip; | |
189 | } | |
190 | ||
14cf11af PM |
191 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
192 | { | |
193 | siginfo_t info; | |
d0c3d534 OJ |
194 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
195 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
196 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
197 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
198 | |
199 | if (!user_mode(regs)) { | |
200 | if (die("Exception in kernel mode", regs, signr)) | |
201 | return; | |
d0c3d534 OJ |
202 | } else if (show_unhandled_signals && |
203 | unhandled_signal(current, signr) && | |
204 | printk_ratelimit()) { | |
205 | printk(regs->msr & MSR_SF ? fmt64 : fmt32, | |
206 | current->comm, current->pid, signr, | |
207 | addr, regs->nip, regs->link, code); | |
208 | } | |
14cf11af PM |
209 | |
210 | memset(&info, 0, sizeof(info)); | |
211 | info.si_signo = signr; | |
212 | info.si_code = code; | |
213 | info.si_addr = (void __user *) addr; | |
214 | force_sig_info(signr, &info, current); | |
14cf11af PM |
215 | } |
216 | ||
217 | #ifdef CONFIG_PPC64 | |
218 | void system_reset_exception(struct pt_regs *regs) | |
219 | { | |
220 | /* See if any machine dependent calls */ | |
c902be71 AB |
221 | if (ppc_md.system_reset_exception) { |
222 | if (ppc_md.system_reset_exception(regs)) | |
223 | return; | |
224 | } | |
14cf11af | 225 | |
c0ce7d08 DW |
226 | #ifdef CONFIG_KEXEC |
227 | cpu_set(smp_processor_id(), cpus_in_sr); | |
228 | #endif | |
229 | ||
8dad3f92 | 230 | die("System Reset", regs, SIGABRT); |
14cf11af | 231 | |
eac8392f DW |
232 | /* |
233 | * Some CPUs when released from the debugger will execute this path. | |
234 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
235 | * hung before entering the debugger it will return to the hung | |
236 | * state when exiting this function. This causes a problem in | |
237 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
238 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
239 | * here. If a kdump had not been initiated or we exit the debugger | |
240 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
241 | * will return after 5ms and the CPU returns to its previous state. | |
242 | */ | |
243 | crash_kexec_secondary(regs); | |
244 | ||
14cf11af PM |
245 | /* Must die if the interrupt is not recoverable */ |
246 | if (!(regs->msr & MSR_RI)) | |
247 | panic("Unrecoverable System Reset"); | |
248 | ||
249 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
250 | } | |
251 | #endif | |
252 | ||
253 | /* | |
254 | * I/O accesses can cause machine checks on powermacs. | |
255 | * Check if the NIP corresponds to the address of a sync | |
256 | * instruction for which there is an entry in the exception | |
257 | * table. | |
258 | * Note that the 601 only takes a machine check on TEA | |
259 | * (transfer error ack) signal assertion, and does not | |
260 | * set any of the top 16 bits of SRR1. | |
261 | * -- paulus. | |
262 | */ | |
263 | static inline int check_io_access(struct pt_regs *regs) | |
264 | { | |
68a64357 | 265 | #ifdef CONFIG_PPC32 |
14cf11af PM |
266 | unsigned long msr = regs->msr; |
267 | const struct exception_table_entry *entry; | |
268 | unsigned int *nip = (unsigned int *)regs->nip; | |
269 | ||
270 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
271 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
272 | /* | |
273 | * Check that it's a sync instruction, or somewhere | |
274 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
275 | * As the address is in the exception table | |
276 | * we should be able to read the instr there. | |
277 | * For the debug message, we look at the preceding | |
278 | * load or store. | |
279 | */ | |
280 | if (*nip == 0x60000000) /* nop */ | |
281 | nip -= 2; | |
282 | else if (*nip == 0x4c00012c) /* isync */ | |
283 | --nip; | |
284 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
285 | /* sync or twi */ | |
286 | unsigned int rb; | |
287 | ||
288 | --nip; | |
289 | rb = (*nip >> 11) & 0x1f; | |
290 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
291 | (*nip & 0x100)? "OUT to": "IN from", | |
292 | regs->gpr[rb] - _IO_BASE, nip); | |
293 | regs->msr |= MSR_RI; | |
294 | regs->nip = entry->fixup; | |
295 | return 1; | |
296 | } | |
297 | } | |
68a64357 | 298 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
299 | return 0; |
300 | } | |
301 | ||
302 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
303 | /* On 4xx, the reason for the machine check or program exception | |
304 | is in the ESR. */ | |
305 | #define get_reason(regs) ((regs)->dsisr) | |
306 | #ifndef CONFIG_FSL_BOOKE | |
307 | #define get_mc_reason(regs) ((regs)->dsisr) | |
308 | #else | |
86d7a9a9 | 309 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) |
14cf11af PM |
310 | #endif |
311 | #define REASON_FP ESR_FP | |
312 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
313 | #define REASON_PRIVILEGED ESR_PPR | |
314 | #define REASON_TRAP ESR_PTR | |
315 | ||
316 | /* single-step stuff */ | |
317 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
318 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
319 | ||
320 | #else | |
321 | /* On non-4xx, the reason for the machine check or program | |
322 | exception is in the MSR. */ | |
323 | #define get_reason(regs) ((regs)->msr) | |
324 | #define get_mc_reason(regs) ((regs)->msr) | |
325 | #define REASON_FP 0x100000 | |
326 | #define REASON_ILLEGAL 0x80000 | |
327 | #define REASON_PRIVILEGED 0x40000 | |
328 | #define REASON_TRAP 0x20000 | |
329 | ||
330 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
331 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
332 | #endif | |
333 | ||
47c0bd1a BH |
334 | #if defined(CONFIG_4xx) |
335 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 336 | { |
1a6a4ffe | 337 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 338 | |
14cf11af PM |
339 | if (reason & ESR_IMCP) { |
340 | printk("Instruction"); | |
341 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
342 | } else | |
343 | printk("Data"); | |
344 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
349 | int machine_check_440A(struct pt_regs *regs) | |
350 | { | |
351 | unsigned long reason = get_mc_reason(regs); | |
352 | ||
14cf11af PM |
353 | printk("Machine check in kernel mode.\n"); |
354 | if (reason & ESR_IMCP){ | |
355 | printk("Instruction Synchronous Machine Check exception\n"); | |
356 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
357 | } | |
358 | else { | |
359 | u32 mcsr = mfspr(SPRN_MCSR); | |
360 | if (mcsr & MCSR_IB) | |
361 | printk("Instruction Read PLB Error\n"); | |
362 | if (mcsr & MCSR_DRB) | |
363 | printk("Data Read PLB Error\n"); | |
364 | if (mcsr & MCSR_DWB) | |
365 | printk("Data Write PLB Error\n"); | |
366 | if (mcsr & MCSR_TLBP) | |
367 | printk("TLB Parity Error\n"); | |
368 | if (mcsr & MCSR_ICP){ | |
369 | flush_instruction_cache(); | |
370 | printk("I-Cache Parity Error\n"); | |
371 | } | |
372 | if (mcsr & MCSR_DCSP) | |
373 | printk("D-Cache Search Parity Error\n"); | |
374 | if (mcsr & MCSR_DCFP) | |
375 | printk("D-Cache Flush Parity Error\n"); | |
376 | if (mcsr & MCSR_IMPE) | |
377 | printk("Machine Check exception is imprecise\n"); | |
378 | ||
379 | /* Clear MCSR */ | |
380 | mtspr(SPRN_MCSR, mcsr); | |
381 | } | |
47c0bd1a BH |
382 | return 0; |
383 | } | |
384 | #elif defined(CONFIG_E500) | |
385 | int machine_check_e500(struct pt_regs *regs) | |
386 | { | |
387 | unsigned long reason = get_mc_reason(regs); | |
388 | ||
14cf11af PM |
389 | printk("Machine check in kernel mode.\n"); |
390 | printk("Caused by (from MCSR=%lx): ", reason); | |
391 | ||
392 | if (reason & MCSR_MCP) | |
393 | printk("Machine Check Signal\n"); | |
394 | if (reason & MCSR_ICPERR) | |
395 | printk("Instruction Cache Parity Error\n"); | |
396 | if (reason & MCSR_DCP_PERR) | |
397 | printk("Data Cache Push Parity Error\n"); | |
398 | if (reason & MCSR_DCPERR) | |
399 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
400 | if (reason & MCSR_BUS_IAERR) |
401 | printk("Bus - Instruction Address Error\n"); | |
402 | if (reason & MCSR_BUS_RAERR) | |
403 | printk("Bus - Read Address Error\n"); | |
404 | if (reason & MCSR_BUS_WAERR) | |
405 | printk("Bus - Write Address Error\n"); | |
406 | if (reason & MCSR_BUS_IBERR) | |
407 | printk("Bus - Instruction Data Error\n"); | |
408 | if (reason & MCSR_BUS_RBERR) | |
409 | printk("Bus - Read Data Bus Error\n"); | |
410 | if (reason & MCSR_BUS_WBERR) | |
411 | printk("Bus - Read Data Bus Error\n"); | |
412 | if (reason & MCSR_BUS_IPERR) | |
413 | printk("Bus - Instruction Parity Error\n"); | |
414 | if (reason & MCSR_BUS_RPERR) | |
415 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
416 | |
417 | return 0; | |
418 | } | |
419 | #elif defined(CONFIG_E200) | |
420 | int machine_check_e200(struct pt_regs *regs) | |
421 | { | |
422 | unsigned long reason = get_mc_reason(regs); | |
423 | ||
14cf11af PM |
424 | printk("Machine check in kernel mode.\n"); |
425 | printk("Caused by (from MCSR=%lx): ", reason); | |
426 | ||
427 | if (reason & MCSR_MCP) | |
428 | printk("Machine Check Signal\n"); | |
429 | if (reason & MCSR_CP_PERR) | |
430 | printk("Cache Push Parity Error\n"); | |
431 | if (reason & MCSR_CPERR) | |
432 | printk("Cache Parity Error\n"); | |
433 | if (reason & MCSR_EXCP_ERR) | |
434 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
435 | if (reason & MCSR_BUS_IRERR) | |
436 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
437 | if (reason & MCSR_BUS_DRERR) | |
438 | printk("Bus - Read Bus Error on data load\n"); | |
439 | if (reason & MCSR_BUS_WRERR) | |
440 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
441 | |
442 | return 0; | |
443 | } | |
444 | #else | |
445 | int machine_check_generic(struct pt_regs *regs) | |
446 | { | |
447 | unsigned long reason = get_mc_reason(regs); | |
448 | ||
14cf11af PM |
449 | printk("Machine check in kernel mode.\n"); |
450 | printk("Caused by (from SRR1=%lx): ", reason); | |
451 | switch (reason & 0x601F0000) { | |
452 | case 0x80000: | |
453 | printk("Machine check signal\n"); | |
454 | break; | |
455 | case 0: /* for 601 */ | |
456 | case 0x40000: | |
457 | case 0x140000: /* 7450 MSS error and TEA */ | |
458 | printk("Transfer error ack signal\n"); | |
459 | break; | |
460 | case 0x20000: | |
461 | printk("Data parity error signal\n"); | |
462 | break; | |
463 | case 0x10000: | |
464 | printk("Address parity error signal\n"); | |
465 | break; | |
466 | case 0x20000000: | |
467 | printk("L1 Data Cache error\n"); | |
468 | break; | |
469 | case 0x40000000: | |
470 | printk("L1 Instruction Cache error\n"); | |
471 | break; | |
472 | case 0x00100000: | |
473 | printk("L2 data cache parity error\n"); | |
474 | break; | |
475 | default: | |
476 | printk("Unknown values in msr\n"); | |
477 | } | |
75918a4b OJ |
478 | return 0; |
479 | } | |
47c0bd1a | 480 | #endif /* everything else */ |
75918a4b OJ |
481 | |
482 | void machine_check_exception(struct pt_regs *regs) | |
483 | { | |
484 | int recover = 0; | |
485 | ||
89713ed1 AB |
486 | __get_cpu_var(irq_stat).mce_exceptions++; |
487 | ||
47c0bd1a BH |
488 | /* See if any machine dependent calls. In theory, we would want |
489 | * to call the CPU first, and call the ppc_md. one if the CPU | |
490 | * one returns a positive number. However there is existing code | |
491 | * that assumes the board gets a first chance, so let's keep it | |
492 | * that way for now and fix things later. --BenH. | |
493 | */ | |
75918a4b OJ |
494 | if (ppc_md.machine_check_exception) |
495 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
496 | else if (cur_cpu_spec->machine_check) |
497 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 498 | |
47c0bd1a | 499 | if (recover > 0) |
75918a4b OJ |
500 | return; |
501 | ||
502 | if (user_mode(regs)) { | |
503 | regs->msr |= MSR_RI; | |
504 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
505 | return; | |
506 | } | |
507 | ||
508 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
47c0bd1a BH |
509 | /* the qspan pci read routines can cause machine checks -- Cort |
510 | * | |
511 | * yuck !!! that totally needs to go away ! There are better ways | |
512 | * to deal with that than having a wart in the mcheck handler. | |
513 | * -- BenH | |
514 | */ | |
75918a4b OJ |
515 | bad_page_fault(regs, regs->dar, SIGBUS); |
516 | return; | |
517 | #endif | |
518 | ||
519 | if (debugger_fault_handler(regs)) { | |
520 | regs->msr |= MSR_RI; | |
521 | return; | |
522 | } | |
523 | ||
524 | if (check_io_access(regs)) | |
525 | return; | |
526 | ||
14cf11af PM |
527 | if (debugger_fault_handler(regs)) |
528 | return; | |
8dad3f92 | 529 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
530 | |
531 | /* Must die if the interrupt is not recoverable */ | |
532 | if (!(regs->msr & MSR_RI)) | |
533 | panic("Unrecoverable Machine check"); | |
534 | } | |
535 | ||
536 | void SMIException(struct pt_regs *regs) | |
537 | { | |
538 | die("System Management Interrupt", regs, SIGABRT); | |
539 | } | |
540 | ||
dc1c1ca3 | 541 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
542 | { |
543 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
544 | regs->nip, regs->msr, regs->trap); | |
545 | ||
546 | _exception(SIGTRAP, regs, 0, 0); | |
547 | } | |
548 | ||
dc1c1ca3 | 549 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
550 | { |
551 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
552 | 5, SIGTRAP) == NOTIFY_STOP) | |
553 | return; | |
554 | if (debugger_iabr_match(regs)) | |
555 | return; | |
556 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
557 | } | |
558 | ||
559 | void RunModeException(struct pt_regs *regs) | |
560 | { | |
561 | _exception(SIGTRAP, regs, 0, 0); | |
562 | } | |
563 | ||
8dad3f92 | 564 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
565 | { |
566 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
567 | ||
568 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
569 | 5, SIGTRAP) == NOTIFY_STOP) | |
570 | return; | |
571 | if (debugger_sstep(regs)) | |
572 | return; | |
573 | ||
574 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
575 | } | |
576 | ||
577 | /* | |
578 | * After we have successfully emulated an instruction, we have to | |
579 | * check if the instruction was being single-stepped, and if so, | |
580 | * pretend we got a single-step exception. This was pointed out | |
581 | * by Kumar Gala. -- paulus | |
582 | */ | |
8dad3f92 | 583 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
584 | { |
585 | if (single_stepping(regs)) { | |
586 | clear_single_step(regs); | |
587 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
588 | } | |
589 | } | |
590 | ||
5fad293b | 591 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 592 | { |
5fad293b | 593 | int ret = 0; |
dc1c1ca3 SR |
594 | |
595 | /* Invalid operation */ | |
596 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 597 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
598 | |
599 | /* Overflow */ | |
600 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 601 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
602 | |
603 | /* Underflow */ | |
604 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 605 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
606 | |
607 | /* Divide by zero */ | |
608 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 609 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
610 | |
611 | /* Inexact result */ | |
612 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
613 | ret = FPE_FLTRES; |
614 | ||
615 | return ret; | |
616 | } | |
617 | ||
618 | static void parse_fpe(struct pt_regs *regs) | |
619 | { | |
620 | int code = 0; | |
621 | ||
622 | flush_fp_to_thread(current); | |
623 | ||
624 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
625 | |
626 | _exception(SIGFPE, regs, code, regs->nip); | |
627 | } | |
628 | ||
629 | /* | |
630 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
631 | * provide the PVR to user applications using the mfspr rd, PVR. |
632 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
633 | * memory access caused an access fault. Return zero on success. | |
634 | * | |
635 | * There are a couple of ways to do this, either "decode" the instruction | |
636 | * or directly match lots of bits. In this case, matching lots of | |
637 | * bits is faster and easier. | |
86417780 | 638 | * |
14cf11af | 639 | */ |
14cf11af PM |
640 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
641 | { | |
642 | u8 rT = (instword >> 21) & 0x1f; | |
643 | u8 rA = (instword >> 16) & 0x1f; | |
644 | u8 NB_RB = (instword >> 11) & 0x1f; | |
645 | u32 num_bytes; | |
646 | unsigned long EA; | |
647 | int pos = 0; | |
648 | ||
649 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 650 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
651 | if ((rT == rA) || (rT == NB_RB)) |
652 | return -EINVAL; | |
653 | ||
654 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
655 | ||
16c57b36 KG |
656 | switch (instword & PPC_INST_STRING_MASK) { |
657 | case PPC_INST_LSWX: | |
658 | case PPC_INST_STSWX: | |
14cf11af PM |
659 | EA += NB_RB; |
660 | num_bytes = regs->xer & 0x7f; | |
661 | break; | |
16c57b36 KG |
662 | case PPC_INST_LSWI: |
663 | case PPC_INST_STSWI: | |
14cf11af PM |
664 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
665 | break; | |
666 | default: | |
667 | return -EINVAL; | |
668 | } | |
669 | ||
670 | while (num_bytes != 0) | |
671 | { | |
672 | u8 val; | |
673 | u32 shift = 8 * (3 - (pos & 0x3)); | |
674 | ||
16c57b36 KG |
675 | switch ((instword & PPC_INST_STRING_MASK)) { |
676 | case PPC_INST_LSWX: | |
677 | case PPC_INST_LSWI: | |
14cf11af PM |
678 | if (get_user(val, (u8 __user *)EA)) |
679 | return -EFAULT; | |
680 | /* first time updating this reg, | |
681 | * zero it out */ | |
682 | if (pos == 0) | |
683 | regs->gpr[rT] = 0; | |
684 | regs->gpr[rT] |= val << shift; | |
685 | break; | |
16c57b36 KG |
686 | case PPC_INST_STSWI: |
687 | case PPC_INST_STSWX: | |
14cf11af PM |
688 | val = regs->gpr[rT] >> shift; |
689 | if (put_user(val, (u8 __user *)EA)) | |
690 | return -EFAULT; | |
691 | break; | |
692 | } | |
693 | /* move EA to next address */ | |
694 | EA += 1; | |
695 | num_bytes--; | |
696 | ||
697 | /* manage our position within the register */ | |
698 | if (++pos == 4) { | |
699 | pos = 0; | |
700 | if (++rT == 32) | |
701 | rT = 0; | |
702 | } | |
703 | } | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
c3412dcb WS |
708 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
709 | { | |
710 | u32 ra,rs; | |
711 | unsigned long tmp; | |
712 | ||
713 | ra = (instword >> 16) & 0x1f; | |
714 | rs = (instword >> 21) & 0x1f; | |
715 | ||
716 | tmp = regs->gpr[rs]; | |
717 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
718 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
719 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
720 | regs->gpr[ra] = tmp; | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
c1469f13 KG |
725 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
726 | { | |
727 | u8 rT = (instword >> 21) & 0x1f; | |
728 | u8 rA = (instword >> 16) & 0x1f; | |
729 | u8 rB = (instword >> 11) & 0x1f; | |
730 | u8 BC = (instword >> 6) & 0x1f; | |
731 | u8 bit; | |
732 | unsigned long tmp; | |
733 | ||
734 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
735 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
736 | ||
737 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
14cf11af PM |
742 | static int emulate_instruction(struct pt_regs *regs) |
743 | { | |
744 | u32 instword; | |
745 | u32 rd; | |
746 | ||
fab5db97 | 747 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
748 | return -EINVAL; |
749 | CHECK_FULL_REGS(regs); | |
750 | ||
751 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
752 | return -EFAULT; | |
753 | ||
754 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 755 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 756 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
757 | rd = (instword >> 21) & 0x1f; |
758 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
759 | return 0; | |
760 | } | |
761 | ||
762 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 763 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 764 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 765 | return 0; |
80947e7c | 766 | } |
14cf11af PM |
767 | |
768 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 769 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 770 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
771 | unsigned long msk = 0xf0000000UL >> shift; |
772 | ||
eecff81d | 773 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
774 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
775 | regs->xer &= ~0xf0000000UL; | |
776 | return 0; | |
777 | } | |
778 | ||
779 | /* Emulate load/store string insn. */ | |
80947e7c | 780 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 781 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 782 | return emulate_string_inst(regs, instword); |
80947e7c | 783 | } |
14cf11af | 784 | |
c3412dcb | 785 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 786 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 787 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
788 | return emulate_popcntb_inst(regs, instword); |
789 | } | |
790 | ||
c1469f13 | 791 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 792 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 793 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
794 | return emulate_isel(regs, instword); |
795 | } | |
796 | ||
14cf11af PM |
797 | return -EINVAL; |
798 | } | |
799 | ||
73c9ceab | 800 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 801 | { |
73c9ceab | 802 | return is_kernel_addr(addr); |
14cf11af PM |
803 | } |
804 | ||
8dad3f92 | 805 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
806 | { |
807 | unsigned int reason = get_reason(regs); | |
808 | extern int do_mathemu(struct pt_regs *regs); | |
809 | ||
aa42c69c | 810 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 811 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 812 | |
dc1c1ca3 SR |
813 | if (reason & REASON_FP) { |
814 | /* IEEE FP exception */ | |
815 | parse_fpe(regs); | |
8dad3f92 PM |
816 | return; |
817 | } | |
818 | if (reason & REASON_TRAP) { | |
14cf11af | 819 | /* trap exception */ |
dc1c1ca3 SR |
820 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
821 | == NOTIFY_STOP) | |
822 | return; | |
14cf11af PM |
823 | if (debugger_bpt(regs)) |
824 | return; | |
73c9ceab JF |
825 | |
826 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 827 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
828 | regs->nip += 4; |
829 | return; | |
830 | } | |
8dad3f92 PM |
831 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
832 | return; | |
833 | } | |
834 | ||
cd8a5673 PM |
835 | local_irq_enable(); |
836 | ||
04903a30 KG |
837 | #ifdef CONFIG_MATH_EMULATION |
838 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
839 | * but there seems to be a hardware bug on the 405GP (RevD) | |
840 | * that means ESR is sometimes set incorrectly - either to | |
841 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
842 | * hardware people - not sure if it can happen on any illegal | |
843 | * instruction or only on FP instructions, whether there is a | |
844 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
845 | switch (do_mathemu(regs)) { |
846 | case 0: | |
04903a30 KG |
847 | emulate_single_step(regs); |
848 | return; | |
5fad293b KG |
849 | case 1: { |
850 | int code = 0; | |
851 | code = __parse_fpscr(current->thread.fpscr.val); | |
852 | _exception(SIGFPE, regs, code, regs->nip); | |
853 | return; | |
854 | } | |
855 | case -EFAULT: | |
856 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
857 | return; | |
04903a30 | 858 | } |
5fad293b | 859 | /* fall through on any other errors */ |
04903a30 KG |
860 | #endif /* CONFIG_MATH_EMULATION */ |
861 | ||
8dad3f92 PM |
862 | /* Try to emulate it if we should. */ |
863 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
864 | switch (emulate_instruction(regs)) { |
865 | case 0: | |
866 | regs->nip += 4; | |
867 | emulate_single_step(regs); | |
8dad3f92 | 868 | return; |
14cf11af PM |
869 | case -EFAULT: |
870 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 871 | return; |
14cf11af PM |
872 | } |
873 | } | |
8dad3f92 PM |
874 | |
875 | if (reason & REASON_PRIVILEGED) | |
876 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
877 | else | |
878 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
879 | } |
880 | ||
dc1c1ca3 | 881 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 882 | { |
4393c4f6 | 883 | int sig, code, fixed = 0; |
14cf11af | 884 | |
e9370ae1 PM |
885 | /* we don't implement logging of alignment exceptions */ |
886 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
887 | fixed = fix_alignment(regs); | |
14cf11af PM |
888 | |
889 | if (fixed == 1) { | |
890 | regs->nip += 4; /* skip over emulated instruction */ | |
891 | emulate_single_step(regs); | |
892 | return; | |
893 | } | |
894 | ||
dc1c1ca3 | 895 | /* Operand address was bad */ |
14cf11af | 896 | if (fixed == -EFAULT) { |
4393c4f6 BH |
897 | sig = SIGSEGV; |
898 | code = SEGV_ACCERR; | |
899 | } else { | |
900 | sig = SIGBUS; | |
901 | code = BUS_ADRALN; | |
14cf11af | 902 | } |
4393c4f6 BH |
903 | if (user_mode(regs)) |
904 | _exception(sig, regs, code, regs->dar); | |
905 | else | |
906 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
907 | } |
908 | ||
909 | void StackOverflow(struct pt_regs *regs) | |
910 | { | |
911 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
912 | current, regs->gpr[1]); | |
913 | debugger(regs); | |
914 | show_regs(regs); | |
915 | panic("kernel stack overflow"); | |
916 | } | |
917 | ||
918 | void nonrecoverable_exception(struct pt_regs *regs) | |
919 | { | |
920 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
921 | regs->nip, regs->msr); | |
922 | debugger(regs); | |
923 | die("nonrecoverable exception", regs, SIGKILL); | |
924 | } | |
925 | ||
926 | void trace_syscall(struct pt_regs *regs) | |
927 | { | |
928 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 929 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
930 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
931 | } | |
dc1c1ca3 | 932 | |
dc1c1ca3 SR |
933 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
934 | { | |
935 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
936 | "%lx at %lx\n", regs->trap, regs->nip); | |
937 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
938 | } | |
dc1c1ca3 SR |
939 | |
940 | void altivec_unavailable_exception(struct pt_regs *regs) | |
941 | { | |
dc1c1ca3 SR |
942 | if (user_mode(regs)) { |
943 | /* A user program has executed an altivec instruction, | |
944 | but this kernel doesn't support altivec. */ | |
945 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
946 | return; | |
947 | } | |
6c4841c2 | 948 | |
dc1c1ca3 SR |
949 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
950 | "%lx at %lx\n", regs->trap, regs->nip); | |
951 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
952 | } |
953 | ||
ce48b210 MN |
954 | void vsx_unavailable_exception(struct pt_regs *regs) |
955 | { | |
956 | if (user_mode(regs)) { | |
957 | /* A user program has executed an vsx instruction, | |
958 | but this kernel doesn't support vsx. */ | |
959 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
960 | return; | |
961 | } | |
962 | ||
963 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
964 | "%lx at %lx\n", regs->trap, regs->nip); | |
965 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
966 | } | |
967 | ||
dc1c1ca3 SR |
968 | void performance_monitor_exception(struct pt_regs *regs) |
969 | { | |
89713ed1 AB |
970 | __get_cpu_var(irq_stat).pmu_irqs++; |
971 | ||
dc1c1ca3 SR |
972 | perf_irq(regs); |
973 | } | |
dc1c1ca3 | 974 | |
8dad3f92 | 975 | #ifdef CONFIG_8xx |
14cf11af PM |
976 | void SoftwareEmulation(struct pt_regs *regs) |
977 | { | |
978 | extern int do_mathemu(struct pt_regs *); | |
979 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 980 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 981 | int errcode; |
5dd57a13 | 982 | #endif |
14cf11af PM |
983 | |
984 | CHECK_FULL_REGS(regs); | |
985 | ||
986 | if (!user_mode(regs)) { | |
987 | debugger(regs); | |
988 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
989 | } | |
990 | ||
991 | #ifdef CONFIG_MATH_EMULATION | |
992 | errcode = do_mathemu(regs); | |
80947e7c | 993 | if (errcode >= 0) |
eecff81d | 994 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
995 | |
996 | switch (errcode) { | |
997 | case 0: | |
998 | emulate_single_step(regs); | |
999 | return; | |
1000 | case 1: { | |
1001 | int code = 0; | |
1002 | code = __parse_fpscr(current->thread.fpscr.val); | |
1003 | _exception(SIGFPE, regs, code, regs->nip); | |
1004 | return; | |
1005 | } | |
1006 | case -EFAULT: | |
1007 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1008 | return; | |
1009 | default: | |
1010 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1011 | return; | |
1012 | } | |
1013 | ||
5dd57a13 | 1014 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1015 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1016 | if (errcode >= 0) |
eecff81d | 1017 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1018 | |
5fad293b KG |
1019 | switch (errcode) { |
1020 | case 0: | |
14cf11af | 1021 | emulate_single_step(regs); |
5fad293b KG |
1022 | return; |
1023 | case 1: | |
1024 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1025 | return; | |
1026 | case -EFAULT: | |
1027 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1028 | return; | |
1029 | } | |
5dd57a13 SW |
1030 | #else |
1031 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1032 | #endif |
14cf11af | 1033 | } |
8dad3f92 | 1034 | #endif /* CONFIG_8xx */ |
14cf11af PM |
1035 | |
1036 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
1037 | ||
f8279621 | 1038 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1039 | { |
ec097c84 RM |
1040 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1041 | * on server, it stops on the target of the branch. In order to simulate | |
1042 | * the server behaviour, we thus restart right away with a single step | |
1043 | * instead of stopping here when hitting a BT | |
1044 | */ | |
1045 | if (debug_status & DBSR_BT) { | |
1046 | regs->msr &= ~MSR_DE; | |
1047 | ||
1048 | /* Disable BT */ | |
1049 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1050 | /* Clear the BT event */ | |
1051 | mtspr(SPRN_DBSR, DBSR_BT); | |
1052 | ||
1053 | /* Do the single step trick only when coming from userspace */ | |
1054 | if (user_mode(regs)) { | |
1055 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1056 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1057 | regs->msr |= MSR_DE; | |
1058 | return; | |
1059 | } | |
1060 | ||
1061 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1062 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1063 | return; | |
1064 | } | |
1065 | if (debugger_sstep(regs)) | |
1066 | return; | |
1067 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1068 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1069 | |
1070 | /* Disable instruction completion */ | |
1071 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1072 | /* Clear the instruction completion event */ | |
1073 | mtspr(SPRN_DBSR, DBSR_IC); | |
1074 | ||
1075 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1076 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1077 | return; | |
1078 | } | |
1079 | ||
1080 | if (debugger_sstep(regs)) | |
1081 | return; | |
1082 | ||
ec097c84 RM |
1083 | if (user_mode(regs)) |
1084 | current->thread.dbcr0 &= ~(DBCR0_IC); | |
f8279621 KG |
1085 | |
1086 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
d6a61bfc LM |
1087 | } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
1088 | regs->msr &= ~MSR_DE; | |
1089 | ||
1090 | if (user_mode(regs)) { | |
1091 | current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | | |
1092 | DBCR0_IDM); | |
1093 | } else { | |
1094 | /* Disable DAC interupts */ | |
1095 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | | |
1096 | DBSR_DAC1W | DBCR0_IDM)); | |
1097 | ||
1098 | /* Clear the DAC event */ | |
1099 | mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W)); | |
1100 | } | |
1101 | /* Setup and send the trap to the handler */ | |
1102 | do_dabr(regs, mfspr(SPRN_DAC1), debug_status); | |
14cf11af PM |
1103 | } |
1104 | } | |
1105 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
1106 | ||
1107 | #if !defined(CONFIG_TAU_INT) | |
1108 | void TAUException(struct pt_regs *regs) | |
1109 | { | |
1110 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1111 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1112 | } | |
1113 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1114 | |
1115 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1116 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1117 | { |
1118 | int err; | |
1119 | ||
14cf11af PM |
1120 | if (!user_mode(regs)) { |
1121 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1122 | " at %lx\n", regs->nip); | |
8dad3f92 | 1123 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1124 | } |
1125 | ||
dc1c1ca3 | 1126 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1127 | |
eecff81d | 1128 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1129 | err = emulate_altivec(regs); |
1130 | if (err == 0) { | |
1131 | regs->nip += 4; /* skip emulated instruction */ | |
1132 | emulate_single_step(regs); | |
1133 | return; | |
1134 | } | |
1135 | ||
1136 | if (err == -EFAULT) { | |
1137 | /* got an error reading the instruction */ | |
1138 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1139 | } else { | |
1140 | /* didn't recognize the instruction */ | |
1141 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1142 | if (printk_ratelimit()) | |
1143 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1144 | "in %s at %lx\n", current->comm, regs->nip); | |
1145 | current->thread.vscr.u[3] |= 0x10000; | |
1146 | } | |
1147 | } | |
1148 | #endif /* CONFIG_ALTIVEC */ | |
1149 | ||
ce48b210 MN |
1150 | #ifdef CONFIG_VSX |
1151 | void vsx_assist_exception(struct pt_regs *regs) | |
1152 | { | |
1153 | if (!user_mode(regs)) { | |
1154 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1155 | " at %lx\n", regs->nip); | |
1156 | die("Kernel VSX assist exception", regs, SIGILL); | |
1157 | } | |
1158 | ||
1159 | flush_vsx_to_thread(current); | |
1160 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1161 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1162 | } | |
1163 | #endif /* CONFIG_VSX */ | |
1164 | ||
14cf11af | 1165 | #ifdef CONFIG_FSL_BOOKE |
620165f9 KG |
1166 | |
1167 | void doorbell_exception(struct pt_regs *regs) | |
1168 | { | |
1169 | #ifdef CONFIG_SMP | |
1170 | int cpu = smp_processor_id(); | |
1171 | int msg; | |
1172 | ||
1173 | if (num_online_cpus() < 2) | |
1174 | return; | |
1175 | ||
1176 | for (msg = 0; msg < 4; msg++) | |
1177 | if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) | |
1178 | smp_message_recv(msg); | |
1179 | #else | |
1180 | printk(KERN_WARNING "Received doorbell on non-smp system\n"); | |
1181 | #endif | |
1182 | } | |
1183 | ||
14cf11af PM |
1184 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
1185 | unsigned long error_code) | |
1186 | { | |
1187 | /* We treat cache locking instructions from the user | |
1188 | * as priv ops, in the future we could try to do | |
1189 | * something smarter | |
1190 | */ | |
1191 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1192 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1193 | return; | |
1194 | } | |
1195 | #endif /* CONFIG_FSL_BOOKE */ | |
1196 | ||
1197 | #ifdef CONFIG_SPE | |
1198 | void SPEFloatingPointException(struct pt_regs *regs) | |
1199 | { | |
6a800f36 | 1200 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1201 | unsigned long spefscr; |
1202 | int fpexc_mode; | |
1203 | int code = 0; | |
6a800f36 LY |
1204 | int err; |
1205 | ||
1206 | preempt_disable(); | |
1207 | if (regs->msr & MSR_SPE) | |
1208 | giveup_spe(current); | |
1209 | preempt_enable(); | |
14cf11af PM |
1210 | |
1211 | spefscr = current->thread.spefscr; | |
1212 | fpexc_mode = current->thread.fpexc_mode; | |
1213 | ||
14cf11af PM |
1214 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1215 | code = FPE_FLTOVF; | |
14cf11af PM |
1216 | } |
1217 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1218 | code = FPE_FLTUND; | |
14cf11af PM |
1219 | } |
1220 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1221 | code = FPE_FLTDIV; | |
1222 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1223 | code = FPE_FLTINV; | |
14cf11af PM |
1224 | } |
1225 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1226 | code = FPE_FLTRES; | |
1227 | ||
6a800f36 LY |
1228 | err = do_spe_mathemu(regs); |
1229 | if (err == 0) { | |
1230 | regs->nip += 4; /* skip emulated instruction */ | |
1231 | emulate_single_step(regs); | |
1232 | return; | |
1233 | } | |
1234 | ||
1235 | if (err == -EFAULT) { | |
1236 | /* got an error reading the instruction */ | |
1237 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1238 | } else if (err == -EINVAL) { | |
1239 | /* didn't recognize the instruction */ | |
1240 | printk(KERN_ERR "unrecognized spe instruction " | |
1241 | "in %s at %lx\n", current->comm, regs->nip); | |
1242 | } else { | |
1243 | _exception(SIGFPE, regs, code, regs->nip); | |
1244 | } | |
14cf11af | 1245 | |
14cf11af PM |
1246 | return; |
1247 | } | |
6a800f36 LY |
1248 | |
1249 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1250 | { | |
1251 | extern int speround_handler(struct pt_regs *regs); | |
1252 | int err; | |
1253 | ||
1254 | preempt_disable(); | |
1255 | if (regs->msr & MSR_SPE) | |
1256 | giveup_spe(current); | |
1257 | preempt_enable(); | |
1258 | ||
1259 | regs->nip -= 4; | |
1260 | err = speround_handler(regs); | |
1261 | if (err == 0) { | |
1262 | regs->nip += 4; /* skip emulated instruction */ | |
1263 | emulate_single_step(regs); | |
1264 | return; | |
1265 | } | |
1266 | ||
1267 | if (err == -EFAULT) { | |
1268 | /* got an error reading the instruction */ | |
1269 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1270 | } else if (err == -EINVAL) { | |
1271 | /* didn't recognize the instruction */ | |
1272 | printk(KERN_ERR "unrecognized spe instruction " | |
1273 | "in %s at %lx\n", current->comm, regs->nip); | |
1274 | } else { | |
1275 | _exception(SIGFPE, regs, 0, regs->nip); | |
1276 | return; | |
1277 | } | |
1278 | } | |
14cf11af PM |
1279 | #endif |
1280 | ||
dc1c1ca3 SR |
1281 | /* |
1282 | * We enter here if we get an unrecoverable exception, that is, one | |
1283 | * that happened at a point where the RI (recoverable interrupt) bit | |
1284 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1285 | * we therefore lost state by taking this exception. | |
1286 | */ | |
1287 | void unrecoverable_exception(struct pt_regs *regs) | |
1288 | { | |
1289 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1290 | regs->trap, regs->nip); | |
1291 | die("Unrecoverable exception", regs, SIGABRT); | |
1292 | } | |
dc1c1ca3 | 1293 | |
14cf11af PM |
1294 | #ifdef CONFIG_BOOKE_WDT |
1295 | /* | |
1296 | * Default handler for a Watchdog exception, | |
1297 | * spins until a reboot occurs | |
1298 | */ | |
1299 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1300 | { | |
1301 | /* Generic WatchdogHandler, implement your own */ | |
1302 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1303 | return; | |
1304 | } | |
1305 | ||
1306 | void WatchdogException(struct pt_regs *regs) | |
1307 | { | |
1308 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1309 | WatchdogHandler(regs); | |
1310 | } | |
1311 | #endif | |
dc1c1ca3 | 1312 | |
dc1c1ca3 SR |
1313 | /* |
1314 | * We enter here if we discover during exception entry that we are | |
1315 | * running in supervisor mode with a userspace value in the stack pointer. | |
1316 | */ | |
1317 | void kernel_bad_stack(struct pt_regs *regs) | |
1318 | { | |
1319 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1320 | regs->gpr[1], regs->nip); | |
1321 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1322 | } | |
14cf11af PM |
1323 | |
1324 | void __init trap_init(void) | |
1325 | { | |
1326 | } | |
80947e7c GU |
1327 | |
1328 | ||
1329 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1330 | ||
1331 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1332 | ||
1333 | struct ppc_emulated ppc_emulated = { | |
1334 | #ifdef CONFIG_ALTIVEC | |
1335 | WARN_EMULATED_SETUP(altivec), | |
1336 | #endif | |
1337 | WARN_EMULATED_SETUP(dcba), | |
1338 | WARN_EMULATED_SETUP(dcbz), | |
1339 | WARN_EMULATED_SETUP(fp_pair), | |
1340 | WARN_EMULATED_SETUP(isel), | |
1341 | WARN_EMULATED_SETUP(mcrxr), | |
1342 | WARN_EMULATED_SETUP(mfpvr), | |
1343 | WARN_EMULATED_SETUP(multiple), | |
1344 | WARN_EMULATED_SETUP(popcntb), | |
1345 | WARN_EMULATED_SETUP(spe), | |
1346 | WARN_EMULATED_SETUP(string), | |
1347 | WARN_EMULATED_SETUP(unaligned), | |
1348 | #ifdef CONFIG_MATH_EMULATION | |
1349 | WARN_EMULATED_SETUP(math), | |
1350 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1351 | WARN_EMULATED_SETUP(8xx), | |
1352 | #endif | |
1353 | #ifdef CONFIG_VSX | |
1354 | WARN_EMULATED_SETUP(vsx), | |
1355 | #endif | |
1356 | }; | |
1357 | ||
1358 | u32 ppc_warn_emulated; | |
1359 | ||
1360 | void ppc_warn_emulated_print(const char *type) | |
1361 | { | |
1362 | if (printk_ratelimit()) | |
1363 | pr_warning("%s used emulated %s instruction\n", current->comm, | |
1364 | type); | |
1365 | } | |
1366 | ||
1367 | static int __init ppc_warn_emulated_init(void) | |
1368 | { | |
1369 | struct dentry *dir, *d; | |
1370 | unsigned int i; | |
1371 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1372 | ||
1373 | if (!powerpc_debugfs_root) | |
1374 | return -ENODEV; | |
1375 | ||
1376 | dir = debugfs_create_dir("emulated_instructions", | |
1377 | powerpc_debugfs_root); | |
1378 | if (!dir) | |
1379 | return -ENOMEM; | |
1380 | ||
1381 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1382 | &ppc_warn_emulated); | |
1383 | if (!d) | |
1384 | goto fail; | |
1385 | ||
1386 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1387 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1388 | (u32 *)&entries[i].val.counter); | |
1389 | if (!d) | |
1390 | goto fail; | |
1391 | } | |
1392 | ||
1393 | return 0; | |
1394 | ||
1395 | fail: | |
1396 | debugfs_remove_recursive(dir); | |
1397 | return -ENOMEM; | |
1398 | } | |
1399 | ||
1400 | device_initcall(ppc_warn_emulated_init); | |
1401 | ||
1402 | #endif /* CONFIG_PPC_EMULATED_STATS */ |