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powerpc: Use the merged of_device.c with ARCH=powerpc
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
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14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
17#include <linux/config.h>
18#include <linux/errno.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
14cf11af
PM		 24#include <linux/slab.h>
25#include <linux/user.h>
26#include <linux/a.out.h>
27#include <linux/interrupt.h>
14cf11af
PM		 28#include <linux/init.h>
29#include <linux/module.h>
14cf11af
PM		 30#include <linux/delay.h>
31#include <linux/kprobes.h>
32#include <asm/kdebug.h>
dc1c1ca3
SR		 33#ifdef CONFIG_PPC32
34#include <linux/ptrace.h>
35#include <linux/prctl.h>
36#endif
14cf11af
PM		 37
38#include <asm/pgtable.h>
39#include <asm/uaccess.h>
40#include <asm/system.h>
41#include <asm/io.h>
dc1c1ca3 42#ifdef CONFIG_PPC32
14cf11af
PM		 43#include <asm/reg.h>
44#include <asm/xmon.h>
45#ifdef CONFIG_PMAC_BACKLIGHT
46#include <asm/backlight.h>
47#endif
48#include <asm/perfmon.h>
dc1c1ca3
SR		 49#endif
50#ifdef CONFIG_PPC64
51#include <asm/processor.h>
52#include <asm/ppcdebug.h>
53#include <asm/rtas.h>
54#include <asm/systemcfg.h>
55#include <asm/machdep.h>
56#include <asm/pmc.h>
57#endif
58
59#ifdef CONFIG_PPC64
60#define __KPROBES __kprobes
61#else
62#define __KPROBES
63#endif
14cf11af
PM		 64
65#ifdef CONFIG_DEBUGGER
66int (*__debugger)(struct pt_regs *regs);
67int (*__debugger_ipi)(struct pt_regs *regs);
68int (*__debugger_bpt)(struct pt_regs *regs);
69int (*__debugger_sstep)(struct pt_regs *regs);
70int (*__debugger_iabr_match)(struct pt_regs *regs);
71int (*__debugger_dabr_match)(struct pt_regs *regs);
72int (*__debugger_fault_handler)(struct pt_regs *regs);
73
74EXPORT_SYMBOL(__debugger);
75EXPORT_SYMBOL(__debugger_ipi);
76EXPORT_SYMBOL(__debugger_bpt);
77EXPORT_SYMBOL(__debugger_sstep);
78EXPORT_SYMBOL(__debugger_iabr_match);
79EXPORT_SYMBOL(__debugger_dabr_match);
80EXPORT_SYMBOL(__debugger_fault_handler);
81#endif
82
83struct notifier_block *powerpc_die_chain;
84static DEFINE_SPINLOCK(die_notifier_lock);
85
86int register_die_notifier(struct notifier_block *nb)
87{
88 int err = 0;
89 unsigned long flags;
90
91 spin_lock_irqsave(&die_notifier_lock, flags);
92 err = notifier_chain_register(&powerpc_die_chain, nb);
93 spin_unlock_irqrestore(&die_notifier_lock, flags);
94 return err;
95}
96
97/*
98 * Trap & Exception support
99 */
100
101static DEFINE_SPINLOCK(die_lock);
102
103int die(const char *str, struct pt_regs *regs, long err)
104{
105 static int die_counter;
106 int nl = 0;
107
108 if (debugger(regs))
109 return 1;
110
111 console_verbose();
112 spin_lock_irq(&die_lock);
113 bust_spinlocks(1);
dc1c1ca3 114#if defined(CONFIG_PPC32) && defined(CONFIG_PMAC_BACKLIGHT)
14cf11af
PM		 115 if (_machine == _MACH_Pmac) {
116 set_backlight_enable(1);
117 set_backlight_level(BACKLIGHT_MAX);
118 }
119#endif
120 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
121#ifdef CONFIG_PREEMPT
122 printk("PREEMPT ");
123 nl = 1;
124#endif
125#ifdef CONFIG_SMP
126 printk("SMP NR_CPUS=%d ", NR_CPUS);
127 nl = 1;
128#endif
129#ifdef CONFIG_DEBUG_PAGEALLOC
130 printk("DEBUG_PAGEALLOC ");
131 nl = 1;
132#endif
133#ifdef CONFIG_NUMA
134 printk("NUMA ");
135 nl = 1;
136#endif
137#ifdef CONFIG_PPC64
138 switch (systemcfg->platform) {
139 case PLATFORM_PSERIES:
140 printk("PSERIES ");
141 nl = 1;
142 break;
143 case PLATFORM_PSERIES_LPAR:
144 printk("PSERIES LPAR ");
145 nl = 1;
146 break;
147 case PLATFORM_ISERIES_LPAR:
148 printk("ISERIES LPAR ");
149 nl = 1;
150 break;
151 case PLATFORM_POWERMAC:
152 printk("POWERMAC ");
153 nl = 1;
154 break;
155 case PLATFORM_BPA:
156 printk("BPA ");
157 nl = 1;
158 break;
159 }
160#endif
161 if (nl)
162 printk("\n");
163 print_modules();
164 show_regs(regs);
165 bust_spinlocks(0);
166 spin_unlock_irq(&die_lock);
167
168 if (in_interrupt())
169 panic("Fatal exception in interrupt");
170
171 if (panic_on_oops) {
dc1c1ca3
SR		 172#ifdef CONFIG_PPC64
173 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
174 ssleep(5);
175#endif
14cf11af
PM		 176 panic("Fatal exception");
177 }
dc1c1ca3 178#ifdef CONFIG_PPC32
14cf11af 179 do_exit(err);
dc1c1ca3
SR		 180#else
181 do_exit(SIGSEGV);
182#endif
14cf11af
PM		 183
184 return 0;
185}
186
187void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
188{
189 siginfo_t info;
190
191 if (!user_mode(regs)) {
192 if (die("Exception in kernel mode", regs, signr))
193 return;
194 }
195
196 memset(&info, 0, sizeof(info));
197 info.si_signo = signr;
198 info.si_code = code;
199 info.si_addr = (void __user *) addr;
200 force_sig_info(signr, &info, current);
201
dc1c1ca3 202#ifdef CONFIG_PPC32
14cf11af
PM		 203 /*
204 * Init gets no signals that it doesn't have a handler for.
205 * That's all very well, but if it has caused a synchronous
206 * exception and we ignore the resulting signal, it will just
207 * generate the same exception over and over again and we get
208 * nowhere. Better to kill it and let the kernel panic.
209 */
210 if (current->pid == 1) {
211 __sighandler_t handler;
212
213 spin_lock_irq(&current->sighand->siglock);
214 handler = current->sighand->action[signr-1].sa.sa_handler;
215 spin_unlock_irq(&current->sighand->siglock);
216 if (handler == SIG_DFL) {
217 /* init has generated a synchronous exception
218 and it doesn't have a handler for the signal */
219 printk(KERN_CRIT "init has generated signal %d "
220 "but has no handler for it\n", signr);
221 do_exit(signr);
222 }
223 }
dc1c1ca3 224#endif
14cf11af
PM		 225}
226
227#ifdef CONFIG_PPC64
228void system_reset_exception(struct pt_regs *regs)
229{
230 /* See if any machine dependent calls */
231 if (ppc_md.system_reset_exception)
232 ppc_md.system_reset_exception(regs);
233
dc1c1ca3 234 die("System Reset", regs, 0);
14cf11af
PM		 235
236 /* Must die if the interrupt is not recoverable */
237 if (!(regs->msr & MSR_RI))
238 panic("Unrecoverable System Reset");
239
240 /* What should we do here? We could issue a shutdown or hard reset. */
241}
242#endif
243
dc1c1ca3 244#ifdef CONFIG_PPC32
14cf11af
PM		 245/*
246 * I/O accesses can cause machine checks on powermacs.
247 * Check if the NIP corresponds to the address of a sync
248 * instruction for which there is an entry in the exception
249 * table.
250 * Note that the 601 only takes a machine check on TEA
251 * (transfer error ack) signal assertion, and does not
252 * set any of the top 16 bits of SRR1.
253 * -- paulus.
254 */
255static inline int check_io_access(struct pt_regs *regs)
256{
257#ifdef CONFIG_PPC_PMAC
258 unsigned long msr = regs->msr;
259 const struct exception_table_entry *entry;
260 unsigned int *nip = (unsigned int *)regs->nip;
261
262 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
263 && (entry = search_exception_tables(regs->nip)) != NULL) {
264 /*
265 * Check that it's a sync instruction, or somewhere
266 * in the twi; isync; nop sequence that inb/inw/inl uses.
267 * As the address is in the exception table
268 * we should be able to read the instr there.
269 * For the debug message, we look at the preceding
270 * load or store.
271 */
272 if (*nip == 0x60000000) /* nop */
273 nip -= 2;
274 else if (*nip == 0x4c00012c) /* isync */
275 --nip;
276 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
277 /* sync or twi */
278 unsigned int rb;
279
280 --nip;
281 rb = (*nip >> 11) & 0x1f;
282 printk(KERN_DEBUG "%s bad port %lx at %p\n",
283 (*nip & 0x100)? "OUT to": "IN from",
284 regs->gpr[rb] - _IO_BASE, nip);
285 regs->msr |= MSR_RI;
286 regs->nip = entry->fixup;
287 return 1;
288 }
289 }
290#endif /* CONFIG_PPC_PMAC */
291 return 0;
292}
dc1c1ca3 293#endif /* CONFIG_PPC32 */
14cf11af
PM		 294
295#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
dc1c1ca3 296
14cf11af
PM		 297/* On 4xx, the reason for the machine check or program exception
298 is in the ESR. */
299#define get_reason(regs) ((regs)->dsisr)
300#ifndef CONFIG_FSL_BOOKE
301#define get_mc_reason(regs) ((regs)->dsisr)
302#else
303#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
304#endif
305#define REASON_FP ESR_FP
306#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
307#define REASON_PRIVILEGED ESR_PPR
308#define REASON_TRAP ESR_PTR
309
310/* single-step stuff */
311#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
312#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
313
314#else
dc1c1ca3 315
14cf11af
PM		 316/* On non-4xx, the reason for the machine check or program
317 exception is in the MSR. */
318#define get_reason(regs) ((regs)->msr)
319#define get_mc_reason(regs) ((regs)->msr)
320#define REASON_FP 0x100000
321#define REASON_ILLEGAL 0x80000
322#define REASON_PRIVILEGED 0x40000
323#define REASON_TRAP 0x20000
324
325#define single_stepping(regs) ((regs)->msr & MSR_SE)
326#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
327#endif
328
dc1c1ca3 329#ifdef CONFIG_PPC32
14cf11af
PM		 330/*
331 * This is "fall-back" implementation for configurations
332 * which don't provide platform-specific machine check info
333 */
334void __attribute__ ((weak))
335platform_machine_check(struct pt_regs *regs)
336{
337}
dc1c1ca3 338#endif
14cf11af 339
dc1c1ca3 340void machine_check_exception(struct pt_regs *regs)
14cf11af
PM		 341{
342#ifdef CONFIG_PPC64
343 int recover = 0;
344
345 /* See if any machine dependent calls */
346 if (ppc_md.machine_check_exception)
347 recover = ppc_md.machine_check_exception(regs);
348
349 if (recover)
350 return;
351#else
352 unsigned long reason = get_mc_reason(regs);
353
354 if (user_mode(regs)) {
355 regs->msr |= MSR_RI;
356 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
357 return;
358 }
359
360#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
361 /* the qspan pci read routines can cause machine checks -- Cort */
362 bad_page_fault(regs, regs->dar, SIGBUS);
363 return;
364#endif
365
366 if (debugger_fault_handler(regs)) {
367 regs->msr |= MSR_RI;
368 return;
369 }
370
371 if (check_io_access(regs))
372 return;
373
374#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
375 if (reason & ESR_IMCP) {
376 printk("Instruction");
377 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
378 } else
379 printk("Data");
380 printk(" machine check in kernel mode.\n");
381#elif defined(CONFIG_440A)
382 printk("Machine check in kernel mode.\n");
383 if (reason & ESR_IMCP){
384 printk("Instruction Synchronous Machine Check exception\n");
385 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
386 }
387 else {
388 u32 mcsr = mfspr(SPRN_MCSR);
389 if (mcsr & MCSR_IB)
390 printk("Instruction Read PLB Error\n");
391 if (mcsr & MCSR_DRB)
392 printk("Data Read PLB Error\n");
393 if (mcsr & MCSR_DWB)
394 printk("Data Write PLB Error\n");
395 if (mcsr & MCSR_TLBP)
396 printk("TLB Parity Error\n");
397 if (mcsr & MCSR_ICP){
398 flush_instruction_cache();
399 printk("I-Cache Parity Error\n");
400 }
401 if (mcsr & MCSR_DCSP)
402 printk("D-Cache Search Parity Error\n");
403 if (mcsr & MCSR_DCFP)
404 printk("D-Cache Flush Parity Error\n");
405 if (mcsr & MCSR_IMPE)
406 printk("Machine Check exception is imprecise\n");
407
408 /* Clear MCSR */
409 mtspr(SPRN_MCSR, mcsr);
410 }
411#elif defined (CONFIG_E500)
412 printk("Machine check in kernel mode.\n");
413 printk("Caused by (from MCSR=%lx): ", reason);
414
415 if (reason & MCSR_MCP)
416 printk("Machine Check Signal\n");
417 if (reason & MCSR_ICPERR)
418 printk("Instruction Cache Parity Error\n");
419 if (reason & MCSR_DCP_PERR)
420 printk("Data Cache Push Parity Error\n");
421 if (reason & MCSR_DCPERR)
422 printk("Data Cache Parity Error\n");
423 if (reason & MCSR_GL_CI)
424 printk("Guarded Load or Cache-Inhibited stwcx.\n");
425 if (reason & MCSR_BUS_IAERR)
426 printk("Bus - Instruction Address Error\n");
427 if (reason & MCSR_BUS_RAERR)
428 printk("Bus - Read Address Error\n");
429 if (reason & MCSR_BUS_WAERR)
430 printk("Bus - Write Address Error\n");
431 if (reason & MCSR_BUS_IBERR)
432 printk("Bus - Instruction Data Error\n");
433 if (reason & MCSR_BUS_RBERR)
434 printk("Bus - Read Data Bus Error\n");
435 if (reason & MCSR_BUS_WBERR)
436 printk("Bus - Read Data Bus Error\n");
437 if (reason & MCSR_BUS_IPERR)
438 printk("Bus - Instruction Parity Error\n");
439 if (reason & MCSR_BUS_RPERR)
440 printk("Bus - Read Parity Error\n");
441#elif defined (CONFIG_E200)
442 printk("Machine check in kernel mode.\n");
443 printk("Caused by (from MCSR=%lx): ", reason);
444
445 if (reason & MCSR_MCP)
446 printk("Machine Check Signal\n");
447 if (reason & MCSR_CP_PERR)
448 printk("Cache Push Parity Error\n");
449 if (reason & MCSR_CPERR)
450 printk("Cache Parity Error\n");
451 if (reason & MCSR_EXCP_ERR)
452 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
453 if (reason & MCSR_BUS_IRERR)
454 printk("Bus - Read Bus Error on instruction fetch\n");
455 if (reason & MCSR_BUS_DRERR)
456 printk("Bus - Read Bus Error on data load\n");
457 if (reason & MCSR_BUS_WRERR)
458 printk("Bus - Write Bus Error on buffered store or cache line push\n");
459#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
460 printk("Machine check in kernel mode.\n");
461 printk("Caused by (from SRR1=%lx): ", reason);
462 switch (reason & 0x601F0000) {
463 case 0x80000:
464 printk("Machine check signal\n");
465 break;
466 case 0: /* for 601 */
467 case 0x40000:
468 case 0x140000: /* 7450 MSS error and TEA */
469 printk("Transfer error ack signal\n");
470 break;
471 case 0x20000:
472 printk("Data parity error signal\n");
473 break;
474 case 0x10000:
475 printk("Address parity error signal\n");
476 break;
477 case 0x20000000:
478 printk("L1 Data Cache error\n");
479 break;
480 case 0x40000000:
481 printk("L1 Instruction Cache error\n");
482 break;
483 case 0x00100000:
484 printk("L2 data cache parity error\n");
485 break;
486 default:
487 printk("Unknown values in msr\n");
488 }
489#endif /* CONFIG_4xx */
490
491 /*
492 * Optional platform-provided routine to print out
493 * additional info, e.g. bus error registers.
494 */
495 platform_machine_check(regs);
dc1c1ca3 496#endif /* CONFIG_PPC32 */
14cf11af
PM		 497
498 if (debugger_fault_handler(regs))
499 return;
dc1c1ca3
SR		 500 die("Machine check", regs,
501#ifdef CONFIG_PPC32
502 SIGBUS
503#else
504 0
505#endif
506 );
14cf11af
PM		 507
508 /* Must die if the interrupt is not recoverable */
509 if (!(regs->msr & MSR_RI))
510 panic("Unrecoverable Machine check");
511}
512
dc1c1ca3 513#ifdef CONFIG_PPC32
14cf11af
PM		 514void SMIException(struct pt_regs *regs)
515{
516 die("System Management Interrupt", regs, SIGABRT);
517}
dc1c1ca3 518#endif
14cf11af 519
dc1c1ca3 520void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 521{
522 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
523 regs->nip, regs->msr, regs->trap);
524
525 _exception(SIGTRAP, regs, 0, 0);
526}
527
dc1c1ca3 528void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 529{
530 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
531 5, SIGTRAP) == NOTIFY_STOP)
532 return;
533 if (debugger_iabr_match(regs))
534 return;
535 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
536}
537
dc1c1ca3 538#ifdef CONFIG_PPC32
14cf11af
PM		 539void RunModeException(struct pt_regs *regs)
540{
541 _exception(SIGTRAP, regs, 0, 0);
542}
dc1c1ca3 543#endif
14cf11af 544
dc1c1ca3 545void __KPROBES single_step_exception(struct pt_regs *regs)
14cf11af 546{
dc1c1ca3 547#ifdef CONFIG_PPC32
14cf11af 548 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
dc1c1ca3
SR		 549#else
550 regs->msr &= ~MSR_SE; /* Turn off 'trace' bit */
551#endif
14cf11af
PM		 552
553 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
554 5, SIGTRAP) == NOTIFY_STOP)
555 return;
556 if (debugger_sstep(regs))
557 return;
558
559 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
560}
561
562/*
563 * After we have successfully emulated an instruction, we have to
564 * check if the instruction was being single-stepped, and if so,
565 * pretend we got a single-step exception. This was pointed out
566 * by Kumar Gala. -- paulus
567 */
dc1c1ca3 568static inline void emulate_single_step(struct pt_regs *regs)
14cf11af
PM		 569{
570 if (single_stepping(regs)) {
dc1c1ca3 571#ifdef CONFIG_PPC32
14cf11af
PM		 572 clear_single_step(regs);
573 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
dc1c1ca3
SR		 574#else
575 single_step_exception(regs);
576#endif
14cf11af
PM		 577 }
578}
579
dc1c1ca3
SR		 580static void parse_fpe(struct pt_regs *regs)
581{
582 int code = 0;
583 unsigned long fpscr;
584
585#ifdef CONFIG_PPC32
586 /* We must make sure the FP state is consistent with
587 * our MSR_FP in regs
588 */
589 preempt_disable();
590 if (regs->msr & MSR_FP)
591 giveup_fpu(current);
592 preempt_enable();
593#else
594 flush_fp_to_thread(current);
595#endif
596
597 fpscr = current->thread.fpscr;
598
599 /* Invalid operation */
600 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
601 code = FPE_FLTINV;
602
603 /* Overflow */
604 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
605 code = FPE_FLTOVF;
606
607 /* Underflow */
608 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
609 code = FPE_FLTUND;
610
611 /* Divide by zero */
612 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
613 code = FPE_FLTDIV;
614
615 /* Inexact result */
616 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
617 code = FPE_FLTRES;
618
619 _exception(SIGFPE, regs, code, regs->nip);
620}
621
622/*
623 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 624 * provide the PVR to user applications using the mfspr rd, PVR.
625 * Return non-zero if we can't emulate, or -EFAULT if the associated
626 * memory access caused an access fault. Return zero on success.
627 *
628 * There are a couple of ways to do this, either "decode" the instruction
629 * or directly match lots of bits. In this case, matching lots of
630 * bits is faster and easier.
14cf11af
PM		 631 */
632#define INST_MFSPR_PVR 0x7c1f42a6
633#define INST_MFSPR_PVR_MASK 0xfc1fffff
634
635#define INST_DCBA 0x7c0005ec
636#define INST_DCBA_MASK 0x7c0007fe
637
638#define INST_MCRXR 0x7c000400
639#define INST_MCRXR_MASK 0x7c0007fe
640
dc1c1ca3
SR		 641#ifdef CONFIG_PPC32
642
14cf11af
PM		 643#define INST_STRING 0x7c00042a
644#define INST_STRING_MASK 0x7c0007fe
645#define INST_STRING_GEN_MASK 0x7c00067e
646#define INST_LSWI 0x7c0004aa
647#define INST_LSWX 0x7c00042a
648#define INST_STSWI 0x7c0005aa
649#define INST_STSWX 0x7c00052a
650
651static int emulate_string_inst(struct pt_regs *regs, u32 instword)
652{
653 u8 rT = (instword >> 21) & 0x1f;
654 u8 rA = (instword >> 16) & 0x1f;
655 u8 NB_RB = (instword >> 11) & 0x1f;
656 u32 num_bytes;
657 unsigned long EA;
658 int pos = 0;
659
660 /* Early out if we are an invalid form of lswx */
661 if ((instword & INST_STRING_MASK) == INST_LSWX)
662 if ((rT == rA) || (rT == NB_RB))
663 return -EINVAL;
664
665 EA = (rA == 0) ? 0 : regs->gpr[rA];
666
667 switch (instword & INST_STRING_MASK) {
668 case INST_LSWX:
669 case INST_STSWX:
670 EA += NB_RB;
671 num_bytes = regs->xer & 0x7f;
672 break;
673 case INST_LSWI:
674 case INST_STSWI:
675 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
676 break;
677 default:
678 return -EINVAL;
679 }
680
681 while (num_bytes != 0)
682 {
683 u8 val;
684 u32 shift = 8 * (3 - (pos & 0x3));
685
686 switch ((instword & INST_STRING_MASK)) {
687 case INST_LSWX:
688 case INST_LSWI:
689 if (get_user(val, (u8 __user *)EA))
690 return -EFAULT;
691 /* first time updating this reg,
692 * zero it out */
693 if (pos == 0)
694 regs->gpr[rT] = 0;
695 regs->gpr[rT] |= val << shift;
696 break;
697 case INST_STSWI:
698 case INST_STSWX:
699 val = regs->gpr[rT] >> shift;
700 if (put_user(val, (u8 __user *)EA))
701 return -EFAULT;
702 break;
703 }
704 /* move EA to next address */
705 EA += 1;
706 num_bytes--;
707
708 /* manage our position within the register */
709 if (++pos == 4) {
710 pos = 0;
711 if (++rT == 32)
712 rT = 0;
713 }
714 }
715
716 return 0;
717}
dc1c1ca3 718#endif /* CONFIG_PPC32 */
14cf11af
PM		 719
720static int emulate_instruction(struct pt_regs *regs)
721{
722 u32 instword;
723 u32 rd;
724
725 if (!user_mode(regs))
726 return -EINVAL;
727 CHECK_FULL_REGS(regs);
728
729 if (get_user(instword, (u32 __user *)(regs->nip)))
730 return -EFAULT;
731
732 /* Emulate the mfspr rD, PVR. */
733 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
734 rd = (instword >> 21) & 0x1f;
735 regs->gpr[rd] = mfspr(SPRN_PVR);
736 return 0;
737 }
738
739 /* Emulating the dcba insn is just a no-op. */
dc1c1ca3
SR		 740 if ((instword & INST_DCBA_MASK) == INST_DCBA) {
741#ifdef CONFIG_PPC64
742 static int warned;
743
744 if (!warned) {
745 printk(KERN_WARNING
746 "process %d (%s) uses obsolete 'dcba' insn\n",
747 current->pid, current->comm);
748 warned = 1;
749 }
750#endif /* CONFIG_PPC64 */
14cf11af 751 return 0;
dc1c1ca3 752 }
14cf11af
PM		 753
754 /* Emulate the mcrxr insn. */
755 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
dc1c1ca3 756 unsigned int shift = (instword >> 21) & 0x1c;
14cf11af 757 unsigned long msk = 0xf0000000UL >> shift;
dc1c1ca3
SR		 758#ifdef CONFIG_PPC64
759 static int warned;
14cf11af 760
dc1c1ca3
SR		 761 if (!warned) {
762 printk(KERN_WARNING
763 "process %d (%s) uses obsolete 'mcrxr' insn\n",
764 current->pid, current->comm);
765 warned = 1;
766 }
767#endif
14cf11af
PM		 768 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
769 regs->xer &= ~0xf0000000UL;
770 return 0;
771 }
772
dc1c1ca3 773#ifdef CONFIG_PPC32
14cf11af
PM		 774 /* Emulate load/store string insn. */
775 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
776 return emulate_string_inst(regs, instword);
dc1c1ca3 777#endif
14cf11af
PM		 778
779 return -EINVAL;
780}
781
782/*
783 * Look through the list of trap instructions that are used for BUG(),
784 * BUG_ON() and WARN_ON() and see if we hit one. At this point we know
785 * that the exception was caused by a trap instruction of some kind.
786 * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
787 * otherwise.
788 */
789extern struct bug_entry __start___bug_table[], __stop___bug_table[];
790
791#ifndef CONFIG_MODULES
792#define module_find_bug(x) NULL
793#endif
794
795struct bug_entry *find_bug(unsigned long bugaddr)
796{
797 struct bug_entry *bug;
798
799 for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
800 if (bugaddr == bug->bug_addr)
801 return bug;
802 return module_find_bug(bugaddr);
803}
804
dc1c1ca3 805static int check_bug_trap(struct pt_regs *regs)
14cf11af
PM		 806{
807 struct bug_entry *bug;
808 unsigned long addr;
809
810 if (regs->msr & MSR_PR)
811 return 0; /* not in kernel */
812 addr = regs->nip; /* address of trap instruction */
813 if (addr < PAGE_OFFSET)
814 return 0;
815 bug = find_bug(regs->nip);
816 if (bug == NULL)
817 return 0;
818 if (bug->line & BUG_WARNING_TRAP) {
819 /* this is a WARN_ON rather than BUG/BUG_ON */
dc1c1ca3 820#if defined(CONFIG_PPC32) && defined(CONFIG_XMON)
14cf11af
PM		 821 xmon_printf(KERN_ERR "Badness in %s at %s:%d\n",
822 bug->function, bug->file,
823 bug->line & ~BUG_WARNING_TRAP);
dc1c1ca3 824#endif
14cf11af
PM		 825 printk(KERN_ERR "Badness in %s at %s:%d\n",
826 bug->function, bug->file,
827 bug->line & ~BUG_WARNING_TRAP);
dc1c1ca3 828#ifdef CONFIG_PPC32
14cf11af 829 dump_stack();
dc1c1ca3
SR		 830#else
831 show_stack(current, (void *)regs->gpr[1]);
832#endif
14cf11af
PM		 833 return 1;
834 }
dc1c1ca3 835#if defined(CONFIG_PPC32) && defined(CONFIG_XMON)
14cf11af
PM		 836 xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
837 bug->function, bug->file, bug->line);
838 xmon(regs);
dc1c1ca3 839#endif
14cf11af
PM		 840 printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
841 bug->function, bug->file, bug->line);
842
843 return 0;
844}
845
dc1c1ca3 846void __KPROBES program_check_exception(struct pt_regs *regs)
14cf11af
PM		 847{
848 unsigned int reason = get_reason(regs);
dc1c1ca3 849#if defined(CONFIG_PPC32) && defined(CONFIG_MATH_EMULATION)
14cf11af
PM		 850 extern int do_mathemu(struct pt_regs *regs);
851
14cf11af
PM		 852 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
853 * but there seems to be a hardware bug on the 405GP (RevD)
854 * that means ESR is sometimes set incorrectly - either to
855 * ESR_DST (!?) or 0. In the process of chasing this with the
856 * hardware people - not sure if it can happen on any illegal
857 * instruction or only on FP instructions, whether there is a
858 * pattern to occurences etc. -dgibson 31/Mar/2003 */
859 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
860 emulate_single_step(regs);
861 return;
862 }
dc1c1ca3 863#endif
14cf11af 864
dc1c1ca3
SR		 865#ifdef CONFIG_PPC64
866 if (debugger_fault_handler(regs))
14cf11af 867 return;
dc1c1ca3 868#endif
14cf11af 869
dc1c1ca3
SR		 870 if (reason & REASON_FP) {
871 /* IEEE FP exception */
872 parse_fpe(regs);
873 } else if (reason & REASON_TRAP) {
14cf11af 874 /* trap exception */
dc1c1ca3
SR		 875#ifdef CONFIG_PPC64
876 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
877 == NOTIFY_STOP)
878 return;
879#endif
14cf11af
PM		 880 if (debugger_bpt(regs))
881 return;
882 if (check_bug_trap(regs)) {
883 regs->nip += 4;
884 return;
885 }
dc1c1ca3
SR		 886 _exception(SIGTRAP, regs, TRAP_BRKPT,
887#ifdef CONFIG_PPC32
888 0
889#else
890 regs->nip
891#endif
892 );
893 } else
894#ifdef CONFIG_PPC32
895 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED))
896#endif
897 {
898 /* Privileged or illegal instruction; try to emulate it. */
14cf11af
PM		 899 switch (emulate_instruction(regs)) {
900 case 0:
901 regs->nip += 4;
902 emulate_single_step(regs);
dc1c1ca3 903 break;
14cf11af
PM		 904 case -EFAULT:
905 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
dc1c1ca3
SR		 906 break;
907 default:
908 if (reason & REASON_PRIVILEGED)
909 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
910 else
911 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
912 break;
14cf11af
PM		 913 }
914 }
14cf11af
PM		 915}
916
dc1c1ca3 917void alignment_exception(struct pt_regs *regs)
14cf11af
PM		 918{
919 int fixed;
920
921 fixed = fix_alignment(regs);
922
923 if (fixed == 1) {
924 regs->nip += 4; /* skip over emulated instruction */
925 emulate_single_step(regs);
926 return;
927 }
928
dc1c1ca3 929 /* Operand address was bad */
14cf11af
PM		 930 if (fixed == -EFAULT) {
931 if (user_mode(regs))
dc1c1ca3
SR		 932 _exception(SIGSEGV, regs,
933#ifdef CONFIG_PPC32
934 SEGV_ACCERR,
935#else
936 SEGV_MAPERR,
937#endif
938 regs->dar);
14cf11af
PM		 939 else
940 /* Search exception table */
941 bad_page_fault(regs, regs->dar, SIGSEGV);
942 return;
943 }
dc1c1ca3
SR		 944 _exception(SIGBUS, regs, BUS_ADRALN,
945#ifdef CONFIG_PPC32
946 regs->dar
947#else
948 regs->nip
949#endif
950 );
14cf11af
PM		 951}
952
dc1c1ca3 953#ifdef CONFIG_PPC32
14cf11af
PM		 954void StackOverflow(struct pt_regs *regs)
955{
956 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
957 current, regs->gpr[1]);
958 debugger(regs);
959 show_regs(regs);
960 panic("kernel stack overflow");
961}
962
963void nonrecoverable_exception(struct pt_regs *regs)
964{
965 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
966 regs->nip, regs->msr);
967 debugger(regs);
968 die("nonrecoverable exception", regs, SIGKILL);
969}
970
971void trace_syscall(struct pt_regs *regs)
972{
973 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
974 current, current->pid, regs->nip, regs->link, regs->gpr[0],
975 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
976}
dc1c1ca3
SR		 977#endif /* CONFIG_PPC32 */
978
979#ifdef CONFIG_PPC64
980void kernel_fp_unavailable_exception(struct pt_regs *regs)
981{
982 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
983 "%lx at %lx\n", regs->trap, regs->nip);
984 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
985}
986#endif
987
988void altivec_unavailable_exception(struct pt_regs *regs)
989{
990#if !defined(CONFIG_ALTIVEC) || defined(CONFIG_PPC64)
991 if (user_mode(regs)) {
992 /* A user program has executed an altivec instruction,
993 but this kernel doesn't support altivec. */
994 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
995 return;
996 }
997#endif
998#ifdef CONFIG_PPC32
999 {
1000 static int kernel_altivec_count;
1001
1002 /* The kernel has executed an altivec instruction without
1003 first enabling altivec. Whinge but let it do it. */
1004 if (++kernel_altivec_count < 10)
1005 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
1006 current, regs->nip);
1007 regs->msr |= MSR_VEC;
1008 }
1009#else
1010 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1011 "%lx at %lx\n", regs->trap, regs->nip);
1012 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1013#endif
1014}
1015
1016#ifdef CONFIG_PPC64
1017extern perf_irq_t perf_irq;
1018#endif
1019
1020#if defined(CONFIG_PPC64) || defined(CONFIG_E500)
1021void performance_monitor_exception(struct pt_regs *regs)
1022{
1023 perf_irq(regs);
1024}
1025#endif
1026
14cf11af 1027
dc1c1ca3 1028#if defined(CONFIG_PPC32) && defined(CONFIG_8xx)
14cf11af
PM		 1029void SoftwareEmulation(struct pt_regs *regs)
1030{
1031 extern int do_mathemu(struct pt_regs *);
1032 extern int Soft_emulate_8xx(struct pt_regs *);
1033 int errcode;
1034
1035 CHECK_FULL_REGS(regs);
1036
1037 if (!user_mode(regs)) {
1038 debugger(regs);
1039 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1040 }
1041
1042#ifdef CONFIG_MATH_EMULATION
1043 errcode = do_mathemu(regs);
1044#else
1045 errcode = Soft_emulate_8xx(regs);
1046#endif
1047 if (errcode) {
1048 if (errcode > 0)
1049 _exception(SIGFPE, regs, 0, 0);
1050 else if (errcode == -EFAULT)
1051 _exception(SIGSEGV, regs, 0, 0);
1052 else
1053 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1054 } else
1055 emulate_single_step(regs);
1056}
dc1c1ca3 1057#endif /* defined(CONFIG_PPC32) && defined(CONFIG_8xx) */
14cf11af 1058
dc1c1ca3 1059#ifdef CONFIG_PPC32
14cf11af
PM		 1060#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
1061
1062void DebugException(struct pt_regs *regs, unsigned long debug_status)
1063{
1064 if (debug_status & DBSR_IC) { /* instruction completion */
1065 regs->msr &= ~MSR_DE;
1066 if (user_mode(regs)) {
1067 current->thread.dbcr0 &= ~DBCR0_IC;
1068 } else {
1069 /* Disable instruction completion */
1070 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1071 /* Clear the instruction completion event */
1072 mtspr(SPRN_DBSR, DBSR_IC);
1073 if (debugger_sstep(regs))
1074 return;
1075 }
1076 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
1077 }
1078}
1079#endif /* CONFIG_4xx || CONFIG_BOOKE */
1080
1081#if !defined(CONFIG_TAU_INT)
1082void TAUException(struct pt_regs *regs)
1083{
1084 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1085 regs->nip, regs->msr, regs->trap, print_tainted());
1086}
1087#endif /* CONFIG_INT_TAU */
dc1c1ca3 1088#endif /* CONFIG_PPC32*/
14cf11af
PM		 1089
1090#ifdef CONFIG_ALTIVEC
dc1c1ca3 1091void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 1092{
1093 int err;
dc1c1ca3
SR		 1094#ifdef CONFIG_PPC64
1095 siginfo_t info;
1096#endif
14cf11af 1097
dc1c1ca3 1098#ifdef CONFIG_PPC32
14cf11af
PM		 1099 preempt_disable();
1100 if (regs->msr & MSR_VEC)
1101 giveup_altivec(current);
1102 preempt_enable();
dc1c1ca3 1103#endif
14cf11af
PM		 1104 if (!user_mode(regs)) {
1105 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1106 " at %lx\n", regs->nip);
dc1c1ca3
SR		 1107 die("Kernel "
1108#ifdef CONFIG_PPC64
1109 "VMX/"
1110#endif
1111 "Altivec assist exception", regs, SIGILL);
14cf11af
PM		 1112 }
1113
dc1c1ca3
SR		 1114#ifdef CONFIG_PPC64
1115 flush_altivec_to_thread(current);
1116#endif /* CONFIG_PPC64 */
1117
14cf11af
PM		 1118 err = emulate_altivec(regs);
1119 if (err == 0) {
1120 regs->nip += 4; /* skip emulated instruction */
1121 emulate_single_step(regs);
1122 return;
1123 }
1124
1125 if (err == -EFAULT) {
1126 /* got an error reading the instruction */
dc1c1ca3 1127#ifdef CONFIG_PPC32
14cf11af 1128 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
dc1c1ca3
SR		 1129#else
1130 info.si_signo = SIGSEGV;
1131 info.si_errno = 0;
1132 info.si_code = SEGV_MAPERR;
1133 info.si_addr = (void __user *) regs->nip;
1134 force_sig_info(SIGSEGV, &info, current);
1135#endif
14cf11af
PM		 1136 } else {
1137 /* didn't recognize the instruction */
1138 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1139 if (printk_ratelimit())
1140 printk(KERN_ERR "Unrecognized altivec instruction "
1141 "in %s at %lx\n", current->comm, regs->nip);
1142 current->thread.vscr.u[3] |= 0x10000;
1143 }
1144}
1145#endif /* CONFIG_ALTIVEC */
1146
dc1c1ca3 1147#ifdef CONFIG_PPC32
14cf11af
PM		 1148#ifdef CONFIG_FSL_BOOKE
1149void CacheLockingException(struct pt_regs *regs, unsigned long address,
1150 unsigned long error_code)
1151{
1152 /* We treat cache locking instructions from the user
1153 * as priv ops, in the future we could try to do
1154 * something smarter
1155 */
1156 if (error_code & (ESR_DLK|ESR_ILK))
1157 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1158 return;
1159}
1160#endif /* CONFIG_FSL_BOOKE */
1161
1162#ifdef CONFIG_SPE
1163void SPEFloatingPointException(struct pt_regs *regs)
1164{
1165 unsigned long spefscr;
1166 int fpexc_mode;
1167 int code = 0;
1168
1169 spefscr = current->thread.spefscr;
1170 fpexc_mode = current->thread.fpexc_mode;
1171
1172 /* Hardware does not neccessarily set sticky
1173 * underflow/overflow/invalid flags */
1174 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1175 code = FPE_FLTOVF;
1176 spefscr |= SPEFSCR_FOVFS;
1177 }
1178 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1179 code = FPE_FLTUND;
1180 spefscr |= SPEFSCR_FUNFS;
1181 }
1182 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1183 code = FPE_FLTDIV;
1184 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1185 code = FPE_FLTINV;
1186 spefscr |= SPEFSCR_FINVS;
1187 }
1188 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1189 code = FPE_FLTRES;
1190
1191 current->thread.spefscr = spefscr;
1192
1193 _exception(SIGFPE, regs, code, regs->nip);
1194 return;
1195}
1196#endif
dc1c1ca3 1197#endif /* CONFIG_PPC32 */
14cf11af 1198
dc1c1ca3
SR		 1199#ifdef CONFIG_PPC64
1200/*
1201 * We enter here if we get an unrecoverable exception, that is, one
1202 * that happened at a point where the RI (recoverable interrupt) bit
1203 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1204 * we therefore lost state by taking this exception.
1205 */
1206void unrecoverable_exception(struct pt_regs *regs)
1207{
1208 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1209 regs->trap, regs->nip);
1210 die("Unrecoverable exception", regs, SIGABRT);
1211}
1212#endif /* CONFIG_PPC64 */
1213
1214#ifdef CONFIG_PPC32
14cf11af
PM		 1215#ifdef CONFIG_BOOKE_WDT
1216/*
1217 * Default handler for a Watchdog exception,
1218 * spins until a reboot occurs
1219 */
1220void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1221{
1222 /* Generic WatchdogHandler, implement your own */
1223 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1224 return;
1225}
1226
1227void WatchdogException(struct pt_regs *regs)
1228{
1229 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1230 WatchdogHandler(regs);
1231}
1232#endif
dc1c1ca3
SR		 1233#endif /* CONFIG_PPC32 */
1234
1235#ifdef CONFIG_PPC64
1236/*
1237 * We enter here if we discover during exception entry that we are
1238 * running in supervisor mode with a userspace value in the stack pointer.
1239 */
1240void kernel_bad_stack(struct pt_regs *regs)
1241{
1242 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1243 regs->gpr[1], regs->nip);
1244 die("Bad kernel stack pointer", regs, SIGABRT);
1245}
1246#endif
14cf11af
PM		 1247
1248void __init trap_init(void)
1249{
1250}
Linux kernel - Deliverables
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