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Merge branch 'linux-2.6'
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Modified by Cort Dougan (cort@cs.nmt.edu)
10 * and Paul Mackerras (paulus@samba.org)
11 */
12
13/*
14 * This file handles the architecture-dependent parts of hardware exceptions
15 */
16
14cf11af
PM		 17#include <linux/errno.h>
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/mm.h>
21#include <linux/stddef.h>
22#include <linux/unistd.h>
8dad3f92 23#include <linux/ptrace.h>
14cf11af
PM		 24#include <linux/slab.h>
25#include <linux/user.h>
26#include <linux/a.out.h>
27#include <linux/interrupt.h>
14cf11af
PM		 28#include <linux/init.h>
29#include <linux/module.h>
8dad3f92 30#include <linux/prctl.h>
14cf11af
PM		 31#include <linux/delay.h>
32#include <linux/kprobes.h>
cc532915 33#include <linux/kexec.h>
5474c120 34#include <linux/backlight.h>
73c9ceab 35#include <linux/bug.h>
1eeb66a1 36#include <linux/kdebug.h>
14cf11af
PM		 37
38#include <asm/pgtable.h>
39#include <asm/uaccess.h>
40#include <asm/system.h>
41#include <asm/io.h>
86417780
PM		 42#include <asm/machdep.h>
43#include <asm/rtas.h>
f7f6f4fe 44#include <asm/pmc.h>
dc1c1ca3 45#ifdef CONFIG_PPC32
14cf11af 46#include <asm/reg.h>
86417780 47#endif
14cf11af
PM		 48#ifdef CONFIG_PMAC_BACKLIGHT
49#include <asm/backlight.h>
50#endif
dc1c1ca3 51#ifdef CONFIG_PPC64
86417780 52#include <asm/firmware.h>
dc1c1ca3 53#include <asm/processor.h>
dc1c1ca3 54#endif
c0ce7d08 55#include <asm/kexec.h>
dc1c1ca3 56
14cf11af
PM		 57#ifdef CONFIG_DEBUGGER
58int (*__debugger)(struct pt_regs *regs);
59int (*__debugger_ipi)(struct pt_regs *regs);
60int (*__debugger_bpt)(struct pt_regs *regs);
61int (*__debugger_sstep)(struct pt_regs *regs);
62int (*__debugger_iabr_match)(struct pt_regs *regs);
63int (*__debugger_dabr_match)(struct pt_regs *regs);
64int (*__debugger_fault_handler)(struct pt_regs *regs);
65
66EXPORT_SYMBOL(__debugger);
67EXPORT_SYMBOL(__debugger_ipi);
68EXPORT_SYMBOL(__debugger_bpt);
69EXPORT_SYMBOL(__debugger_sstep);
70EXPORT_SYMBOL(__debugger_iabr_match);
71EXPORT_SYMBOL(__debugger_dabr_match);
72EXPORT_SYMBOL(__debugger_fault_handler);
73#endif
74
14cf11af
PM		 75/*
76 * Trap & Exception support
77 */
78
6031d9d9 79#ifdef CONFIG_PMAC_BACKLIGHT
80static void pmac_backlight_unblank(void)
81{
82 mutex_lock(&pmac_backlight_mutex);
83 if (pmac_backlight) {
84 struct backlight_properties *props;
85
86 props = &pmac_backlight->props;
87 props->brightness = props->max_brightness;
88 props->power = FB_BLANK_UNBLANK;
89 backlight_update_status(pmac_backlight);
90 }
91 mutex_unlock(&pmac_backlight_mutex);
92}
93#else
94static inline void pmac_backlight_unblank(void) { }
95#endif
96
14cf11af
PM		 97int die(const char *str, struct pt_regs *regs, long err)
98{
34c2a14f 99 static struct {
100 spinlock_t lock;
101 u32 lock_owner;
102 int lock_owner_depth;
103 } die = {
104 .lock = __SPIN_LOCK_UNLOCKED(die.lock),
105 .lock_owner = -1,
106 .lock_owner_depth = 0
107 };
c0ce7d08 108 static int die_counter;
34c2a14f 109 unsigned long flags;
14cf11af
PM		 110
111 if (debugger(regs))
112 return 1;
113
293e4688 114 oops_enter();
115
34c2a14f 116 if (die.lock_owner != raw_smp_processor_id()) {
117 console_verbose();
118 spin_lock_irqsave(&die.lock, flags);
119 die.lock_owner = smp_processor_id();
120 die.lock_owner_depth = 0;
121 bust_spinlocks(1);
122 if (machine_is(powermac))
123 pmac_backlight_unblank();
124 } else {
125 local_save_flags(flags);
126 }
5474c120 127
34c2a14f 128 if (++die.lock_owner_depth < 3) {
129 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
14cf11af 130#ifdef CONFIG_PREEMPT
34c2a14f 131 printk("PREEMPT ");
14cf11af
PM		 132#endif
133#ifdef CONFIG_SMP
34c2a14f 134 printk("SMP NR_CPUS=%d ", NR_CPUS);
14cf11af
PM		 135#endif
136#ifdef CONFIG_DEBUG_PAGEALLOC
34c2a14f 137 printk("DEBUG_PAGEALLOC ");
14cf11af
PM		 138#endif
139#ifdef CONFIG_NUMA
34c2a14f 140 printk("NUMA ");
14cf11af 141#endif
ae7f4463 142 printk("%s\n", ppc_md.name ? ppc_md.name : "");
34c2a14f 143
144 print_modules();
145 show_regs(regs);
146 } else {
147 printk("Recursive die() failure, output suppressed\n");
148 }
e8222502 149
14cf11af 150 bust_spinlocks(0);
34c2a14f 151 die.lock_owner = -1;
bcdcd8e7 152 add_taint(TAINT_DIE);
34c2a14f 153 spin_unlock_irqrestore(&die.lock, flags);
cc532915 154
c0ce7d08
DW		 155 if (kexec_should_crash(current) ||
156 kexec_sr_activated(smp_processor_id()))
cc532915 157 crash_kexec(regs);
c0ce7d08 158 crash_kexec_secondary(regs);
14cf11af
PM		 159
160 if (in_interrupt())
161 panic("Fatal exception in interrupt");
162
cea6a4ba 163 if (panic_on_oops)
012c437d 164 panic("Fatal exception");
cea6a4ba 165
293e4688 166 oops_exit();
14cf11af
PM		 167 do_exit(err);
168
169 return 0;
170}
171
172void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
173{
174 siginfo_t info;
d0c3d534
OJ		 175 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
176 "at %08lx nip %08lx lr %08lx code %x\n";
177 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
178 "at %016lx nip %016lx lr %016lx code %x\n";
14cf11af
PM		 179
180 if (!user_mode(regs)) {
181 if (die("Exception in kernel mode", regs, signr))
182 return;
d0c3d534
OJ		 183 } else if (show_unhandled_signals &&
184 unhandled_signal(current, signr) &&
185 printk_ratelimit()) {
186 printk(regs->msr & MSR_SF ? fmt64 : fmt32,
187 current->comm, current->pid, signr,
188 addr, regs->nip, regs->link, code);
189 }
14cf11af
PM		 190
191 memset(&info, 0, sizeof(info));
192 info.si_signo = signr;
193 info.si_code = code;
194 info.si_addr = (void __user *) addr;
195 force_sig_info(signr, &info, current);
196
197 /*
198 * Init gets no signals that it doesn't have a handler for.
199 * That's all very well, but if it has caused a synchronous
200 * exception and we ignore the resulting signal, it will just
201 * generate the same exception over and over again and we get
202 * nowhere. Better to kill it and let the kernel panic.
203 */
b460cbc5 204 if (is_global_init(current)) {
14cf11af
PM		 205 __sighandler_t handler;
206
207 spin_lock_irq(&current->sighand->siglock);
208 handler = current->sighand->action[signr-1].sa.sa_handler;
209 spin_unlock_irq(&current->sighand->siglock);
210 if (handler == SIG_DFL) {
211 /* init has generated a synchronous exception
212 and it doesn't have a handler for the signal */
213 printk(KERN_CRIT "init has generated signal %d "
214 "but has no handler for it\n", signr);
215 do_exit(signr);
216 }
217 }
218}
219
220#ifdef CONFIG_PPC64
221void system_reset_exception(struct pt_regs *regs)
222{
223 /* See if any machine dependent calls */
c902be71
AB		 224 if (ppc_md.system_reset_exception) {
225 if (ppc_md.system_reset_exception(regs))
226 return;
227 }
14cf11af 228
c0ce7d08
DW		 229#ifdef CONFIG_KEXEC
230 cpu_set(smp_processor_id(), cpus_in_sr);
231#endif
232
8dad3f92 233 die("System Reset", regs, SIGABRT);
14cf11af 234
eac8392f
DW		 235 /*
236 * Some CPUs when released from the debugger will execute this path.
237 * These CPUs entered the debugger via a soft-reset. If the CPU was
238 * hung before entering the debugger it will return to the hung
239 * state when exiting this function. This causes a problem in
240 * kdump since the hung CPU(s) will not respond to the IPI sent
241 * from kdump. To prevent the problem we call crash_kexec_secondary()
242 * here. If a kdump had not been initiated or we exit the debugger
243 * with the "exit and recover" command (x) crash_kexec_secondary()
244 * will return after 5ms and the CPU returns to its previous state.
245 */
246 crash_kexec_secondary(regs);
247
14cf11af
PM		 248 /* Must die if the interrupt is not recoverable */
249 if (!(regs->msr & MSR_RI))
250 panic("Unrecoverable System Reset");
251
252 /* What should we do here? We could issue a shutdown or hard reset. */
253}
254#endif
255
256/*
257 * I/O accesses can cause machine checks on powermacs.
258 * Check if the NIP corresponds to the address of a sync
259 * instruction for which there is an entry in the exception
260 * table.
261 * Note that the 601 only takes a machine check on TEA
262 * (transfer error ack) signal assertion, and does not
263 * set any of the top 16 bits of SRR1.
264 * -- paulus.
265 */
266static inline int check_io_access(struct pt_regs *regs)
267{
68a64357 268#ifdef CONFIG_PPC32
14cf11af
PM		 269 unsigned long msr = regs->msr;
270 const struct exception_table_entry *entry;
271 unsigned int *nip = (unsigned int *)regs->nip;
272
273 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
274 && (entry = search_exception_tables(regs->nip)) != NULL) {
275 /*
276 * Check that it's a sync instruction, or somewhere
277 * in the twi; isync; nop sequence that inb/inw/inl uses.
278 * As the address is in the exception table
279 * we should be able to read the instr there.
280 * For the debug message, we look at the preceding
281 * load or store.
282 */
283 if (*nip == 0x60000000) /* nop */
284 nip -= 2;
285 else if (*nip == 0x4c00012c) /* isync */
286 --nip;
287 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
288 /* sync or twi */
289 unsigned int rb;
290
291 --nip;
292 rb = (*nip >> 11) & 0x1f;
293 printk(KERN_DEBUG "%s bad port %lx at %p\n",
294 (*nip & 0x100)? "OUT to": "IN from",
295 regs->gpr[rb] - _IO_BASE, nip);
296 regs->msr |= MSR_RI;
297 regs->nip = entry->fixup;
298 return 1;
299 }
300 }
68a64357 301#endif /* CONFIG_PPC32 */
14cf11af
PM		 302 return 0;
303}
304
305#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
306/* On 4xx, the reason for the machine check or program exception
307 is in the ESR. */
308#define get_reason(regs) ((regs)->dsisr)
309#ifndef CONFIG_FSL_BOOKE
310#define get_mc_reason(regs) ((regs)->dsisr)
311#else
86d7a9a9 312#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK)
14cf11af
PM		 313#endif
314#define REASON_FP ESR_FP
315#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
316#define REASON_PRIVILEGED ESR_PPR
317#define REASON_TRAP ESR_PTR
318
319/* single-step stuff */
320#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
321#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
322
323#else
324/* On non-4xx, the reason for the machine check or program
325 exception is in the MSR. */
326#define get_reason(regs) ((regs)->msr)
327#define get_mc_reason(regs) ((regs)->msr)
328#define REASON_FP 0x100000
329#define REASON_ILLEGAL 0x80000
330#define REASON_PRIVILEGED 0x40000
331#define REASON_TRAP 0x20000
332
333#define single_stepping(regs) ((regs)->msr & MSR_SE)
334#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
335#endif
336
75918a4b 337static int generic_machine_check_exception(struct pt_regs *regs)
14cf11af 338{
1a6a4ffe 339 unsigned long reason = get_mc_reason(regs);
14cf11af 340
14cf11af
PM		 341#if defined(CONFIG_4xx) && !defined(CONFIG_440A)
342 if (reason & ESR_IMCP) {
343 printk("Instruction");
344 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
345 } else
346 printk("Data");
347 printk(" machine check in kernel mode.\n");
348#elif defined(CONFIG_440A)
349 printk("Machine check in kernel mode.\n");
350 if (reason & ESR_IMCP){
351 printk("Instruction Synchronous Machine Check exception\n");
352 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
353 }
354 else {
355 u32 mcsr = mfspr(SPRN_MCSR);
356 if (mcsr & MCSR_IB)
357 printk("Instruction Read PLB Error\n");
358 if (mcsr & MCSR_DRB)
359 printk("Data Read PLB Error\n");
360 if (mcsr & MCSR_DWB)
361 printk("Data Write PLB Error\n");
362 if (mcsr & MCSR_TLBP)
363 printk("TLB Parity Error\n");
364 if (mcsr & MCSR_ICP){
365 flush_instruction_cache();
366 printk("I-Cache Parity Error\n");
367 }
368 if (mcsr & MCSR_DCSP)
369 printk("D-Cache Search Parity Error\n");
370 if (mcsr & MCSR_DCFP)
371 printk("D-Cache Flush Parity Error\n");
372 if (mcsr & MCSR_IMPE)
373 printk("Machine Check exception is imprecise\n");
374
375 /* Clear MCSR */
376 mtspr(SPRN_MCSR, mcsr);
377 }
378#elif defined (CONFIG_E500)
379 printk("Machine check in kernel mode.\n");
380 printk("Caused by (from MCSR=%lx): ", reason);
381
382 if (reason & MCSR_MCP)
383 printk("Machine Check Signal\n");
384 if (reason & MCSR_ICPERR)
385 printk("Instruction Cache Parity Error\n");
386 if (reason & MCSR_DCP_PERR)
387 printk("Data Cache Push Parity Error\n");
388 if (reason & MCSR_DCPERR)
389 printk("Data Cache Parity Error\n");
14cf11af
PM		 390 if (reason & MCSR_BUS_IAERR)
391 printk("Bus - Instruction Address Error\n");
392 if (reason & MCSR_BUS_RAERR)
393 printk("Bus - Read Address Error\n");
394 if (reason & MCSR_BUS_WAERR)
395 printk("Bus - Write Address Error\n");
396 if (reason & MCSR_BUS_IBERR)
397 printk("Bus - Instruction Data Error\n");
398 if (reason & MCSR_BUS_RBERR)
399 printk("Bus - Read Data Bus Error\n");
400 if (reason & MCSR_BUS_WBERR)
401 printk("Bus - Read Data Bus Error\n");
402 if (reason & MCSR_BUS_IPERR)
403 printk("Bus - Instruction Parity Error\n");
404 if (reason & MCSR_BUS_RPERR)
405 printk("Bus - Read Parity Error\n");
406#elif defined (CONFIG_E200)
407 printk("Machine check in kernel mode.\n");
408 printk("Caused by (from MCSR=%lx): ", reason);
409
410 if (reason & MCSR_MCP)
411 printk("Machine Check Signal\n");
412 if (reason & MCSR_CP_PERR)
413 printk("Cache Push Parity Error\n");
414 if (reason & MCSR_CPERR)
415 printk("Cache Parity Error\n");
416 if (reason & MCSR_EXCP_ERR)
417 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
418 if (reason & MCSR_BUS_IRERR)
419 printk("Bus - Read Bus Error on instruction fetch\n");
420 if (reason & MCSR_BUS_DRERR)
421 printk("Bus - Read Bus Error on data load\n");
422 if (reason & MCSR_BUS_WRERR)
423 printk("Bus - Write Bus Error on buffered store or cache line push\n");
424#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
425 printk("Machine check in kernel mode.\n");
426 printk("Caused by (from SRR1=%lx): ", reason);
427 switch (reason & 0x601F0000) {
428 case 0x80000:
429 printk("Machine check signal\n");
430 break;
431 case 0: /* for 601 */
432 case 0x40000:
433 case 0x140000: /* 7450 MSS error and TEA */
434 printk("Transfer error ack signal\n");
435 break;
436 case 0x20000:
437 printk("Data parity error signal\n");
438 break;
439 case 0x10000:
440 printk("Address parity error signal\n");
441 break;
442 case 0x20000000:
443 printk("L1 Data Cache error\n");
444 break;
445 case 0x40000000:
446 printk("L1 Instruction Cache error\n");
447 break;
448 case 0x00100000:
449 printk("L2 data cache parity error\n");
450 break;
451 default:
452 printk("Unknown values in msr\n");
453 }
454#endif /* CONFIG_4xx */
455
75918a4b
OJ		 456 return 0;
457}
458
459void machine_check_exception(struct pt_regs *regs)
460{
461 int recover = 0;
462
463 /* See if any machine dependent calls */
464 if (ppc_md.machine_check_exception)
465 recover = ppc_md.machine_check_exception(regs);
466 else
467 recover = generic_machine_check_exception(regs);
468
469 if (recover)
470 return;
471
472 if (user_mode(regs)) {
473 regs->msr |= MSR_RI;
474 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
475 return;
476 }
477
478#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
479 /* the qspan pci read routines can cause machine checks -- Cort */
480 bad_page_fault(regs, regs->dar, SIGBUS);
481 return;
482#endif
483
484 if (debugger_fault_handler(regs)) {
485 regs->msr |= MSR_RI;
486 return;
487 }
488
489 if (check_io_access(regs))
490 return;
491
14cf11af
PM		 492 if (debugger_fault_handler(regs))
493 return;
8dad3f92 494 die("Machine check", regs, SIGBUS);
14cf11af
PM		 495
496 /* Must die if the interrupt is not recoverable */
497 if (!(regs->msr & MSR_RI))
498 panic("Unrecoverable Machine check");
499}
500
501void SMIException(struct pt_regs *regs)
502{
503 die("System Management Interrupt", regs, SIGABRT);
504}
505
dc1c1ca3 506void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 507{
508 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
509 regs->nip, regs->msr, regs->trap);
510
511 _exception(SIGTRAP, regs, 0, 0);
512}
513
dc1c1ca3 514void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 515{
516 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
517 5, SIGTRAP) == NOTIFY_STOP)
518 return;
519 if (debugger_iabr_match(regs))
520 return;
521 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
522}
523
524void RunModeException(struct pt_regs *regs)
525{
526 _exception(SIGTRAP, regs, 0, 0);
527}
528
8dad3f92 529void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af
PM		 530{
531 regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
532
533 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
534 5, SIGTRAP) == NOTIFY_STOP)
535 return;
536 if (debugger_sstep(regs))
537 return;
538
539 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
540}
541
542/*
543 * After we have successfully emulated an instruction, we have to
544 * check if the instruction was being single-stepped, and if so,
545 * pretend we got a single-step exception. This was pointed out
546 * by Kumar Gala. -- paulus
547 */
8dad3f92 548static void emulate_single_step(struct pt_regs *regs)
14cf11af
PM		 549{
550 if (single_stepping(regs)) {
551 clear_single_step(regs);
552 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
553 }
554}
555
5fad293b 556static inline int __parse_fpscr(unsigned long fpscr)
dc1c1ca3 557{
5fad293b 558 int ret = 0;
dc1c1ca3
SR		 559
560 /* Invalid operation */
561 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
5fad293b 562 ret = FPE_FLTINV;
dc1c1ca3
SR		 563
564 /* Overflow */
565 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
5fad293b 566 ret = FPE_FLTOVF;
dc1c1ca3
SR		 567
568 /* Underflow */
569 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
5fad293b 570 ret = FPE_FLTUND;
dc1c1ca3
SR		 571
572 /* Divide by zero */
573 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
5fad293b 574 ret = FPE_FLTDIV;
dc1c1ca3
SR		 575
576 /* Inexact result */
577 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
5fad293b
KG		 578 ret = FPE_FLTRES;
579
580 return ret;
581}
582
583static void parse_fpe(struct pt_regs *regs)
584{
585 int code = 0;
586
587 flush_fp_to_thread(current);
588
589 code = __parse_fpscr(current->thread.fpscr.val);
dc1c1ca3
SR		 590
591 _exception(SIGFPE, regs, code, regs->nip);
592}
593
594/*
595 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 596 * provide the PVR to user applications using the mfspr rd, PVR.
597 * Return non-zero if we can't emulate, or -EFAULT if the associated
598 * memory access caused an access fault. Return zero on success.
599 *
600 * There are a couple of ways to do this, either "decode" the instruction
601 * or directly match lots of bits. In this case, matching lots of
602 * bits is faster and easier.
86417780 603 *
14cf11af
PM		 604 */
605#define INST_MFSPR_PVR 0x7c1f42a6
606#define INST_MFSPR_PVR_MASK 0xfc1fffff
607
608#define INST_DCBA 0x7c0005ec
87589f08 609#define INST_DCBA_MASK 0xfc0007fe
14cf11af
PM		 610
611#define INST_MCRXR 0x7c000400
87589f08 612#define INST_MCRXR_MASK 0xfc0007fe
14cf11af
PM		 613
614#define INST_STRING 0x7c00042a
87589f08
PM		 615#define INST_STRING_MASK 0xfc0007fe
616#define INST_STRING_GEN_MASK 0xfc00067e
14cf11af
PM		 617#define INST_LSWI 0x7c0004aa
618#define INST_LSWX 0x7c00042a
619#define INST_STSWI 0x7c0005aa
620#define INST_STSWX 0x7c00052a
621
c3412dcb
WS		 622#define INST_POPCNTB 0x7c0000f4
623#define INST_POPCNTB_MASK 0xfc0007fe
624
c1469f13
KG		 625#define INST_ISEL 0x7c00001e
626#define INST_ISEL_MASK 0xfc00003e
627
14cf11af
PM		 628static int emulate_string_inst(struct pt_regs *regs, u32 instword)
629{
630 u8 rT = (instword >> 21) & 0x1f;
631 u8 rA = (instword >> 16) & 0x1f;
632 u8 NB_RB = (instword >> 11) & 0x1f;
633 u32 num_bytes;
634 unsigned long EA;
635 int pos = 0;
636
637 /* Early out if we are an invalid form of lswx */
638 if ((instword & INST_STRING_MASK) == INST_LSWX)
639 if ((rT == rA) || (rT == NB_RB))
640 return -EINVAL;
641
642 EA = (rA == 0) ? 0 : regs->gpr[rA];
643
644 switch (instword & INST_STRING_MASK) {
645 case INST_LSWX:
646 case INST_STSWX:
647 EA += NB_RB;
648 num_bytes = regs->xer & 0x7f;
649 break;
650 case INST_LSWI:
651 case INST_STSWI:
652 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
653 break;
654 default:
655 return -EINVAL;
656 }
657
658 while (num_bytes != 0)
659 {
660 u8 val;
661 u32 shift = 8 * (3 - (pos & 0x3));
662
663 switch ((instword & INST_STRING_MASK)) {
664 case INST_LSWX:
665 case INST_LSWI:
666 if (get_user(val, (u8 __user *)EA))
667 return -EFAULT;
668 /* first time updating this reg,
669 * zero it out */
670 if (pos == 0)
671 regs->gpr[rT] = 0;
672 regs->gpr[rT] |= val << shift;
673 break;
674 case INST_STSWI:
675 case INST_STSWX:
676 val = regs->gpr[rT] >> shift;
677 if (put_user(val, (u8 __user *)EA))
678 return -EFAULT;
679 break;
680 }
681 /* move EA to next address */
682 EA += 1;
683 num_bytes--;
684
685 /* manage our position within the register */
686 if (++pos == 4) {
687 pos = 0;
688 if (++rT == 32)
689 rT = 0;
690 }
691 }
692
693 return 0;
694}
695
c3412dcb
WS		 696static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
697{
698 u32 ra,rs;
699 unsigned long tmp;
700
701 ra = (instword >> 16) & 0x1f;
702 rs = (instword >> 21) & 0x1f;
703
704 tmp = regs->gpr[rs];
705 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
706 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
707 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
708 regs->gpr[ra] = tmp;
709
710 return 0;
711}
712
c1469f13
KG		 713static int emulate_isel(struct pt_regs *regs, u32 instword)
714{
715 u8 rT = (instword >> 21) & 0x1f;
716 u8 rA = (instword >> 16) & 0x1f;
717 u8 rB = (instword >> 11) & 0x1f;
718 u8 BC = (instword >> 6) & 0x1f;
719 u8 bit;
720 unsigned long tmp;
721
722 tmp = (rA == 0) ? 0 : regs->gpr[rA];
723 bit = (regs->ccr >> (31 - BC)) & 0x1;
724
725 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
726
727 return 0;
728}
729
14cf11af
PM		 730static int emulate_instruction(struct pt_regs *regs)
731{
732 u32 instword;
733 u32 rd;
734
fab5db97 735 if (!user_mode(regs) || (regs->msr & MSR_LE))
14cf11af
PM		 736 return -EINVAL;
737 CHECK_FULL_REGS(regs);
738
739 if (get_user(instword, (u32 __user *)(regs->nip)))
740 return -EFAULT;
741
742 /* Emulate the mfspr rD, PVR. */
743 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
744 rd = (instword >> 21) & 0x1f;
745 regs->gpr[rd] = mfspr(SPRN_PVR);
746 return 0;
747 }
748
749 /* Emulating the dcba insn is just a no-op. */
8dad3f92 750 if ((instword & INST_DCBA_MASK) == INST_DCBA)
14cf11af
PM		 751 return 0;
752
753 /* Emulate the mcrxr insn. */
754 if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
86417780 755 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 756 unsigned long msk = 0xf0000000UL >> shift;
757
758 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
759 regs->xer &= ~0xf0000000UL;
760 return 0;
761 }
762
763 /* Emulate load/store string insn. */
764 if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
765 return emulate_string_inst(regs, instword);
766
c3412dcb
WS		 767 /* Emulate the popcntb (Population Count Bytes) instruction. */
768 if ((instword & INST_POPCNTB_MASK) == INST_POPCNTB) {
769 return emulate_popcntb_inst(regs, instword);
770 }
771
c1469f13
KG		 772 /* Emulate isel (Integer Select) instruction */
773 if ((instword & INST_ISEL_MASK) == INST_ISEL) {
774 return emulate_isel(regs, instword);
775 }
776
14cf11af
PM		 777 return -EINVAL;
778}
779
73c9ceab 780int is_valid_bugaddr(unsigned long addr)
14cf11af 781{
73c9ceab 782 return is_kernel_addr(addr);
14cf11af
PM		 783}
784
8dad3f92 785void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 786{
787 unsigned int reason = get_reason(regs);
788 extern int do_mathemu(struct pt_regs *regs);
789
aa42c69c 790 /* We can now get here via a FP Unavailable exception if the core
04903a30 791 * has no FPU, in that case the reason flags will be 0 */
14cf11af 792
dc1c1ca3
SR		 793 if (reason & REASON_FP) {
794 /* IEEE FP exception */
795 parse_fpe(regs);
8dad3f92
PM		 796 return;
797 }
798 if (reason & REASON_TRAP) {
14cf11af 799 /* trap exception */
dc1c1ca3
SR		 800 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
801 == NOTIFY_STOP)
802 return;
14cf11af
PM		 803 if (debugger_bpt(regs))
804 return;
73c9ceab
JF		 805
806 if (!(regs->msr & MSR_PR) && /* not user-mode */
608e2619 807 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
14cf11af
PM		 808 regs->nip += 4;
809 return;
810 }
8dad3f92
PM		 811 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
812 return;
813 }
814
cd8a5673
PM		 815 local_irq_enable();
816
04903a30
KG		 817#ifdef CONFIG_MATH_EMULATION
818 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
819 * but there seems to be a hardware bug on the 405GP (RevD)
820 * that means ESR is sometimes set incorrectly - either to
821 * ESR_DST (!?) or 0. In the process of chasing this with the
822 * hardware people - not sure if it can happen on any illegal
823 * instruction or only on FP instructions, whether there is a
824 * pattern to occurences etc. -dgibson 31/Mar/2003 */
5fad293b
KG		 825 switch (do_mathemu(regs)) {
826 case 0:
04903a30
KG		 827 emulate_single_step(regs);
828 return;
5fad293b
KG		 829 case 1: {
830 int code = 0;
831 code = __parse_fpscr(current->thread.fpscr.val);
832 _exception(SIGFPE, regs, code, regs->nip);
833 return;
834 }
835 case -EFAULT:
836 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
837 return;
04903a30 838 }
5fad293b 839 /* fall through on any other errors */
04903a30
KG		 840#endif /* CONFIG_MATH_EMULATION */
841
8dad3f92
PM		 842 /* Try to emulate it if we should. */
843 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 844 switch (emulate_instruction(regs)) {
845 case 0:
846 regs->nip += 4;
847 emulate_single_step(regs);
8dad3f92 848 return;
14cf11af
PM		 849 case -EFAULT:
850 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 851 return;
14cf11af
PM		 852 }
853 }
8dad3f92
PM		 854
855 if (reason & REASON_PRIVILEGED)
856 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
857 else
858 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 859}
860
dc1c1ca3 861void alignment_exception(struct pt_regs *regs)
14cf11af 862{
4393c4f6 863 int sig, code, fixed = 0;
14cf11af 864
e9370ae1
PM		 865 /* we don't implement logging of alignment exceptions */
866 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
867 fixed = fix_alignment(regs);
14cf11af
PM		 868
869 if (fixed == 1) {
870 regs->nip += 4; /* skip over emulated instruction */
871 emulate_single_step(regs);
872 return;
873 }
874
dc1c1ca3 875 /* Operand address was bad */
14cf11af 876 if (fixed == -EFAULT) {
4393c4f6
BH		 877 sig = SIGSEGV;
878 code = SEGV_ACCERR;
879 } else {
880 sig = SIGBUS;
881 code = BUS_ADRALN;
14cf11af 882 }
4393c4f6
BH		 883 if (user_mode(regs))
884 _exception(sig, regs, code, regs->dar);
885 else
886 bad_page_fault(regs, regs->dar, sig);
14cf11af
PM		 887}
888
889void StackOverflow(struct pt_regs *regs)
890{
891 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
892 current, regs->gpr[1]);
893 debugger(regs);
894 show_regs(regs);
895 panic("kernel stack overflow");
896}
897
898void nonrecoverable_exception(struct pt_regs *regs)
899{
900 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
901 regs->nip, regs->msr);
902 debugger(regs);
903 die("nonrecoverable exception", regs, SIGKILL);
904}
905
906void trace_syscall(struct pt_regs *regs)
907{
908 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
19c5870c 909 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
14cf11af
PM		 910 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
911}
dc1c1ca3 912
dc1c1ca3
SR		 913void kernel_fp_unavailable_exception(struct pt_regs *regs)
914{
915 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
916 "%lx at %lx\n", regs->trap, regs->nip);
917 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
918}
dc1c1ca3
SR		 919
920void altivec_unavailable_exception(struct pt_regs *regs)
921{
dc1c1ca3
SR		 922 if (user_mode(regs)) {
923 /* A user program has executed an altivec instruction,
924 but this kernel doesn't support altivec. */
925 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
926 return;
927 }
6c4841c2 928
dc1c1ca3
SR		 929 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
930 "%lx at %lx\n", regs->trap, regs->nip);
931 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 932}
933
dc1c1ca3
SR		 934void performance_monitor_exception(struct pt_regs *regs)
935{
936 perf_irq(regs);
937}
dc1c1ca3 938
8dad3f92 939#ifdef CONFIG_8xx
14cf11af
PM		 940void SoftwareEmulation(struct pt_regs *regs)
941{
942 extern int do_mathemu(struct pt_regs *);
943 extern int Soft_emulate_8xx(struct pt_regs *);
5dd57a13 944#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 945 int errcode;
5dd57a13 946#endif
14cf11af
PM		 947
948 CHECK_FULL_REGS(regs);
949
950 if (!user_mode(regs)) {
951 debugger(regs);
952 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
953 }
954
955#ifdef CONFIG_MATH_EMULATION
956 errcode = do_mathemu(regs);
5fad293b
KG		 957
958 switch (errcode) {
959 case 0:
960 emulate_single_step(regs);
961 return;
962 case 1: {
963 int code = 0;
964 code = __parse_fpscr(current->thread.fpscr.val);
965 _exception(SIGFPE, regs, code, regs->nip);
966 return;
967 }
968 case -EFAULT:
969 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
970 return;
971 default:
972 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
973 return;
974 }
975
5dd57a13 976#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 977 errcode = Soft_emulate_8xx(regs);
5fad293b
KG		 978 switch (errcode) {
979 case 0:
14cf11af 980 emulate_single_step(regs);
5fad293b
KG		 981 return;
982 case 1:
983 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
984 return;
985 case -EFAULT:
986 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
987 return;
988 }
5dd57a13
SW		 989#else
990 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
5fad293b 991#endif
14cf11af 992}
8dad3f92 993#endif /* CONFIG_8xx */
14cf11af
PM		 994
995#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
996
997void DebugException(struct pt_regs *regs, unsigned long debug_status)
998{
999 if (debug_status & DBSR_IC) { /* instruction completion */
1000 regs->msr &= ~MSR_DE;
1001 if (user_mode(regs)) {
1002 current->thread.dbcr0 &= ~DBCR0_IC;
1003 } else {
1004 /* Disable instruction completion */
1005 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1006 /* Clear the instruction completion event */
1007 mtspr(SPRN_DBSR, DBSR_IC);
1008 if (debugger_sstep(regs))
1009 return;
1010 }
1011 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
1012 }
1013}
1014#endif /* CONFIG_4xx || CONFIG_BOOKE */
1015
1016#if !defined(CONFIG_TAU_INT)
1017void TAUException(struct pt_regs *regs)
1018{
1019 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1020 regs->nip, regs->msr, regs->trap, print_tainted());
1021}
1022#endif /* CONFIG_INT_TAU */
14cf11af
PM		 1023
1024#ifdef CONFIG_ALTIVEC
dc1c1ca3 1025void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 1026{
1027 int err;
1028
14cf11af
PM		 1029 if (!user_mode(regs)) {
1030 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1031 " at %lx\n", regs->nip);
8dad3f92 1032 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 1033 }
1034
dc1c1ca3 1035 flush_altivec_to_thread(current);
dc1c1ca3 1036
14cf11af
PM		 1037 err = emulate_altivec(regs);
1038 if (err == 0) {
1039 regs->nip += 4; /* skip emulated instruction */
1040 emulate_single_step(regs);
1041 return;
1042 }
1043
1044 if (err == -EFAULT) {
1045 /* got an error reading the instruction */
1046 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1047 } else {
1048 /* didn't recognize the instruction */
1049 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1050 if (printk_ratelimit())
1051 printk(KERN_ERR "Unrecognized altivec instruction "
1052 "in %s at %lx\n", current->comm, regs->nip);
1053 current->thread.vscr.u[3] |= 0x10000;
1054 }
1055}
1056#endif /* CONFIG_ALTIVEC */
1057
14cf11af
PM		 1058#ifdef CONFIG_FSL_BOOKE
1059void CacheLockingException(struct pt_regs *regs, unsigned long address,
1060 unsigned long error_code)
1061{
1062 /* We treat cache locking instructions from the user
1063 * as priv ops, in the future we could try to do
1064 * something smarter
1065 */
1066 if (error_code & (ESR_DLK|ESR_ILK))
1067 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1068 return;
1069}
1070#endif /* CONFIG_FSL_BOOKE */
1071
1072#ifdef CONFIG_SPE
1073void SPEFloatingPointException(struct pt_regs *regs)
1074{
1075 unsigned long spefscr;
1076 int fpexc_mode;
1077 int code = 0;
1078
1079 spefscr = current->thread.spefscr;
1080 fpexc_mode = current->thread.fpexc_mode;
1081
1082 /* Hardware does not neccessarily set sticky
1083 * underflow/overflow/invalid flags */
1084 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1085 code = FPE_FLTOVF;
1086 spefscr |= SPEFSCR_FOVFS;
1087 }
1088 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1089 code = FPE_FLTUND;
1090 spefscr |= SPEFSCR_FUNFS;
1091 }
1092 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1093 code = FPE_FLTDIV;
1094 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1095 code = FPE_FLTINV;
1096 spefscr |= SPEFSCR_FINVS;
1097 }
1098 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1099 code = FPE_FLTRES;
1100
1101 current->thread.spefscr = spefscr;
1102
1103 _exception(SIGFPE, regs, code, regs->nip);
1104 return;
1105}
1106#endif
1107
dc1c1ca3
SR		 1108/*
1109 * We enter here if we get an unrecoverable exception, that is, one
1110 * that happened at a point where the RI (recoverable interrupt) bit
1111 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1112 * we therefore lost state by taking this exception.
1113 */
1114void unrecoverable_exception(struct pt_regs *regs)
1115{
1116 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1117 regs->trap, regs->nip);
1118 die("Unrecoverable exception", regs, SIGABRT);
1119}
dc1c1ca3 1120
14cf11af
PM		 1121#ifdef CONFIG_BOOKE_WDT
1122/*
1123 * Default handler for a Watchdog exception,
1124 * spins until a reboot occurs
1125 */
1126void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1127{
1128 /* Generic WatchdogHandler, implement your own */
1129 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1130 return;
1131}
1132
1133void WatchdogException(struct pt_regs *regs)
1134{
1135 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1136 WatchdogHandler(regs);
1137}
1138#endif
dc1c1ca3 1139
dc1c1ca3
SR		 1140/*
1141 * We enter here if we discover during exception entry that we are
1142 * running in supervisor mode with a userspace value in the stack pointer.
1143 */
1144void kernel_bad_stack(struct pt_regs *regs)
1145{
1146 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1147 regs->gpr[1], regs->nip);
1148 die("Bad kernel stack pointer", regs, SIGABRT);
1149}
14cf11af
PM		 1150
1151void __init trap_init(void)
1152{
1153}
Linux kernel - Deliverables
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