Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af PM |
24 | #include <linux/slab.h> |
25 | #include <linux/user.h> | |
26 | #include <linux/a.out.h> | |
27 | #include <linux/interrupt.h> | |
14cf11af PM |
28 | #include <linux/init.h> |
29 | #include <linux/module.h> | |
8dad3f92 | 30 | #include <linux/prctl.h> |
14cf11af PM |
31 | #include <linux/delay.h> |
32 | #include <linux/kprobes.h> | |
cc532915 | 33 | #include <linux/kexec.h> |
5474c120 | 34 | #include <linux/backlight.h> |
73c9ceab | 35 | #include <linux/bug.h> |
1eeb66a1 | 36 | #include <linux/kdebug.h> |
14cf11af PM |
37 | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/system.h> | |
41 | #include <asm/io.h> | |
86417780 PM |
42 | #include <asm/machdep.h> |
43 | #include <asm/rtas.h> | |
f7f6f4fe | 44 | #include <asm/pmc.h> |
dc1c1ca3 | 45 | #ifdef CONFIG_PPC32 |
14cf11af | 46 | #include <asm/reg.h> |
86417780 | 47 | #endif |
14cf11af PM |
48 | #ifdef CONFIG_PMAC_BACKLIGHT |
49 | #include <asm/backlight.h> | |
50 | #endif | |
dc1c1ca3 | 51 | #ifdef CONFIG_PPC64 |
86417780 | 52 | #include <asm/firmware.h> |
dc1c1ca3 | 53 | #include <asm/processor.h> |
dc1c1ca3 | 54 | #endif |
c0ce7d08 | 55 | #include <asm/kexec.h> |
dc1c1ca3 | 56 | |
14cf11af PM |
57 | #ifdef CONFIG_DEBUGGER |
58 | int (*__debugger)(struct pt_regs *regs); | |
59 | int (*__debugger_ipi)(struct pt_regs *regs); | |
60 | int (*__debugger_bpt)(struct pt_regs *regs); | |
61 | int (*__debugger_sstep)(struct pt_regs *regs); | |
62 | int (*__debugger_iabr_match)(struct pt_regs *regs); | |
63 | int (*__debugger_dabr_match)(struct pt_regs *regs); | |
64 | int (*__debugger_fault_handler)(struct pt_regs *regs); | |
65 | ||
66 | EXPORT_SYMBOL(__debugger); | |
67 | EXPORT_SYMBOL(__debugger_ipi); | |
68 | EXPORT_SYMBOL(__debugger_bpt); | |
69 | EXPORT_SYMBOL(__debugger_sstep); | |
70 | EXPORT_SYMBOL(__debugger_iabr_match); | |
71 | EXPORT_SYMBOL(__debugger_dabr_match); | |
72 | EXPORT_SYMBOL(__debugger_fault_handler); | |
73 | #endif | |
74 | ||
14cf11af PM |
75 | /* |
76 | * Trap & Exception support | |
77 | */ | |
78 | ||
6031d9d9 | 79 | #ifdef CONFIG_PMAC_BACKLIGHT |
80 | static void pmac_backlight_unblank(void) | |
81 | { | |
82 | mutex_lock(&pmac_backlight_mutex); | |
83 | if (pmac_backlight) { | |
84 | struct backlight_properties *props; | |
85 | ||
86 | props = &pmac_backlight->props; | |
87 | props->brightness = props->max_brightness; | |
88 | props->power = FB_BLANK_UNBLANK; | |
89 | backlight_update_status(pmac_backlight); | |
90 | } | |
91 | mutex_unlock(&pmac_backlight_mutex); | |
92 | } | |
93 | #else | |
94 | static inline void pmac_backlight_unblank(void) { } | |
95 | #endif | |
96 | ||
14cf11af PM |
97 | int die(const char *str, struct pt_regs *regs, long err) |
98 | { | |
34c2a14f | 99 | static struct { |
100 | spinlock_t lock; | |
101 | u32 lock_owner; | |
102 | int lock_owner_depth; | |
103 | } die = { | |
104 | .lock = __SPIN_LOCK_UNLOCKED(die.lock), | |
105 | .lock_owner = -1, | |
106 | .lock_owner_depth = 0 | |
107 | }; | |
c0ce7d08 | 108 | static int die_counter; |
34c2a14f | 109 | unsigned long flags; |
14cf11af PM |
110 | |
111 | if (debugger(regs)) | |
112 | return 1; | |
113 | ||
293e4688 | 114 | oops_enter(); |
115 | ||
34c2a14f | 116 | if (die.lock_owner != raw_smp_processor_id()) { |
117 | console_verbose(); | |
118 | spin_lock_irqsave(&die.lock, flags); | |
119 | die.lock_owner = smp_processor_id(); | |
120 | die.lock_owner_depth = 0; | |
121 | bust_spinlocks(1); | |
122 | if (machine_is(powermac)) | |
123 | pmac_backlight_unblank(); | |
124 | } else { | |
125 | local_save_flags(flags); | |
126 | } | |
5474c120 | 127 | |
34c2a14f | 128 | if (++die.lock_owner_depth < 3) { |
129 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 130 | #ifdef CONFIG_PREEMPT |
34c2a14f | 131 | printk("PREEMPT "); |
14cf11af PM |
132 | #endif |
133 | #ifdef CONFIG_SMP | |
34c2a14f | 134 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
135 | #endif |
136 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 137 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
138 | #endif |
139 | #ifdef CONFIG_NUMA | |
34c2a14f | 140 | printk("NUMA "); |
14cf11af | 141 | #endif |
ae7f4463 | 142 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 143 | |
144 | print_modules(); | |
145 | show_regs(regs); | |
146 | } else { | |
147 | printk("Recursive die() failure, output suppressed\n"); | |
148 | } | |
e8222502 | 149 | |
14cf11af | 150 | bust_spinlocks(0); |
34c2a14f | 151 | die.lock_owner = -1; |
bcdcd8e7 | 152 | add_taint(TAINT_DIE); |
34c2a14f | 153 | spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 154 | |
c0ce7d08 DW |
155 | if (kexec_should_crash(current) || |
156 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 157 | crash_kexec(regs); |
c0ce7d08 | 158 | crash_kexec_secondary(regs); |
14cf11af PM |
159 | |
160 | if (in_interrupt()) | |
161 | panic("Fatal exception in interrupt"); | |
162 | ||
cea6a4ba | 163 | if (panic_on_oops) |
012c437d | 164 | panic("Fatal exception"); |
cea6a4ba | 165 | |
293e4688 | 166 | oops_exit(); |
14cf11af PM |
167 | do_exit(err); |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
173 | { | |
174 | siginfo_t info; | |
175 | ||
176 | if (!user_mode(regs)) { | |
177 | if (die("Exception in kernel mode", regs, signr)) | |
178 | return; | |
179 | } | |
180 | ||
181 | memset(&info, 0, sizeof(info)); | |
182 | info.si_signo = signr; | |
183 | info.si_code = code; | |
184 | info.si_addr = (void __user *) addr; | |
185 | force_sig_info(signr, &info, current); | |
186 | ||
187 | /* | |
188 | * Init gets no signals that it doesn't have a handler for. | |
189 | * That's all very well, but if it has caused a synchronous | |
190 | * exception and we ignore the resulting signal, it will just | |
191 | * generate the same exception over and over again and we get | |
192 | * nowhere. Better to kill it and let the kernel panic. | |
193 | */ | |
60bccbed | 194 | if (is_init(current)) { |
14cf11af PM |
195 | __sighandler_t handler; |
196 | ||
197 | spin_lock_irq(¤t->sighand->siglock); | |
198 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
199 | spin_unlock_irq(¤t->sighand->siglock); | |
200 | if (handler == SIG_DFL) { | |
201 | /* init has generated a synchronous exception | |
202 | and it doesn't have a handler for the signal */ | |
203 | printk(KERN_CRIT "init has generated signal %d " | |
204 | "but has no handler for it\n", signr); | |
205 | do_exit(signr); | |
206 | } | |
207 | } | |
208 | } | |
209 | ||
210 | #ifdef CONFIG_PPC64 | |
211 | void system_reset_exception(struct pt_regs *regs) | |
212 | { | |
213 | /* See if any machine dependent calls */ | |
c902be71 AB |
214 | if (ppc_md.system_reset_exception) { |
215 | if (ppc_md.system_reset_exception(regs)) | |
216 | return; | |
217 | } | |
14cf11af | 218 | |
c0ce7d08 DW |
219 | #ifdef CONFIG_KEXEC |
220 | cpu_set(smp_processor_id(), cpus_in_sr); | |
221 | #endif | |
222 | ||
8dad3f92 | 223 | die("System Reset", regs, SIGABRT); |
14cf11af | 224 | |
eac8392f DW |
225 | /* |
226 | * Some CPUs when released from the debugger will execute this path. | |
227 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
228 | * hung before entering the debugger it will return to the hung | |
229 | * state when exiting this function. This causes a problem in | |
230 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
231 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
232 | * here. If a kdump had not been initiated or we exit the debugger | |
233 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
234 | * will return after 5ms and the CPU returns to its previous state. | |
235 | */ | |
236 | crash_kexec_secondary(regs); | |
237 | ||
14cf11af PM |
238 | /* Must die if the interrupt is not recoverable */ |
239 | if (!(regs->msr & MSR_RI)) | |
240 | panic("Unrecoverable System Reset"); | |
241 | ||
242 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
243 | } | |
244 | #endif | |
245 | ||
246 | /* | |
247 | * I/O accesses can cause machine checks on powermacs. | |
248 | * Check if the NIP corresponds to the address of a sync | |
249 | * instruction for which there is an entry in the exception | |
250 | * table. | |
251 | * Note that the 601 only takes a machine check on TEA | |
252 | * (transfer error ack) signal assertion, and does not | |
253 | * set any of the top 16 bits of SRR1. | |
254 | * -- paulus. | |
255 | */ | |
256 | static inline int check_io_access(struct pt_regs *regs) | |
257 | { | |
68a64357 | 258 | #ifdef CONFIG_PPC32 |
14cf11af PM |
259 | unsigned long msr = regs->msr; |
260 | const struct exception_table_entry *entry; | |
261 | unsigned int *nip = (unsigned int *)regs->nip; | |
262 | ||
263 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
264 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
265 | /* | |
266 | * Check that it's a sync instruction, or somewhere | |
267 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
268 | * As the address is in the exception table | |
269 | * we should be able to read the instr there. | |
270 | * For the debug message, we look at the preceding | |
271 | * load or store. | |
272 | */ | |
273 | if (*nip == 0x60000000) /* nop */ | |
274 | nip -= 2; | |
275 | else if (*nip == 0x4c00012c) /* isync */ | |
276 | --nip; | |
277 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
278 | /* sync or twi */ | |
279 | unsigned int rb; | |
280 | ||
281 | --nip; | |
282 | rb = (*nip >> 11) & 0x1f; | |
283 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
284 | (*nip & 0x100)? "OUT to": "IN from", | |
285 | regs->gpr[rb] - _IO_BASE, nip); | |
286 | regs->msr |= MSR_RI; | |
287 | regs->nip = entry->fixup; | |
288 | return 1; | |
289 | } | |
290 | } | |
68a64357 | 291 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
292 | return 0; |
293 | } | |
294 | ||
295 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
296 | /* On 4xx, the reason for the machine check or program exception | |
297 | is in the ESR. */ | |
298 | #define get_reason(regs) ((regs)->dsisr) | |
299 | #ifndef CONFIG_FSL_BOOKE | |
300 | #define get_mc_reason(regs) ((regs)->dsisr) | |
301 | #else | |
86d7a9a9 | 302 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) |
14cf11af PM |
303 | #endif |
304 | #define REASON_FP ESR_FP | |
305 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
306 | #define REASON_PRIVILEGED ESR_PPR | |
307 | #define REASON_TRAP ESR_PTR | |
308 | ||
309 | /* single-step stuff */ | |
310 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
311 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
312 | ||
313 | #else | |
314 | /* On non-4xx, the reason for the machine check or program | |
315 | exception is in the MSR. */ | |
316 | #define get_reason(regs) ((regs)->msr) | |
317 | #define get_mc_reason(regs) ((regs)->msr) | |
318 | #define REASON_FP 0x100000 | |
319 | #define REASON_ILLEGAL 0x80000 | |
320 | #define REASON_PRIVILEGED 0x40000 | |
321 | #define REASON_TRAP 0x20000 | |
322 | ||
323 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
324 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
325 | #endif | |
326 | ||
75918a4b | 327 | static int generic_machine_check_exception(struct pt_regs *regs) |
14cf11af | 328 | { |
1a6a4ffe | 329 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 330 | |
14cf11af PM |
331 | #if defined(CONFIG_4xx) && !defined(CONFIG_440A) |
332 | if (reason & ESR_IMCP) { | |
333 | printk("Instruction"); | |
334 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
335 | } else | |
336 | printk("Data"); | |
337 | printk(" machine check in kernel mode.\n"); | |
338 | #elif defined(CONFIG_440A) | |
339 | printk("Machine check in kernel mode.\n"); | |
340 | if (reason & ESR_IMCP){ | |
341 | printk("Instruction Synchronous Machine Check exception\n"); | |
342 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
343 | } | |
344 | else { | |
345 | u32 mcsr = mfspr(SPRN_MCSR); | |
346 | if (mcsr & MCSR_IB) | |
347 | printk("Instruction Read PLB Error\n"); | |
348 | if (mcsr & MCSR_DRB) | |
349 | printk("Data Read PLB Error\n"); | |
350 | if (mcsr & MCSR_DWB) | |
351 | printk("Data Write PLB Error\n"); | |
352 | if (mcsr & MCSR_TLBP) | |
353 | printk("TLB Parity Error\n"); | |
354 | if (mcsr & MCSR_ICP){ | |
355 | flush_instruction_cache(); | |
356 | printk("I-Cache Parity Error\n"); | |
357 | } | |
358 | if (mcsr & MCSR_DCSP) | |
359 | printk("D-Cache Search Parity Error\n"); | |
360 | if (mcsr & MCSR_DCFP) | |
361 | printk("D-Cache Flush Parity Error\n"); | |
362 | if (mcsr & MCSR_IMPE) | |
363 | printk("Machine Check exception is imprecise\n"); | |
364 | ||
365 | /* Clear MCSR */ | |
366 | mtspr(SPRN_MCSR, mcsr); | |
367 | } | |
368 | #elif defined (CONFIG_E500) | |
369 | printk("Machine check in kernel mode.\n"); | |
370 | printk("Caused by (from MCSR=%lx): ", reason); | |
371 | ||
372 | if (reason & MCSR_MCP) | |
373 | printk("Machine Check Signal\n"); | |
374 | if (reason & MCSR_ICPERR) | |
375 | printk("Instruction Cache Parity Error\n"); | |
376 | if (reason & MCSR_DCP_PERR) | |
377 | printk("Data Cache Push Parity Error\n"); | |
378 | if (reason & MCSR_DCPERR) | |
379 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
380 | if (reason & MCSR_BUS_IAERR) |
381 | printk("Bus - Instruction Address Error\n"); | |
382 | if (reason & MCSR_BUS_RAERR) | |
383 | printk("Bus - Read Address Error\n"); | |
384 | if (reason & MCSR_BUS_WAERR) | |
385 | printk("Bus - Write Address Error\n"); | |
386 | if (reason & MCSR_BUS_IBERR) | |
387 | printk("Bus - Instruction Data Error\n"); | |
388 | if (reason & MCSR_BUS_RBERR) | |
389 | printk("Bus - Read Data Bus Error\n"); | |
390 | if (reason & MCSR_BUS_WBERR) | |
391 | printk("Bus - Read Data Bus Error\n"); | |
392 | if (reason & MCSR_BUS_IPERR) | |
393 | printk("Bus - Instruction Parity Error\n"); | |
394 | if (reason & MCSR_BUS_RPERR) | |
395 | printk("Bus - Read Parity Error\n"); | |
396 | #elif defined (CONFIG_E200) | |
397 | printk("Machine check in kernel mode.\n"); | |
398 | printk("Caused by (from MCSR=%lx): ", reason); | |
399 | ||
400 | if (reason & MCSR_MCP) | |
401 | printk("Machine Check Signal\n"); | |
402 | if (reason & MCSR_CP_PERR) | |
403 | printk("Cache Push Parity Error\n"); | |
404 | if (reason & MCSR_CPERR) | |
405 | printk("Cache Parity Error\n"); | |
406 | if (reason & MCSR_EXCP_ERR) | |
407 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
408 | if (reason & MCSR_BUS_IRERR) | |
409 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
410 | if (reason & MCSR_BUS_DRERR) | |
411 | printk("Bus - Read Bus Error on data load\n"); | |
412 | if (reason & MCSR_BUS_WRERR) | |
413 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
414 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | |
415 | printk("Machine check in kernel mode.\n"); | |
416 | printk("Caused by (from SRR1=%lx): ", reason); | |
417 | switch (reason & 0x601F0000) { | |
418 | case 0x80000: | |
419 | printk("Machine check signal\n"); | |
420 | break; | |
421 | case 0: /* for 601 */ | |
422 | case 0x40000: | |
423 | case 0x140000: /* 7450 MSS error and TEA */ | |
424 | printk("Transfer error ack signal\n"); | |
425 | break; | |
426 | case 0x20000: | |
427 | printk("Data parity error signal\n"); | |
428 | break; | |
429 | case 0x10000: | |
430 | printk("Address parity error signal\n"); | |
431 | break; | |
432 | case 0x20000000: | |
433 | printk("L1 Data Cache error\n"); | |
434 | break; | |
435 | case 0x40000000: | |
436 | printk("L1 Instruction Cache error\n"); | |
437 | break; | |
438 | case 0x00100000: | |
439 | printk("L2 data cache parity error\n"); | |
440 | break; | |
441 | default: | |
442 | printk("Unknown values in msr\n"); | |
443 | } | |
444 | #endif /* CONFIG_4xx */ | |
445 | ||
75918a4b OJ |
446 | return 0; |
447 | } | |
448 | ||
449 | void machine_check_exception(struct pt_regs *regs) | |
450 | { | |
451 | int recover = 0; | |
452 | ||
453 | /* See if any machine dependent calls */ | |
454 | if (ppc_md.machine_check_exception) | |
455 | recover = ppc_md.machine_check_exception(regs); | |
456 | else | |
457 | recover = generic_machine_check_exception(regs); | |
458 | ||
459 | if (recover) | |
460 | return; | |
461 | ||
462 | if (user_mode(regs)) { | |
463 | regs->msr |= MSR_RI; | |
464 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
465 | return; | |
466 | } | |
467 | ||
468 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
469 | /* the qspan pci read routines can cause machine checks -- Cort */ | |
470 | bad_page_fault(regs, regs->dar, SIGBUS); | |
471 | return; | |
472 | #endif | |
473 | ||
474 | if (debugger_fault_handler(regs)) { | |
475 | regs->msr |= MSR_RI; | |
476 | return; | |
477 | } | |
478 | ||
479 | if (check_io_access(regs)) | |
480 | return; | |
481 | ||
14cf11af PM |
482 | if (debugger_fault_handler(regs)) |
483 | return; | |
8dad3f92 | 484 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
485 | |
486 | /* Must die if the interrupt is not recoverable */ | |
487 | if (!(regs->msr & MSR_RI)) | |
488 | panic("Unrecoverable Machine check"); | |
489 | } | |
490 | ||
491 | void SMIException(struct pt_regs *regs) | |
492 | { | |
493 | die("System Management Interrupt", regs, SIGABRT); | |
494 | } | |
495 | ||
dc1c1ca3 | 496 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
497 | { |
498 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
499 | regs->nip, regs->msr, regs->trap); | |
500 | ||
501 | _exception(SIGTRAP, regs, 0, 0); | |
502 | } | |
503 | ||
dc1c1ca3 | 504 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
505 | { |
506 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
507 | 5, SIGTRAP) == NOTIFY_STOP) | |
508 | return; | |
509 | if (debugger_iabr_match(regs)) | |
510 | return; | |
511 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
512 | } | |
513 | ||
514 | void RunModeException(struct pt_regs *regs) | |
515 | { | |
516 | _exception(SIGTRAP, regs, 0, 0); | |
517 | } | |
518 | ||
8dad3f92 | 519 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
520 | { |
521 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
522 | ||
523 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
524 | 5, SIGTRAP) == NOTIFY_STOP) | |
525 | return; | |
526 | if (debugger_sstep(regs)) | |
527 | return; | |
528 | ||
529 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
530 | } | |
531 | ||
532 | /* | |
533 | * After we have successfully emulated an instruction, we have to | |
534 | * check if the instruction was being single-stepped, and if so, | |
535 | * pretend we got a single-step exception. This was pointed out | |
536 | * by Kumar Gala. -- paulus | |
537 | */ | |
8dad3f92 | 538 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
539 | { |
540 | if (single_stepping(regs)) { | |
541 | clear_single_step(regs); | |
542 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
543 | } | |
544 | } | |
545 | ||
5fad293b | 546 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 547 | { |
5fad293b | 548 | int ret = 0; |
dc1c1ca3 SR |
549 | |
550 | /* Invalid operation */ | |
551 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 552 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
553 | |
554 | /* Overflow */ | |
555 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 556 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
557 | |
558 | /* Underflow */ | |
559 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 560 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
561 | |
562 | /* Divide by zero */ | |
563 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 564 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
565 | |
566 | /* Inexact result */ | |
567 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
568 | ret = FPE_FLTRES; |
569 | ||
570 | return ret; | |
571 | } | |
572 | ||
573 | static void parse_fpe(struct pt_regs *regs) | |
574 | { | |
575 | int code = 0; | |
576 | ||
577 | flush_fp_to_thread(current); | |
578 | ||
579 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
580 | |
581 | _exception(SIGFPE, regs, code, regs->nip); | |
582 | } | |
583 | ||
584 | /* | |
585 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
586 | * provide the PVR to user applications using the mfspr rd, PVR. |
587 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
588 | * memory access caused an access fault. Return zero on success. | |
589 | * | |
590 | * There are a couple of ways to do this, either "decode" the instruction | |
591 | * or directly match lots of bits. In this case, matching lots of | |
592 | * bits is faster and easier. | |
86417780 | 593 | * |
14cf11af PM |
594 | */ |
595 | #define INST_MFSPR_PVR 0x7c1f42a6 | |
596 | #define INST_MFSPR_PVR_MASK 0xfc1fffff | |
597 | ||
598 | #define INST_DCBA 0x7c0005ec | |
87589f08 | 599 | #define INST_DCBA_MASK 0xfc0007fe |
14cf11af PM |
600 | |
601 | #define INST_MCRXR 0x7c000400 | |
87589f08 | 602 | #define INST_MCRXR_MASK 0xfc0007fe |
14cf11af PM |
603 | |
604 | #define INST_STRING 0x7c00042a | |
87589f08 PM |
605 | #define INST_STRING_MASK 0xfc0007fe |
606 | #define INST_STRING_GEN_MASK 0xfc00067e | |
14cf11af PM |
607 | #define INST_LSWI 0x7c0004aa |
608 | #define INST_LSWX 0x7c00042a | |
609 | #define INST_STSWI 0x7c0005aa | |
610 | #define INST_STSWX 0x7c00052a | |
611 | ||
c3412dcb WS |
612 | #define INST_POPCNTB 0x7c0000f4 |
613 | #define INST_POPCNTB_MASK 0xfc0007fe | |
614 | ||
14cf11af PM |
615 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
616 | { | |
617 | u8 rT = (instword >> 21) & 0x1f; | |
618 | u8 rA = (instword >> 16) & 0x1f; | |
619 | u8 NB_RB = (instword >> 11) & 0x1f; | |
620 | u32 num_bytes; | |
621 | unsigned long EA; | |
622 | int pos = 0; | |
623 | ||
624 | /* Early out if we are an invalid form of lswx */ | |
625 | if ((instword & INST_STRING_MASK) == INST_LSWX) | |
626 | if ((rT == rA) || (rT == NB_RB)) | |
627 | return -EINVAL; | |
628 | ||
629 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
630 | ||
631 | switch (instword & INST_STRING_MASK) { | |
632 | case INST_LSWX: | |
633 | case INST_STSWX: | |
634 | EA += NB_RB; | |
635 | num_bytes = regs->xer & 0x7f; | |
636 | break; | |
637 | case INST_LSWI: | |
638 | case INST_STSWI: | |
639 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; | |
640 | break; | |
641 | default: | |
642 | return -EINVAL; | |
643 | } | |
644 | ||
645 | while (num_bytes != 0) | |
646 | { | |
647 | u8 val; | |
648 | u32 shift = 8 * (3 - (pos & 0x3)); | |
649 | ||
650 | switch ((instword & INST_STRING_MASK)) { | |
651 | case INST_LSWX: | |
652 | case INST_LSWI: | |
653 | if (get_user(val, (u8 __user *)EA)) | |
654 | return -EFAULT; | |
655 | /* first time updating this reg, | |
656 | * zero it out */ | |
657 | if (pos == 0) | |
658 | regs->gpr[rT] = 0; | |
659 | regs->gpr[rT] |= val << shift; | |
660 | break; | |
661 | case INST_STSWI: | |
662 | case INST_STSWX: | |
663 | val = regs->gpr[rT] >> shift; | |
664 | if (put_user(val, (u8 __user *)EA)) | |
665 | return -EFAULT; | |
666 | break; | |
667 | } | |
668 | /* move EA to next address */ | |
669 | EA += 1; | |
670 | num_bytes--; | |
671 | ||
672 | /* manage our position within the register */ | |
673 | if (++pos == 4) { | |
674 | pos = 0; | |
675 | if (++rT == 32) | |
676 | rT = 0; | |
677 | } | |
678 | } | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
c3412dcb WS |
683 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
684 | { | |
685 | u32 ra,rs; | |
686 | unsigned long tmp; | |
687 | ||
688 | ra = (instword >> 16) & 0x1f; | |
689 | rs = (instword >> 21) & 0x1f; | |
690 | ||
691 | tmp = regs->gpr[rs]; | |
692 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
693 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
694 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
695 | regs->gpr[ra] = tmp; | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
14cf11af PM |
700 | static int emulate_instruction(struct pt_regs *regs) |
701 | { | |
702 | u32 instword; | |
703 | u32 rd; | |
704 | ||
fab5db97 | 705 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
706 | return -EINVAL; |
707 | CHECK_FULL_REGS(regs); | |
708 | ||
709 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
710 | return -EFAULT; | |
711 | ||
712 | /* Emulate the mfspr rD, PVR. */ | |
713 | if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { | |
714 | rd = (instword >> 21) & 0x1f; | |
715 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
716 | return 0; | |
717 | } | |
718 | ||
719 | /* Emulating the dcba insn is just a no-op. */ | |
8dad3f92 | 720 | if ((instword & INST_DCBA_MASK) == INST_DCBA) |
14cf11af PM |
721 | return 0; |
722 | ||
723 | /* Emulate the mcrxr insn. */ | |
724 | if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { | |
86417780 | 725 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
726 | unsigned long msk = 0xf0000000UL >> shift; |
727 | ||
728 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); | |
729 | regs->xer &= ~0xf0000000UL; | |
730 | return 0; | |
731 | } | |
732 | ||
733 | /* Emulate load/store string insn. */ | |
734 | if ((instword & INST_STRING_GEN_MASK) == INST_STRING) | |
735 | return emulate_string_inst(regs, instword); | |
736 | ||
c3412dcb WS |
737 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
738 | if ((instword & INST_POPCNTB_MASK) == INST_POPCNTB) { | |
739 | return emulate_popcntb_inst(regs, instword); | |
740 | } | |
741 | ||
14cf11af PM |
742 | return -EINVAL; |
743 | } | |
744 | ||
73c9ceab | 745 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 746 | { |
73c9ceab | 747 | return is_kernel_addr(addr); |
14cf11af PM |
748 | } |
749 | ||
8dad3f92 | 750 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
751 | { |
752 | unsigned int reason = get_reason(regs); | |
753 | extern int do_mathemu(struct pt_regs *regs); | |
754 | ||
aa42c69c | 755 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 756 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 757 | |
dc1c1ca3 SR |
758 | if (reason & REASON_FP) { |
759 | /* IEEE FP exception */ | |
760 | parse_fpe(regs); | |
8dad3f92 PM |
761 | return; |
762 | } | |
763 | if (reason & REASON_TRAP) { | |
14cf11af | 764 | /* trap exception */ |
dc1c1ca3 SR |
765 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
766 | == NOTIFY_STOP) | |
767 | return; | |
14cf11af PM |
768 | if (debugger_bpt(regs)) |
769 | return; | |
73c9ceab JF |
770 | |
771 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 772 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
773 | regs->nip += 4; |
774 | return; | |
775 | } | |
8dad3f92 PM |
776 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
777 | return; | |
778 | } | |
779 | ||
cd8a5673 PM |
780 | local_irq_enable(); |
781 | ||
04903a30 KG |
782 | #ifdef CONFIG_MATH_EMULATION |
783 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
784 | * but there seems to be a hardware bug on the 405GP (RevD) | |
785 | * that means ESR is sometimes set incorrectly - either to | |
786 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
787 | * hardware people - not sure if it can happen on any illegal | |
788 | * instruction or only on FP instructions, whether there is a | |
789 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
790 | switch (do_mathemu(regs)) { |
791 | case 0: | |
04903a30 KG |
792 | emulate_single_step(regs); |
793 | return; | |
5fad293b KG |
794 | case 1: { |
795 | int code = 0; | |
796 | code = __parse_fpscr(current->thread.fpscr.val); | |
797 | _exception(SIGFPE, regs, code, regs->nip); | |
798 | return; | |
799 | } | |
800 | case -EFAULT: | |
801 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
802 | return; | |
04903a30 | 803 | } |
5fad293b | 804 | /* fall through on any other errors */ |
04903a30 KG |
805 | #endif /* CONFIG_MATH_EMULATION */ |
806 | ||
8dad3f92 PM |
807 | /* Try to emulate it if we should. */ |
808 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
809 | switch (emulate_instruction(regs)) { |
810 | case 0: | |
811 | regs->nip += 4; | |
812 | emulate_single_step(regs); | |
8dad3f92 | 813 | return; |
14cf11af PM |
814 | case -EFAULT: |
815 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 816 | return; |
14cf11af PM |
817 | } |
818 | } | |
8dad3f92 PM |
819 | |
820 | if (reason & REASON_PRIVILEGED) | |
821 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
822 | else | |
823 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
824 | } |
825 | ||
dc1c1ca3 | 826 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 827 | { |
4393c4f6 | 828 | int sig, code, fixed = 0; |
14cf11af | 829 | |
e9370ae1 PM |
830 | /* we don't implement logging of alignment exceptions */ |
831 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
832 | fixed = fix_alignment(regs); | |
14cf11af PM |
833 | |
834 | if (fixed == 1) { | |
835 | regs->nip += 4; /* skip over emulated instruction */ | |
836 | emulate_single_step(regs); | |
837 | return; | |
838 | } | |
839 | ||
dc1c1ca3 | 840 | /* Operand address was bad */ |
14cf11af | 841 | if (fixed == -EFAULT) { |
4393c4f6 BH |
842 | sig = SIGSEGV; |
843 | code = SEGV_ACCERR; | |
844 | } else { | |
845 | sig = SIGBUS; | |
846 | code = BUS_ADRALN; | |
14cf11af | 847 | } |
4393c4f6 BH |
848 | if (user_mode(regs)) |
849 | _exception(sig, regs, code, regs->dar); | |
850 | else | |
851 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
852 | } |
853 | ||
854 | void StackOverflow(struct pt_regs *regs) | |
855 | { | |
856 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
857 | current, regs->gpr[1]); | |
858 | debugger(regs); | |
859 | show_regs(regs); | |
860 | panic("kernel stack overflow"); | |
861 | } | |
862 | ||
863 | void nonrecoverable_exception(struct pt_regs *regs) | |
864 | { | |
865 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
866 | regs->nip, regs->msr); | |
867 | debugger(regs); | |
868 | die("nonrecoverable exception", regs, SIGKILL); | |
869 | } | |
870 | ||
871 | void trace_syscall(struct pt_regs *regs) | |
872 | { | |
873 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
874 | current, current->pid, regs->nip, regs->link, regs->gpr[0], | |
875 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); | |
876 | } | |
dc1c1ca3 | 877 | |
dc1c1ca3 SR |
878 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
879 | { | |
880 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
881 | "%lx at %lx\n", regs->trap, regs->nip); | |
882 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
883 | } | |
dc1c1ca3 SR |
884 | |
885 | void altivec_unavailable_exception(struct pt_regs *regs) | |
886 | { | |
dc1c1ca3 SR |
887 | if (user_mode(regs)) { |
888 | /* A user program has executed an altivec instruction, | |
889 | but this kernel doesn't support altivec. */ | |
890 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
891 | return; | |
892 | } | |
6c4841c2 | 893 | |
dc1c1ca3 SR |
894 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
895 | "%lx at %lx\n", regs->trap, regs->nip); | |
896 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
897 | } |
898 | ||
dc1c1ca3 SR |
899 | void performance_monitor_exception(struct pt_regs *regs) |
900 | { | |
901 | perf_irq(regs); | |
902 | } | |
dc1c1ca3 | 903 | |
8dad3f92 | 904 | #ifdef CONFIG_8xx |
14cf11af PM |
905 | void SoftwareEmulation(struct pt_regs *regs) |
906 | { | |
907 | extern int do_mathemu(struct pt_regs *); | |
908 | extern int Soft_emulate_8xx(struct pt_regs *); | |
909 | int errcode; | |
910 | ||
911 | CHECK_FULL_REGS(regs); | |
912 | ||
913 | if (!user_mode(regs)) { | |
914 | debugger(regs); | |
915 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
916 | } | |
917 | ||
918 | #ifdef CONFIG_MATH_EMULATION | |
919 | errcode = do_mathemu(regs); | |
5fad293b KG |
920 | |
921 | switch (errcode) { | |
922 | case 0: | |
923 | emulate_single_step(regs); | |
924 | return; | |
925 | case 1: { | |
926 | int code = 0; | |
927 | code = __parse_fpscr(current->thread.fpscr.val); | |
928 | _exception(SIGFPE, regs, code, regs->nip); | |
929 | return; | |
930 | } | |
931 | case -EFAULT: | |
932 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
933 | return; | |
934 | default: | |
935 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
936 | return; | |
937 | } | |
938 | ||
14cf11af PM |
939 | #else |
940 | errcode = Soft_emulate_8xx(regs); | |
5fad293b KG |
941 | switch (errcode) { |
942 | case 0: | |
14cf11af | 943 | emulate_single_step(regs); |
5fad293b KG |
944 | return; |
945 | case 1: | |
946 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
947 | return; | |
948 | case -EFAULT: | |
949 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
950 | return; | |
951 | } | |
952 | #endif | |
14cf11af | 953 | } |
8dad3f92 | 954 | #endif /* CONFIG_8xx */ |
14cf11af PM |
955 | |
956 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
957 | ||
958 | void DebugException(struct pt_regs *regs, unsigned long debug_status) | |
959 | { | |
960 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
961 | regs->msr &= ~MSR_DE; | |
962 | if (user_mode(regs)) { | |
963 | current->thread.dbcr0 &= ~DBCR0_IC; | |
964 | } else { | |
965 | /* Disable instruction completion */ | |
966 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
967 | /* Clear the instruction completion event */ | |
968 | mtspr(SPRN_DBSR, DBSR_IC); | |
969 | if (debugger_sstep(regs)) | |
970 | return; | |
971 | } | |
972 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
973 | } | |
974 | } | |
975 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
976 | ||
977 | #if !defined(CONFIG_TAU_INT) | |
978 | void TAUException(struct pt_regs *regs) | |
979 | { | |
980 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
981 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
982 | } | |
983 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
984 | |
985 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 986 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
987 | { |
988 | int err; | |
989 | ||
14cf11af PM |
990 | if (!user_mode(regs)) { |
991 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
992 | " at %lx\n", regs->nip); | |
8dad3f92 | 993 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
994 | } |
995 | ||
dc1c1ca3 | 996 | flush_altivec_to_thread(current); |
dc1c1ca3 | 997 | |
14cf11af PM |
998 | err = emulate_altivec(regs); |
999 | if (err == 0) { | |
1000 | regs->nip += 4; /* skip emulated instruction */ | |
1001 | emulate_single_step(regs); | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | if (err == -EFAULT) { | |
1006 | /* got an error reading the instruction */ | |
1007 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1008 | } else { | |
1009 | /* didn't recognize the instruction */ | |
1010 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1011 | if (printk_ratelimit()) | |
1012 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1013 | "in %s at %lx\n", current->comm, regs->nip); | |
1014 | current->thread.vscr.u[3] |= 0x10000; | |
1015 | } | |
1016 | } | |
1017 | #endif /* CONFIG_ALTIVEC */ | |
1018 | ||
14cf11af PM |
1019 | #ifdef CONFIG_FSL_BOOKE |
1020 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1021 | unsigned long error_code) | |
1022 | { | |
1023 | /* We treat cache locking instructions from the user | |
1024 | * as priv ops, in the future we could try to do | |
1025 | * something smarter | |
1026 | */ | |
1027 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1028 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1029 | return; | |
1030 | } | |
1031 | #endif /* CONFIG_FSL_BOOKE */ | |
1032 | ||
1033 | #ifdef CONFIG_SPE | |
1034 | void SPEFloatingPointException(struct pt_regs *regs) | |
1035 | { | |
1036 | unsigned long spefscr; | |
1037 | int fpexc_mode; | |
1038 | int code = 0; | |
1039 | ||
1040 | spefscr = current->thread.spefscr; | |
1041 | fpexc_mode = current->thread.fpexc_mode; | |
1042 | ||
1043 | /* Hardware does not neccessarily set sticky | |
1044 | * underflow/overflow/invalid flags */ | |
1045 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { | |
1046 | code = FPE_FLTOVF; | |
1047 | spefscr |= SPEFSCR_FOVFS; | |
1048 | } | |
1049 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1050 | code = FPE_FLTUND; | |
1051 | spefscr |= SPEFSCR_FUNFS; | |
1052 | } | |
1053 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1054 | code = FPE_FLTDIV; | |
1055 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1056 | code = FPE_FLTINV; | |
1057 | spefscr |= SPEFSCR_FINVS; | |
1058 | } | |
1059 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1060 | code = FPE_FLTRES; | |
1061 | ||
1062 | current->thread.spefscr = spefscr; | |
1063 | ||
1064 | _exception(SIGFPE, regs, code, regs->nip); | |
1065 | return; | |
1066 | } | |
1067 | #endif | |
1068 | ||
dc1c1ca3 SR |
1069 | /* |
1070 | * We enter here if we get an unrecoverable exception, that is, one | |
1071 | * that happened at a point where the RI (recoverable interrupt) bit | |
1072 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1073 | * we therefore lost state by taking this exception. | |
1074 | */ | |
1075 | void unrecoverable_exception(struct pt_regs *regs) | |
1076 | { | |
1077 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1078 | regs->trap, regs->nip); | |
1079 | die("Unrecoverable exception", regs, SIGABRT); | |
1080 | } | |
dc1c1ca3 | 1081 | |
14cf11af PM |
1082 | #ifdef CONFIG_BOOKE_WDT |
1083 | /* | |
1084 | * Default handler for a Watchdog exception, | |
1085 | * spins until a reboot occurs | |
1086 | */ | |
1087 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1088 | { | |
1089 | /* Generic WatchdogHandler, implement your own */ | |
1090 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1091 | return; | |
1092 | } | |
1093 | ||
1094 | void WatchdogException(struct pt_regs *regs) | |
1095 | { | |
1096 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1097 | WatchdogHandler(regs); | |
1098 | } | |
1099 | #endif | |
dc1c1ca3 | 1100 | |
dc1c1ca3 SR |
1101 | /* |
1102 | * We enter here if we discover during exception entry that we are | |
1103 | * running in supervisor mode with a userspace value in the stack pointer. | |
1104 | */ | |
1105 | void kernel_bad_stack(struct pt_regs *regs) | |
1106 | { | |
1107 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1108 | regs->gpr[1], regs->nip); | |
1109 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1110 | } | |
14cf11af PM |
1111 | |
1112 | void __init trap_init(void) | |
1113 | { | |
1114 | } |