Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af PM |
24 | #include <linux/slab.h> |
25 | #include <linux/user.h> | |
14cf11af | 26 | #include <linux/interrupt.h> |
14cf11af PM |
27 | #include <linux/init.h> |
28 | #include <linux/module.h> | |
8dad3f92 | 29 | #include <linux/prctl.h> |
14cf11af PM |
30 | #include <linux/delay.h> |
31 | #include <linux/kprobes.h> | |
cc532915 | 32 | #include <linux/kexec.h> |
5474c120 | 33 | #include <linux/backlight.h> |
73c9ceab | 34 | #include <linux/bug.h> |
1eeb66a1 | 35 | #include <linux/kdebug.h> |
80947e7c | 36 | #include <linux/debugfs.h> |
14cf11af | 37 | |
80947e7c | 38 | #include <asm/emulated_ops.h> |
14cf11af PM |
39 | #include <asm/pgtable.h> |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/system.h> | |
42 | #include <asm/io.h> | |
86417780 PM |
43 | #include <asm/machdep.h> |
44 | #include <asm/rtas.h> | |
f7f6f4fe | 45 | #include <asm/pmc.h> |
dc1c1ca3 | 46 | #ifdef CONFIG_PPC32 |
14cf11af | 47 | #include <asm/reg.h> |
86417780 | 48 | #endif |
14cf11af PM |
49 | #ifdef CONFIG_PMAC_BACKLIGHT |
50 | #include <asm/backlight.h> | |
51 | #endif | |
dc1c1ca3 | 52 | #ifdef CONFIG_PPC64 |
86417780 | 53 | #include <asm/firmware.h> |
dc1c1ca3 | 54 | #include <asm/processor.h> |
dc1c1ca3 | 55 | #endif |
c0ce7d08 | 56 | #include <asm/kexec.h> |
16c57b36 | 57 | #include <asm/ppc-opcode.h> |
620165f9 KG |
58 | #ifdef CONFIG_FSL_BOOKE |
59 | #include <asm/dbell.h> | |
60 | #endif | |
dc1c1ca3 | 61 | |
7dbb922c | 62 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
14cf11af PM |
63 | int (*__debugger)(struct pt_regs *regs); |
64 | int (*__debugger_ipi)(struct pt_regs *regs); | |
65 | int (*__debugger_bpt)(struct pt_regs *regs); | |
66 | int (*__debugger_sstep)(struct pt_regs *regs); | |
67 | int (*__debugger_iabr_match)(struct pt_regs *regs); | |
68 | int (*__debugger_dabr_match)(struct pt_regs *regs); | |
69 | int (*__debugger_fault_handler)(struct pt_regs *regs); | |
70 | ||
71 | EXPORT_SYMBOL(__debugger); | |
72 | EXPORT_SYMBOL(__debugger_ipi); | |
73 | EXPORT_SYMBOL(__debugger_bpt); | |
74 | EXPORT_SYMBOL(__debugger_sstep); | |
75 | EXPORT_SYMBOL(__debugger_iabr_match); | |
76 | EXPORT_SYMBOL(__debugger_dabr_match); | |
77 | EXPORT_SYMBOL(__debugger_fault_handler); | |
78 | #endif | |
79 | ||
14cf11af PM |
80 | /* |
81 | * Trap & Exception support | |
82 | */ | |
83 | ||
6031d9d9 | 84 | #ifdef CONFIG_PMAC_BACKLIGHT |
85 | static void pmac_backlight_unblank(void) | |
86 | { | |
87 | mutex_lock(&pmac_backlight_mutex); | |
88 | if (pmac_backlight) { | |
89 | struct backlight_properties *props; | |
90 | ||
91 | props = &pmac_backlight->props; | |
92 | props->brightness = props->max_brightness; | |
93 | props->power = FB_BLANK_UNBLANK; | |
94 | backlight_update_status(pmac_backlight); | |
95 | } | |
96 | mutex_unlock(&pmac_backlight_mutex); | |
97 | } | |
98 | #else | |
99 | static inline void pmac_backlight_unblank(void) { } | |
100 | #endif | |
101 | ||
14cf11af PM |
102 | int die(const char *str, struct pt_regs *regs, long err) |
103 | { | |
34c2a14f | 104 | static struct { |
105 | spinlock_t lock; | |
106 | u32 lock_owner; | |
107 | int lock_owner_depth; | |
108 | } die = { | |
109 | .lock = __SPIN_LOCK_UNLOCKED(die.lock), | |
110 | .lock_owner = -1, | |
111 | .lock_owner_depth = 0 | |
112 | }; | |
c0ce7d08 | 113 | static int die_counter; |
34c2a14f | 114 | unsigned long flags; |
14cf11af PM |
115 | |
116 | if (debugger(regs)) | |
117 | return 1; | |
118 | ||
293e4688 | 119 | oops_enter(); |
120 | ||
34c2a14f | 121 | if (die.lock_owner != raw_smp_processor_id()) { |
122 | console_verbose(); | |
123 | spin_lock_irqsave(&die.lock, flags); | |
124 | die.lock_owner = smp_processor_id(); | |
125 | die.lock_owner_depth = 0; | |
126 | bust_spinlocks(1); | |
127 | if (machine_is(powermac)) | |
128 | pmac_backlight_unblank(); | |
129 | } else { | |
130 | local_save_flags(flags); | |
131 | } | |
5474c120 | 132 | |
34c2a14f | 133 | if (++die.lock_owner_depth < 3) { |
134 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 135 | #ifdef CONFIG_PREEMPT |
34c2a14f | 136 | printk("PREEMPT "); |
14cf11af PM |
137 | #endif |
138 | #ifdef CONFIG_SMP | |
34c2a14f | 139 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
140 | #endif |
141 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 142 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
143 | #endif |
144 | #ifdef CONFIG_NUMA | |
34c2a14f | 145 | printk("NUMA "); |
14cf11af | 146 | #endif |
ae7f4463 | 147 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 148 | |
149 | print_modules(); | |
150 | show_regs(regs); | |
151 | } else { | |
152 | printk("Recursive die() failure, output suppressed\n"); | |
153 | } | |
e8222502 | 154 | |
14cf11af | 155 | bust_spinlocks(0); |
34c2a14f | 156 | die.lock_owner = -1; |
bcdcd8e7 | 157 | add_taint(TAINT_DIE); |
34c2a14f | 158 | spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 159 | |
c0ce7d08 DW |
160 | if (kexec_should_crash(current) || |
161 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 162 | crash_kexec(regs); |
c0ce7d08 | 163 | crash_kexec_secondary(regs); |
14cf11af PM |
164 | |
165 | if (in_interrupt()) | |
166 | panic("Fatal exception in interrupt"); | |
167 | ||
cea6a4ba | 168 | if (panic_on_oops) |
012c437d | 169 | panic("Fatal exception"); |
cea6a4ba | 170 | |
293e4688 | 171 | oops_exit(); |
14cf11af PM |
172 | do_exit(err); |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
177 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) | |
178 | { | |
179 | siginfo_t info; | |
d0c3d534 OJ |
180 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
181 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
182 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
183 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
184 | |
185 | if (!user_mode(regs)) { | |
186 | if (die("Exception in kernel mode", regs, signr)) | |
187 | return; | |
d0c3d534 OJ |
188 | } else if (show_unhandled_signals && |
189 | unhandled_signal(current, signr) && | |
190 | printk_ratelimit()) { | |
191 | printk(regs->msr & MSR_SF ? fmt64 : fmt32, | |
192 | current->comm, current->pid, signr, | |
193 | addr, regs->nip, regs->link, code); | |
194 | } | |
14cf11af PM |
195 | |
196 | memset(&info, 0, sizeof(info)); | |
197 | info.si_signo = signr; | |
198 | info.si_code = code; | |
199 | info.si_addr = (void __user *) addr; | |
200 | force_sig_info(signr, &info, current); | |
201 | ||
202 | /* | |
203 | * Init gets no signals that it doesn't have a handler for. | |
204 | * That's all very well, but if it has caused a synchronous | |
205 | * exception and we ignore the resulting signal, it will just | |
206 | * generate the same exception over and over again and we get | |
207 | * nowhere. Better to kill it and let the kernel panic. | |
208 | */ | |
b460cbc5 | 209 | if (is_global_init(current)) { |
14cf11af PM |
210 | __sighandler_t handler; |
211 | ||
212 | spin_lock_irq(¤t->sighand->siglock); | |
213 | handler = current->sighand->action[signr-1].sa.sa_handler; | |
214 | spin_unlock_irq(¤t->sighand->siglock); | |
215 | if (handler == SIG_DFL) { | |
216 | /* init has generated a synchronous exception | |
217 | and it doesn't have a handler for the signal */ | |
218 | printk(KERN_CRIT "init has generated signal %d " | |
219 | "but has no handler for it\n", signr); | |
220 | do_exit(signr); | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
225 | #ifdef CONFIG_PPC64 | |
226 | void system_reset_exception(struct pt_regs *regs) | |
227 | { | |
228 | /* See if any machine dependent calls */ | |
c902be71 AB |
229 | if (ppc_md.system_reset_exception) { |
230 | if (ppc_md.system_reset_exception(regs)) | |
231 | return; | |
232 | } | |
14cf11af | 233 | |
c0ce7d08 DW |
234 | #ifdef CONFIG_KEXEC |
235 | cpu_set(smp_processor_id(), cpus_in_sr); | |
236 | #endif | |
237 | ||
8dad3f92 | 238 | die("System Reset", regs, SIGABRT); |
14cf11af | 239 | |
eac8392f DW |
240 | /* |
241 | * Some CPUs when released from the debugger will execute this path. | |
242 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
243 | * hung before entering the debugger it will return to the hung | |
244 | * state when exiting this function. This causes a problem in | |
245 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
246 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
247 | * here. If a kdump had not been initiated or we exit the debugger | |
248 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
249 | * will return after 5ms and the CPU returns to its previous state. | |
250 | */ | |
251 | crash_kexec_secondary(regs); | |
252 | ||
14cf11af PM |
253 | /* Must die if the interrupt is not recoverable */ |
254 | if (!(regs->msr & MSR_RI)) | |
255 | panic("Unrecoverable System Reset"); | |
256 | ||
257 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
258 | } | |
259 | #endif | |
260 | ||
261 | /* | |
262 | * I/O accesses can cause machine checks on powermacs. | |
263 | * Check if the NIP corresponds to the address of a sync | |
264 | * instruction for which there is an entry in the exception | |
265 | * table. | |
266 | * Note that the 601 only takes a machine check on TEA | |
267 | * (transfer error ack) signal assertion, and does not | |
268 | * set any of the top 16 bits of SRR1. | |
269 | * -- paulus. | |
270 | */ | |
271 | static inline int check_io_access(struct pt_regs *regs) | |
272 | { | |
68a64357 | 273 | #ifdef CONFIG_PPC32 |
14cf11af PM |
274 | unsigned long msr = regs->msr; |
275 | const struct exception_table_entry *entry; | |
276 | unsigned int *nip = (unsigned int *)regs->nip; | |
277 | ||
278 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
279 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
280 | /* | |
281 | * Check that it's a sync instruction, or somewhere | |
282 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
283 | * As the address is in the exception table | |
284 | * we should be able to read the instr there. | |
285 | * For the debug message, we look at the preceding | |
286 | * load or store. | |
287 | */ | |
288 | if (*nip == 0x60000000) /* nop */ | |
289 | nip -= 2; | |
290 | else if (*nip == 0x4c00012c) /* isync */ | |
291 | --nip; | |
292 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
293 | /* sync or twi */ | |
294 | unsigned int rb; | |
295 | ||
296 | --nip; | |
297 | rb = (*nip >> 11) & 0x1f; | |
298 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
299 | (*nip & 0x100)? "OUT to": "IN from", | |
300 | regs->gpr[rb] - _IO_BASE, nip); | |
301 | regs->msr |= MSR_RI; | |
302 | regs->nip = entry->fixup; | |
303 | return 1; | |
304 | } | |
305 | } | |
68a64357 | 306 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
307 | return 0; |
308 | } | |
309 | ||
310 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) | |
311 | /* On 4xx, the reason for the machine check or program exception | |
312 | is in the ESR. */ | |
313 | #define get_reason(regs) ((regs)->dsisr) | |
314 | #ifndef CONFIG_FSL_BOOKE | |
315 | #define get_mc_reason(regs) ((regs)->dsisr) | |
316 | #else | |
86d7a9a9 | 317 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) |
14cf11af PM |
318 | #endif |
319 | #define REASON_FP ESR_FP | |
320 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
321 | #define REASON_PRIVILEGED ESR_PPR | |
322 | #define REASON_TRAP ESR_PTR | |
323 | ||
324 | /* single-step stuff */ | |
325 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
326 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
327 | ||
328 | #else | |
329 | /* On non-4xx, the reason for the machine check or program | |
330 | exception is in the MSR. */ | |
331 | #define get_reason(regs) ((regs)->msr) | |
332 | #define get_mc_reason(regs) ((regs)->msr) | |
333 | #define REASON_FP 0x100000 | |
334 | #define REASON_ILLEGAL 0x80000 | |
335 | #define REASON_PRIVILEGED 0x40000 | |
336 | #define REASON_TRAP 0x20000 | |
337 | ||
338 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
339 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
340 | #endif | |
341 | ||
47c0bd1a BH |
342 | #if defined(CONFIG_4xx) |
343 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 344 | { |
1a6a4ffe | 345 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 346 | |
14cf11af PM |
347 | if (reason & ESR_IMCP) { |
348 | printk("Instruction"); | |
349 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
350 | } else | |
351 | printk("Data"); | |
352 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
353 | |
354 | return 0; | |
355 | } | |
356 | ||
357 | int machine_check_440A(struct pt_regs *regs) | |
358 | { | |
359 | unsigned long reason = get_mc_reason(regs); | |
360 | ||
14cf11af PM |
361 | printk("Machine check in kernel mode.\n"); |
362 | if (reason & ESR_IMCP){ | |
363 | printk("Instruction Synchronous Machine Check exception\n"); | |
364 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
365 | } | |
366 | else { | |
367 | u32 mcsr = mfspr(SPRN_MCSR); | |
368 | if (mcsr & MCSR_IB) | |
369 | printk("Instruction Read PLB Error\n"); | |
370 | if (mcsr & MCSR_DRB) | |
371 | printk("Data Read PLB Error\n"); | |
372 | if (mcsr & MCSR_DWB) | |
373 | printk("Data Write PLB Error\n"); | |
374 | if (mcsr & MCSR_TLBP) | |
375 | printk("TLB Parity Error\n"); | |
376 | if (mcsr & MCSR_ICP){ | |
377 | flush_instruction_cache(); | |
378 | printk("I-Cache Parity Error\n"); | |
379 | } | |
380 | if (mcsr & MCSR_DCSP) | |
381 | printk("D-Cache Search Parity Error\n"); | |
382 | if (mcsr & MCSR_DCFP) | |
383 | printk("D-Cache Flush Parity Error\n"); | |
384 | if (mcsr & MCSR_IMPE) | |
385 | printk("Machine Check exception is imprecise\n"); | |
386 | ||
387 | /* Clear MCSR */ | |
388 | mtspr(SPRN_MCSR, mcsr); | |
389 | } | |
47c0bd1a BH |
390 | return 0; |
391 | } | |
392 | #elif defined(CONFIG_E500) | |
393 | int machine_check_e500(struct pt_regs *regs) | |
394 | { | |
395 | unsigned long reason = get_mc_reason(regs); | |
396 | ||
14cf11af PM |
397 | printk("Machine check in kernel mode.\n"); |
398 | printk("Caused by (from MCSR=%lx): ", reason); | |
399 | ||
400 | if (reason & MCSR_MCP) | |
401 | printk("Machine Check Signal\n"); | |
402 | if (reason & MCSR_ICPERR) | |
403 | printk("Instruction Cache Parity Error\n"); | |
404 | if (reason & MCSR_DCP_PERR) | |
405 | printk("Data Cache Push Parity Error\n"); | |
406 | if (reason & MCSR_DCPERR) | |
407 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
408 | if (reason & MCSR_BUS_IAERR) |
409 | printk("Bus - Instruction Address Error\n"); | |
410 | if (reason & MCSR_BUS_RAERR) | |
411 | printk("Bus - Read Address Error\n"); | |
412 | if (reason & MCSR_BUS_WAERR) | |
413 | printk("Bus - Write Address Error\n"); | |
414 | if (reason & MCSR_BUS_IBERR) | |
415 | printk("Bus - Instruction Data Error\n"); | |
416 | if (reason & MCSR_BUS_RBERR) | |
417 | printk("Bus - Read Data Bus Error\n"); | |
418 | if (reason & MCSR_BUS_WBERR) | |
419 | printk("Bus - Read Data Bus Error\n"); | |
420 | if (reason & MCSR_BUS_IPERR) | |
421 | printk("Bus - Instruction Parity Error\n"); | |
422 | if (reason & MCSR_BUS_RPERR) | |
423 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
424 | |
425 | return 0; | |
426 | } | |
427 | #elif defined(CONFIG_E200) | |
428 | int machine_check_e200(struct pt_regs *regs) | |
429 | { | |
430 | unsigned long reason = get_mc_reason(regs); | |
431 | ||
14cf11af PM |
432 | printk("Machine check in kernel mode.\n"); |
433 | printk("Caused by (from MCSR=%lx): ", reason); | |
434 | ||
435 | if (reason & MCSR_MCP) | |
436 | printk("Machine Check Signal\n"); | |
437 | if (reason & MCSR_CP_PERR) | |
438 | printk("Cache Push Parity Error\n"); | |
439 | if (reason & MCSR_CPERR) | |
440 | printk("Cache Parity Error\n"); | |
441 | if (reason & MCSR_EXCP_ERR) | |
442 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
443 | if (reason & MCSR_BUS_IRERR) | |
444 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
445 | if (reason & MCSR_BUS_DRERR) | |
446 | printk("Bus - Read Bus Error on data load\n"); | |
447 | if (reason & MCSR_BUS_WRERR) | |
448 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
449 | |
450 | return 0; | |
451 | } | |
452 | #else | |
453 | int machine_check_generic(struct pt_regs *regs) | |
454 | { | |
455 | unsigned long reason = get_mc_reason(regs); | |
456 | ||
14cf11af PM |
457 | printk("Machine check in kernel mode.\n"); |
458 | printk("Caused by (from SRR1=%lx): ", reason); | |
459 | switch (reason & 0x601F0000) { | |
460 | case 0x80000: | |
461 | printk("Machine check signal\n"); | |
462 | break; | |
463 | case 0: /* for 601 */ | |
464 | case 0x40000: | |
465 | case 0x140000: /* 7450 MSS error and TEA */ | |
466 | printk("Transfer error ack signal\n"); | |
467 | break; | |
468 | case 0x20000: | |
469 | printk("Data parity error signal\n"); | |
470 | break; | |
471 | case 0x10000: | |
472 | printk("Address parity error signal\n"); | |
473 | break; | |
474 | case 0x20000000: | |
475 | printk("L1 Data Cache error\n"); | |
476 | break; | |
477 | case 0x40000000: | |
478 | printk("L1 Instruction Cache error\n"); | |
479 | break; | |
480 | case 0x00100000: | |
481 | printk("L2 data cache parity error\n"); | |
482 | break; | |
483 | default: | |
484 | printk("Unknown values in msr\n"); | |
485 | } | |
75918a4b OJ |
486 | return 0; |
487 | } | |
47c0bd1a | 488 | #endif /* everything else */ |
75918a4b OJ |
489 | |
490 | void machine_check_exception(struct pt_regs *regs) | |
491 | { | |
492 | int recover = 0; | |
493 | ||
47c0bd1a BH |
494 | /* See if any machine dependent calls. In theory, we would want |
495 | * to call the CPU first, and call the ppc_md. one if the CPU | |
496 | * one returns a positive number. However there is existing code | |
497 | * that assumes the board gets a first chance, so let's keep it | |
498 | * that way for now and fix things later. --BenH. | |
499 | */ | |
75918a4b OJ |
500 | if (ppc_md.machine_check_exception) |
501 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
502 | else if (cur_cpu_spec->machine_check) |
503 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 504 | |
47c0bd1a | 505 | if (recover > 0) |
75918a4b OJ |
506 | return; |
507 | ||
508 | if (user_mode(regs)) { | |
509 | regs->msr |= MSR_RI; | |
510 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
511 | return; | |
512 | } | |
513 | ||
514 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
47c0bd1a BH |
515 | /* the qspan pci read routines can cause machine checks -- Cort |
516 | * | |
517 | * yuck !!! that totally needs to go away ! There are better ways | |
518 | * to deal with that than having a wart in the mcheck handler. | |
519 | * -- BenH | |
520 | */ | |
75918a4b OJ |
521 | bad_page_fault(regs, regs->dar, SIGBUS); |
522 | return; | |
523 | #endif | |
524 | ||
525 | if (debugger_fault_handler(regs)) { | |
526 | regs->msr |= MSR_RI; | |
527 | return; | |
528 | } | |
529 | ||
530 | if (check_io_access(regs)) | |
531 | return; | |
532 | ||
14cf11af PM |
533 | if (debugger_fault_handler(regs)) |
534 | return; | |
8dad3f92 | 535 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
536 | |
537 | /* Must die if the interrupt is not recoverable */ | |
538 | if (!(regs->msr & MSR_RI)) | |
539 | panic("Unrecoverable Machine check"); | |
540 | } | |
541 | ||
542 | void SMIException(struct pt_regs *regs) | |
543 | { | |
544 | die("System Management Interrupt", regs, SIGABRT); | |
545 | } | |
546 | ||
dc1c1ca3 | 547 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
548 | { |
549 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
550 | regs->nip, regs->msr, regs->trap); | |
551 | ||
552 | _exception(SIGTRAP, regs, 0, 0); | |
553 | } | |
554 | ||
dc1c1ca3 | 555 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
556 | { |
557 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
558 | 5, SIGTRAP) == NOTIFY_STOP) | |
559 | return; | |
560 | if (debugger_iabr_match(regs)) | |
561 | return; | |
562 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
563 | } | |
564 | ||
565 | void RunModeException(struct pt_regs *regs) | |
566 | { | |
567 | _exception(SIGTRAP, regs, 0, 0); | |
568 | } | |
569 | ||
8dad3f92 | 570 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
571 | { |
572 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
573 | ||
574 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
575 | 5, SIGTRAP) == NOTIFY_STOP) | |
576 | return; | |
577 | if (debugger_sstep(regs)) | |
578 | return; | |
579 | ||
580 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
581 | } | |
582 | ||
583 | /* | |
584 | * After we have successfully emulated an instruction, we have to | |
585 | * check if the instruction was being single-stepped, and if so, | |
586 | * pretend we got a single-step exception. This was pointed out | |
587 | * by Kumar Gala. -- paulus | |
588 | */ | |
8dad3f92 | 589 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
590 | { |
591 | if (single_stepping(regs)) { | |
592 | clear_single_step(regs); | |
593 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
594 | } | |
595 | } | |
596 | ||
5fad293b | 597 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 598 | { |
5fad293b | 599 | int ret = 0; |
dc1c1ca3 SR |
600 | |
601 | /* Invalid operation */ | |
602 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 603 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
604 | |
605 | /* Overflow */ | |
606 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 607 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
608 | |
609 | /* Underflow */ | |
610 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 611 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
612 | |
613 | /* Divide by zero */ | |
614 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 615 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
616 | |
617 | /* Inexact result */ | |
618 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
619 | ret = FPE_FLTRES; |
620 | ||
621 | return ret; | |
622 | } | |
623 | ||
624 | static void parse_fpe(struct pt_regs *regs) | |
625 | { | |
626 | int code = 0; | |
627 | ||
628 | flush_fp_to_thread(current); | |
629 | ||
630 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
631 | |
632 | _exception(SIGFPE, regs, code, regs->nip); | |
633 | } | |
634 | ||
635 | /* | |
636 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
637 | * provide the PVR to user applications using the mfspr rd, PVR. |
638 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
639 | * memory access caused an access fault. Return zero on success. | |
640 | * | |
641 | * There are a couple of ways to do this, either "decode" the instruction | |
642 | * or directly match lots of bits. In this case, matching lots of | |
643 | * bits is faster and easier. | |
86417780 | 644 | * |
14cf11af | 645 | */ |
14cf11af PM |
646 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
647 | { | |
648 | u8 rT = (instword >> 21) & 0x1f; | |
649 | u8 rA = (instword >> 16) & 0x1f; | |
650 | u8 NB_RB = (instword >> 11) & 0x1f; | |
651 | u32 num_bytes; | |
652 | unsigned long EA; | |
653 | int pos = 0; | |
654 | ||
655 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 656 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
657 | if ((rT == rA) || (rT == NB_RB)) |
658 | return -EINVAL; | |
659 | ||
660 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
661 | ||
16c57b36 KG |
662 | switch (instword & PPC_INST_STRING_MASK) { |
663 | case PPC_INST_LSWX: | |
664 | case PPC_INST_STSWX: | |
14cf11af PM |
665 | EA += NB_RB; |
666 | num_bytes = regs->xer & 0x7f; | |
667 | break; | |
16c57b36 KG |
668 | case PPC_INST_LSWI: |
669 | case PPC_INST_STSWI: | |
14cf11af PM |
670 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
671 | break; | |
672 | default: | |
673 | return -EINVAL; | |
674 | } | |
675 | ||
676 | while (num_bytes != 0) | |
677 | { | |
678 | u8 val; | |
679 | u32 shift = 8 * (3 - (pos & 0x3)); | |
680 | ||
16c57b36 KG |
681 | switch ((instword & PPC_INST_STRING_MASK)) { |
682 | case PPC_INST_LSWX: | |
683 | case PPC_INST_LSWI: | |
14cf11af PM |
684 | if (get_user(val, (u8 __user *)EA)) |
685 | return -EFAULT; | |
686 | /* first time updating this reg, | |
687 | * zero it out */ | |
688 | if (pos == 0) | |
689 | regs->gpr[rT] = 0; | |
690 | regs->gpr[rT] |= val << shift; | |
691 | break; | |
16c57b36 KG |
692 | case PPC_INST_STSWI: |
693 | case PPC_INST_STSWX: | |
14cf11af PM |
694 | val = regs->gpr[rT] >> shift; |
695 | if (put_user(val, (u8 __user *)EA)) | |
696 | return -EFAULT; | |
697 | break; | |
698 | } | |
699 | /* move EA to next address */ | |
700 | EA += 1; | |
701 | num_bytes--; | |
702 | ||
703 | /* manage our position within the register */ | |
704 | if (++pos == 4) { | |
705 | pos = 0; | |
706 | if (++rT == 32) | |
707 | rT = 0; | |
708 | } | |
709 | } | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
c3412dcb WS |
714 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
715 | { | |
716 | u32 ra,rs; | |
717 | unsigned long tmp; | |
718 | ||
719 | ra = (instword >> 16) & 0x1f; | |
720 | rs = (instword >> 21) & 0x1f; | |
721 | ||
722 | tmp = regs->gpr[rs]; | |
723 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
724 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
725 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
726 | regs->gpr[ra] = tmp; | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
c1469f13 KG |
731 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
732 | { | |
733 | u8 rT = (instword >> 21) & 0x1f; | |
734 | u8 rA = (instword >> 16) & 0x1f; | |
735 | u8 rB = (instword >> 11) & 0x1f; | |
736 | u8 BC = (instword >> 6) & 0x1f; | |
737 | u8 bit; | |
738 | unsigned long tmp; | |
739 | ||
740 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
741 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
742 | ||
743 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
14cf11af PM |
748 | static int emulate_instruction(struct pt_regs *regs) |
749 | { | |
750 | u32 instword; | |
751 | u32 rd; | |
752 | ||
fab5db97 | 753 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
754 | return -EINVAL; |
755 | CHECK_FULL_REGS(regs); | |
756 | ||
757 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
758 | return -EFAULT; | |
759 | ||
760 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 761 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
80947e7c | 762 | PPC_WARN_EMULATED(mfpvr); |
14cf11af PM |
763 | rd = (instword >> 21) & 0x1f; |
764 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
765 | return 0; | |
766 | } | |
767 | ||
768 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c GU |
769 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
770 | PPC_WARN_EMULATED(dcba); | |
14cf11af | 771 | return 0; |
80947e7c | 772 | } |
14cf11af PM |
773 | |
774 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 775 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 776 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
777 | unsigned long msk = 0xf0000000UL >> shift; |
778 | ||
80947e7c | 779 | PPC_WARN_EMULATED(mcrxr); |
14cf11af PM |
780 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
781 | regs->xer &= ~0xf0000000UL; | |
782 | return 0; | |
783 | } | |
784 | ||
785 | /* Emulate load/store string insn. */ | |
80947e7c GU |
786 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
787 | PPC_WARN_EMULATED(string); | |
14cf11af | 788 | return emulate_string_inst(regs, instword); |
80947e7c | 789 | } |
14cf11af | 790 | |
c3412dcb | 791 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 792 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
80947e7c | 793 | PPC_WARN_EMULATED(popcntb); |
c3412dcb WS |
794 | return emulate_popcntb_inst(regs, instword); |
795 | } | |
796 | ||
c1469f13 | 797 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 798 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
80947e7c | 799 | PPC_WARN_EMULATED(isel); |
c1469f13 KG |
800 | return emulate_isel(regs, instword); |
801 | } | |
802 | ||
14cf11af PM |
803 | return -EINVAL; |
804 | } | |
805 | ||
73c9ceab | 806 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 807 | { |
73c9ceab | 808 | return is_kernel_addr(addr); |
14cf11af PM |
809 | } |
810 | ||
8dad3f92 | 811 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
812 | { |
813 | unsigned int reason = get_reason(regs); | |
814 | extern int do_mathemu(struct pt_regs *regs); | |
815 | ||
aa42c69c | 816 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 817 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 818 | |
dc1c1ca3 SR |
819 | if (reason & REASON_FP) { |
820 | /* IEEE FP exception */ | |
821 | parse_fpe(regs); | |
8dad3f92 PM |
822 | return; |
823 | } | |
824 | if (reason & REASON_TRAP) { | |
14cf11af | 825 | /* trap exception */ |
dc1c1ca3 SR |
826 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
827 | == NOTIFY_STOP) | |
828 | return; | |
14cf11af PM |
829 | if (debugger_bpt(regs)) |
830 | return; | |
73c9ceab JF |
831 | |
832 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 833 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
834 | regs->nip += 4; |
835 | return; | |
836 | } | |
8dad3f92 PM |
837 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
838 | return; | |
839 | } | |
840 | ||
cd8a5673 PM |
841 | local_irq_enable(); |
842 | ||
04903a30 KG |
843 | #ifdef CONFIG_MATH_EMULATION |
844 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
845 | * but there seems to be a hardware bug on the 405GP (RevD) | |
846 | * that means ESR is sometimes set incorrectly - either to | |
847 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
848 | * hardware people - not sure if it can happen on any illegal | |
849 | * instruction or only on FP instructions, whether there is a | |
850 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
851 | switch (do_mathemu(regs)) { |
852 | case 0: | |
04903a30 KG |
853 | emulate_single_step(regs); |
854 | return; | |
5fad293b KG |
855 | case 1: { |
856 | int code = 0; | |
857 | code = __parse_fpscr(current->thread.fpscr.val); | |
858 | _exception(SIGFPE, regs, code, regs->nip); | |
859 | return; | |
860 | } | |
861 | case -EFAULT: | |
862 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
863 | return; | |
04903a30 | 864 | } |
5fad293b | 865 | /* fall through on any other errors */ |
04903a30 KG |
866 | #endif /* CONFIG_MATH_EMULATION */ |
867 | ||
8dad3f92 PM |
868 | /* Try to emulate it if we should. */ |
869 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
870 | switch (emulate_instruction(regs)) { |
871 | case 0: | |
872 | regs->nip += 4; | |
873 | emulate_single_step(regs); | |
8dad3f92 | 874 | return; |
14cf11af PM |
875 | case -EFAULT: |
876 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 877 | return; |
14cf11af PM |
878 | } |
879 | } | |
8dad3f92 PM |
880 | |
881 | if (reason & REASON_PRIVILEGED) | |
882 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
883 | else | |
884 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
885 | } |
886 | ||
dc1c1ca3 | 887 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 888 | { |
4393c4f6 | 889 | int sig, code, fixed = 0; |
14cf11af | 890 | |
e9370ae1 PM |
891 | /* we don't implement logging of alignment exceptions */ |
892 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
893 | fixed = fix_alignment(regs); | |
14cf11af PM |
894 | |
895 | if (fixed == 1) { | |
896 | regs->nip += 4; /* skip over emulated instruction */ | |
897 | emulate_single_step(regs); | |
898 | return; | |
899 | } | |
900 | ||
dc1c1ca3 | 901 | /* Operand address was bad */ |
14cf11af | 902 | if (fixed == -EFAULT) { |
4393c4f6 BH |
903 | sig = SIGSEGV; |
904 | code = SEGV_ACCERR; | |
905 | } else { | |
906 | sig = SIGBUS; | |
907 | code = BUS_ADRALN; | |
14cf11af | 908 | } |
4393c4f6 BH |
909 | if (user_mode(regs)) |
910 | _exception(sig, regs, code, regs->dar); | |
911 | else | |
912 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
913 | } |
914 | ||
915 | void StackOverflow(struct pt_regs *regs) | |
916 | { | |
917 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
918 | current, regs->gpr[1]); | |
919 | debugger(regs); | |
920 | show_regs(regs); | |
921 | panic("kernel stack overflow"); | |
922 | } | |
923 | ||
924 | void nonrecoverable_exception(struct pt_regs *regs) | |
925 | { | |
926 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
927 | regs->nip, regs->msr); | |
928 | debugger(regs); | |
929 | die("nonrecoverable exception", regs, SIGKILL); | |
930 | } | |
931 | ||
932 | void trace_syscall(struct pt_regs *regs) | |
933 | { | |
934 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 935 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
936 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
937 | } | |
dc1c1ca3 | 938 | |
dc1c1ca3 SR |
939 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
940 | { | |
941 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
942 | "%lx at %lx\n", regs->trap, regs->nip); | |
943 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
944 | } | |
dc1c1ca3 SR |
945 | |
946 | void altivec_unavailable_exception(struct pt_regs *regs) | |
947 | { | |
dc1c1ca3 SR |
948 | if (user_mode(regs)) { |
949 | /* A user program has executed an altivec instruction, | |
950 | but this kernel doesn't support altivec. */ | |
951 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
952 | return; | |
953 | } | |
6c4841c2 | 954 | |
dc1c1ca3 SR |
955 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
956 | "%lx at %lx\n", regs->trap, regs->nip); | |
957 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
958 | } |
959 | ||
ce48b210 MN |
960 | void vsx_unavailable_exception(struct pt_regs *regs) |
961 | { | |
962 | if (user_mode(regs)) { | |
963 | /* A user program has executed an vsx instruction, | |
964 | but this kernel doesn't support vsx. */ | |
965 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
966 | return; | |
967 | } | |
968 | ||
969 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
970 | "%lx at %lx\n", regs->trap, regs->nip); | |
971 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
972 | } | |
973 | ||
dc1c1ca3 SR |
974 | void performance_monitor_exception(struct pt_regs *regs) |
975 | { | |
976 | perf_irq(regs); | |
977 | } | |
dc1c1ca3 | 978 | |
8dad3f92 | 979 | #ifdef CONFIG_8xx |
14cf11af PM |
980 | void SoftwareEmulation(struct pt_regs *regs) |
981 | { | |
982 | extern int do_mathemu(struct pt_regs *); | |
983 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 984 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 985 | int errcode; |
5dd57a13 | 986 | #endif |
14cf11af PM |
987 | |
988 | CHECK_FULL_REGS(regs); | |
989 | ||
990 | if (!user_mode(regs)) { | |
991 | debugger(regs); | |
992 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
993 | } | |
994 | ||
995 | #ifdef CONFIG_MATH_EMULATION | |
996 | errcode = do_mathemu(regs); | |
80947e7c GU |
997 | if (errcode >= 0) |
998 | PPC_WARN_EMULATED(math); | |
5fad293b KG |
999 | |
1000 | switch (errcode) { | |
1001 | case 0: | |
1002 | emulate_single_step(regs); | |
1003 | return; | |
1004 | case 1: { | |
1005 | int code = 0; | |
1006 | code = __parse_fpscr(current->thread.fpscr.val); | |
1007 | _exception(SIGFPE, regs, code, regs->nip); | |
1008 | return; | |
1009 | } | |
1010 | case -EFAULT: | |
1011 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1012 | return; | |
1013 | default: | |
1014 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1015 | return; | |
1016 | } | |
1017 | ||
5dd57a13 | 1018 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1019 | errcode = Soft_emulate_8xx(regs); |
80947e7c GU |
1020 | if (errcode >= 0) |
1021 | PPC_WARN_EMULATED(8xx); | |
1022 | ||
5fad293b KG |
1023 | switch (errcode) { |
1024 | case 0: | |
14cf11af | 1025 | emulate_single_step(regs); |
5fad293b KG |
1026 | return; |
1027 | case 1: | |
1028 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1029 | return; | |
1030 | case -EFAULT: | |
1031 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1032 | return; | |
1033 | } | |
5dd57a13 SW |
1034 | #else |
1035 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1036 | #endif |
14cf11af | 1037 | } |
8dad3f92 | 1038 | #endif /* CONFIG_8xx */ |
14cf11af PM |
1039 | |
1040 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
1041 | ||
f8279621 | 1042 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af PM |
1043 | { |
1044 | if (debug_status & DBSR_IC) { /* instruction completion */ | |
1045 | regs->msr &= ~MSR_DE; | |
f8279621 KG |
1046 | |
1047 | /* Disable instruction completion */ | |
1048 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1049 | /* Clear the instruction completion event */ | |
1050 | mtspr(SPRN_DBSR, DBSR_IC); | |
1051 | ||
1052 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1053 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1054 | return; | |
1055 | } | |
1056 | ||
1057 | if (debugger_sstep(regs)) | |
1058 | return; | |
1059 | ||
14cf11af PM |
1060 | if (user_mode(regs)) { |
1061 | current->thread.dbcr0 &= ~DBCR0_IC; | |
14cf11af | 1062 | } |
f8279621 KG |
1063 | |
1064 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
d6a61bfc LM |
1065 | } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { |
1066 | regs->msr &= ~MSR_DE; | |
1067 | ||
1068 | if (user_mode(regs)) { | |
1069 | current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | | |
1070 | DBCR0_IDM); | |
1071 | } else { | |
1072 | /* Disable DAC interupts */ | |
1073 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | | |
1074 | DBSR_DAC1W | DBCR0_IDM)); | |
1075 | ||
1076 | /* Clear the DAC event */ | |
1077 | mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W)); | |
1078 | } | |
1079 | /* Setup and send the trap to the handler */ | |
1080 | do_dabr(regs, mfspr(SPRN_DAC1), debug_status); | |
14cf11af PM |
1081 | } |
1082 | } | |
1083 | #endif /* CONFIG_4xx || CONFIG_BOOKE */ | |
1084 | ||
1085 | #if !defined(CONFIG_TAU_INT) | |
1086 | void TAUException(struct pt_regs *regs) | |
1087 | { | |
1088 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1089 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1090 | } | |
1091 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1092 | |
1093 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1094 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1095 | { |
1096 | int err; | |
1097 | ||
14cf11af PM |
1098 | if (!user_mode(regs)) { |
1099 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1100 | " at %lx\n", regs->nip); | |
8dad3f92 | 1101 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1102 | } |
1103 | ||
dc1c1ca3 | 1104 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1105 | |
80947e7c | 1106 | PPC_WARN_EMULATED(altivec); |
14cf11af PM |
1107 | err = emulate_altivec(regs); |
1108 | if (err == 0) { | |
1109 | regs->nip += 4; /* skip emulated instruction */ | |
1110 | emulate_single_step(regs); | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | if (err == -EFAULT) { | |
1115 | /* got an error reading the instruction */ | |
1116 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1117 | } else { | |
1118 | /* didn't recognize the instruction */ | |
1119 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1120 | if (printk_ratelimit()) | |
1121 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1122 | "in %s at %lx\n", current->comm, regs->nip); | |
1123 | current->thread.vscr.u[3] |= 0x10000; | |
1124 | } | |
1125 | } | |
1126 | #endif /* CONFIG_ALTIVEC */ | |
1127 | ||
ce48b210 MN |
1128 | #ifdef CONFIG_VSX |
1129 | void vsx_assist_exception(struct pt_regs *regs) | |
1130 | { | |
1131 | if (!user_mode(regs)) { | |
1132 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1133 | " at %lx\n", regs->nip); | |
1134 | die("Kernel VSX assist exception", regs, SIGILL); | |
1135 | } | |
1136 | ||
1137 | flush_vsx_to_thread(current); | |
1138 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1139 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1140 | } | |
1141 | #endif /* CONFIG_VSX */ | |
1142 | ||
14cf11af | 1143 | #ifdef CONFIG_FSL_BOOKE |
620165f9 KG |
1144 | |
1145 | void doorbell_exception(struct pt_regs *regs) | |
1146 | { | |
1147 | #ifdef CONFIG_SMP | |
1148 | int cpu = smp_processor_id(); | |
1149 | int msg; | |
1150 | ||
1151 | if (num_online_cpus() < 2) | |
1152 | return; | |
1153 | ||
1154 | for (msg = 0; msg < 4; msg++) | |
1155 | if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) | |
1156 | smp_message_recv(msg); | |
1157 | #else | |
1158 | printk(KERN_WARNING "Received doorbell on non-smp system\n"); | |
1159 | #endif | |
1160 | } | |
1161 | ||
14cf11af PM |
1162 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
1163 | unsigned long error_code) | |
1164 | { | |
1165 | /* We treat cache locking instructions from the user | |
1166 | * as priv ops, in the future we could try to do | |
1167 | * something smarter | |
1168 | */ | |
1169 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1170 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1171 | return; | |
1172 | } | |
1173 | #endif /* CONFIG_FSL_BOOKE */ | |
1174 | ||
1175 | #ifdef CONFIG_SPE | |
1176 | void SPEFloatingPointException(struct pt_regs *regs) | |
1177 | { | |
6a800f36 | 1178 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1179 | unsigned long spefscr; |
1180 | int fpexc_mode; | |
1181 | int code = 0; | |
6a800f36 LY |
1182 | int err; |
1183 | ||
1184 | preempt_disable(); | |
1185 | if (regs->msr & MSR_SPE) | |
1186 | giveup_spe(current); | |
1187 | preempt_enable(); | |
14cf11af PM |
1188 | |
1189 | spefscr = current->thread.spefscr; | |
1190 | fpexc_mode = current->thread.fpexc_mode; | |
1191 | ||
14cf11af PM |
1192 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1193 | code = FPE_FLTOVF; | |
14cf11af PM |
1194 | } |
1195 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1196 | code = FPE_FLTUND; | |
14cf11af PM |
1197 | } |
1198 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1199 | code = FPE_FLTDIV; | |
1200 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1201 | code = FPE_FLTINV; | |
14cf11af PM |
1202 | } |
1203 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1204 | code = FPE_FLTRES; | |
1205 | ||
6a800f36 LY |
1206 | err = do_spe_mathemu(regs); |
1207 | if (err == 0) { | |
1208 | regs->nip += 4; /* skip emulated instruction */ | |
1209 | emulate_single_step(regs); | |
1210 | return; | |
1211 | } | |
1212 | ||
1213 | if (err == -EFAULT) { | |
1214 | /* got an error reading the instruction */ | |
1215 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1216 | } else if (err == -EINVAL) { | |
1217 | /* didn't recognize the instruction */ | |
1218 | printk(KERN_ERR "unrecognized spe instruction " | |
1219 | "in %s at %lx\n", current->comm, regs->nip); | |
1220 | } else { | |
1221 | _exception(SIGFPE, regs, code, regs->nip); | |
1222 | } | |
14cf11af | 1223 | |
14cf11af PM |
1224 | return; |
1225 | } | |
6a800f36 LY |
1226 | |
1227 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1228 | { | |
1229 | extern int speround_handler(struct pt_regs *regs); | |
1230 | int err; | |
1231 | ||
1232 | preempt_disable(); | |
1233 | if (regs->msr & MSR_SPE) | |
1234 | giveup_spe(current); | |
1235 | preempt_enable(); | |
1236 | ||
1237 | regs->nip -= 4; | |
1238 | err = speround_handler(regs); | |
1239 | if (err == 0) { | |
1240 | regs->nip += 4; /* skip emulated instruction */ | |
1241 | emulate_single_step(regs); | |
1242 | return; | |
1243 | } | |
1244 | ||
1245 | if (err == -EFAULT) { | |
1246 | /* got an error reading the instruction */ | |
1247 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1248 | } else if (err == -EINVAL) { | |
1249 | /* didn't recognize the instruction */ | |
1250 | printk(KERN_ERR "unrecognized spe instruction " | |
1251 | "in %s at %lx\n", current->comm, regs->nip); | |
1252 | } else { | |
1253 | _exception(SIGFPE, regs, 0, regs->nip); | |
1254 | return; | |
1255 | } | |
1256 | } | |
14cf11af PM |
1257 | #endif |
1258 | ||
dc1c1ca3 SR |
1259 | /* |
1260 | * We enter here if we get an unrecoverable exception, that is, one | |
1261 | * that happened at a point where the RI (recoverable interrupt) bit | |
1262 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1263 | * we therefore lost state by taking this exception. | |
1264 | */ | |
1265 | void unrecoverable_exception(struct pt_regs *regs) | |
1266 | { | |
1267 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1268 | regs->trap, regs->nip); | |
1269 | die("Unrecoverable exception", regs, SIGABRT); | |
1270 | } | |
dc1c1ca3 | 1271 | |
14cf11af PM |
1272 | #ifdef CONFIG_BOOKE_WDT |
1273 | /* | |
1274 | * Default handler for a Watchdog exception, | |
1275 | * spins until a reboot occurs | |
1276 | */ | |
1277 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1278 | { | |
1279 | /* Generic WatchdogHandler, implement your own */ | |
1280 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1281 | return; | |
1282 | } | |
1283 | ||
1284 | void WatchdogException(struct pt_regs *regs) | |
1285 | { | |
1286 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1287 | WatchdogHandler(regs); | |
1288 | } | |
1289 | #endif | |
dc1c1ca3 | 1290 | |
dc1c1ca3 SR |
1291 | /* |
1292 | * We enter here if we discover during exception entry that we are | |
1293 | * running in supervisor mode with a userspace value in the stack pointer. | |
1294 | */ | |
1295 | void kernel_bad_stack(struct pt_regs *regs) | |
1296 | { | |
1297 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1298 | regs->gpr[1], regs->nip); | |
1299 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1300 | } | |
14cf11af PM |
1301 | |
1302 | void __init trap_init(void) | |
1303 | { | |
1304 | } | |
80947e7c GU |
1305 | |
1306 | ||
1307 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1308 | ||
1309 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1310 | ||
1311 | struct ppc_emulated ppc_emulated = { | |
1312 | #ifdef CONFIG_ALTIVEC | |
1313 | WARN_EMULATED_SETUP(altivec), | |
1314 | #endif | |
1315 | WARN_EMULATED_SETUP(dcba), | |
1316 | WARN_EMULATED_SETUP(dcbz), | |
1317 | WARN_EMULATED_SETUP(fp_pair), | |
1318 | WARN_EMULATED_SETUP(isel), | |
1319 | WARN_EMULATED_SETUP(mcrxr), | |
1320 | WARN_EMULATED_SETUP(mfpvr), | |
1321 | WARN_EMULATED_SETUP(multiple), | |
1322 | WARN_EMULATED_SETUP(popcntb), | |
1323 | WARN_EMULATED_SETUP(spe), | |
1324 | WARN_EMULATED_SETUP(string), | |
1325 | WARN_EMULATED_SETUP(unaligned), | |
1326 | #ifdef CONFIG_MATH_EMULATION | |
1327 | WARN_EMULATED_SETUP(math), | |
1328 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1329 | WARN_EMULATED_SETUP(8xx), | |
1330 | #endif | |
1331 | #ifdef CONFIG_VSX | |
1332 | WARN_EMULATED_SETUP(vsx), | |
1333 | #endif | |
1334 | }; | |
1335 | ||
1336 | u32 ppc_warn_emulated; | |
1337 | ||
1338 | void ppc_warn_emulated_print(const char *type) | |
1339 | { | |
1340 | if (printk_ratelimit()) | |
1341 | pr_warning("%s used emulated %s instruction\n", current->comm, | |
1342 | type); | |
1343 | } | |
1344 | ||
1345 | static int __init ppc_warn_emulated_init(void) | |
1346 | { | |
1347 | struct dentry *dir, *d; | |
1348 | unsigned int i; | |
1349 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1350 | ||
1351 | if (!powerpc_debugfs_root) | |
1352 | return -ENODEV; | |
1353 | ||
1354 | dir = debugfs_create_dir("emulated_instructions", | |
1355 | powerpc_debugfs_root); | |
1356 | if (!dir) | |
1357 | return -ENOMEM; | |
1358 | ||
1359 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1360 | &ppc_warn_emulated); | |
1361 | if (!d) | |
1362 | goto fail; | |
1363 | ||
1364 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1365 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1366 | (u32 *)&entries[i].val.counter); | |
1367 | if (!d) | |
1368 | goto fail; | |
1369 | } | |
1370 | ||
1371 | return 0; | |
1372 | ||
1373 | fail: | |
1374 | debugfs_remove_recursive(dir); | |
1375 | return -ENOMEM; | |
1376 | } | |
1377 | ||
1378 | device_initcall(ppc_warn_emulated_init); | |
1379 | ||
1380 | #endif /* CONFIG_PPC_EMULATED_STATS */ |