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Merge branch 'booke-hugetlb' into next
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
CommitLineData
14cf11af 1/*
14cf11af 2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
fe04b112 3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
14cf11af
PM		 4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14/*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
14cf11af
PM		 18#include <linux/errno.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/stddef.h>
23#include <linux/unistd.h>
8dad3f92 24#include <linux/ptrace.h>
14cf11af 25#include <linux/user.h>
14cf11af 26#include <linux/interrupt.h>
14cf11af
PM		 27#include <linux/init.h>
28#include <linux/module.h>
8dad3f92 29#include <linux/prctl.h>
14cf11af
PM		 30#include <linux/delay.h>
31#include <linux/kprobes.h>
cc532915 32#include <linux/kexec.h>
5474c120 33#include <linux/backlight.h>
73c9ceab 34#include <linux/bug.h>
1eeb66a1 35#include <linux/kdebug.h>
80947e7c 36#include <linux/debugfs.h>
76462232 37#include <linux/ratelimit.h>
14cf11af 38
80947e7c 39#include <asm/emulated_ops.h>
14cf11af
PM		 40#include <asm/pgtable.h>
41#include <asm/uaccess.h>
42#include <asm/system.h>
43#include <asm/io.h>
86417780
PM		 44#include <asm/machdep.h>
45#include <asm/rtas.h>
f7f6f4fe 46#include <asm/pmc.h>
dc1c1ca3 47#ifdef CONFIG_PPC32
14cf11af 48#include <asm/reg.h>
86417780 49#endif
14cf11af
PM		 50#ifdef CONFIG_PMAC_BACKLIGHT
51#include <asm/backlight.h>
52#endif
dc1c1ca3 53#ifdef CONFIG_PPC64
86417780 54#include <asm/firmware.h>
dc1c1ca3 55#include <asm/processor.h>
dc1c1ca3 56#endif
c0ce7d08 57#include <asm/kexec.h>
16c57b36 58#include <asm/ppc-opcode.h>
cce1f106 59#include <asm/rio.h>
dc1c1ca3 60
7dbb922c 61#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
5be3492f
AB		 62int (*__debugger)(struct pt_regs *regs) __read_mostly;
63int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
64int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
65int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
66int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
67int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
68int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
14cf11af
PM		 69
70EXPORT_SYMBOL(__debugger);
71EXPORT_SYMBOL(__debugger_ipi);
72EXPORT_SYMBOL(__debugger_bpt);
73EXPORT_SYMBOL(__debugger_sstep);
74EXPORT_SYMBOL(__debugger_iabr_match);
75EXPORT_SYMBOL(__debugger_dabr_match);
76EXPORT_SYMBOL(__debugger_fault_handler);
77#endif
78
14cf11af
PM		 79/*
80 * Trap & Exception support
81 */
82
6031d9d9 83#ifdef CONFIG_PMAC_BACKLIGHT
84static void pmac_backlight_unblank(void)
85{
86 mutex_lock(&pmac_backlight_mutex);
87 if (pmac_backlight) {
88 struct backlight_properties *props;
89
90 props = &pmac_backlight->props;
91 props->brightness = props->max_brightness;
92 props->power = FB_BLANK_UNBLANK;
93 backlight_update_status(pmac_backlight);
94 }
95 mutex_unlock(&pmac_backlight_mutex);
96}
97#else
98static inline void pmac_backlight_unblank(void) { }
99#endif
100
14cf11af
PM		 101int die(const char *str, struct pt_regs *regs, long err)
102{
34c2a14f 103 static struct {
b8f87782 104 raw_spinlock_t lock;
34c2a14f 105 u32 lock_owner;
106 int lock_owner_depth;
107 } die = {
b8f87782 108 .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock),
34c2a14f 109 .lock_owner = -1,
110 .lock_owner_depth = 0
111 };
c0ce7d08 112 static int die_counter;
34c2a14f 113 unsigned long flags;
14cf11af
PM		 114
115 if (debugger(regs))
116 return 1;
117
293e4688 118 oops_enter();
119
34c2a14f 120 if (die.lock_owner != raw_smp_processor_id()) {
121 console_verbose();
b8f87782 122 raw_spin_lock_irqsave(&die.lock, flags);
34c2a14f 123 die.lock_owner = smp_processor_id();
124 die.lock_owner_depth = 0;
125 bust_spinlocks(1);
126 if (machine_is(powermac))
127 pmac_backlight_unblank();
128 } else {
129 local_save_flags(flags);
130 }
5474c120 131
34c2a14f 132 if (++die.lock_owner_depth < 3) {
133 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
14cf11af 134#ifdef CONFIG_PREEMPT
34c2a14f 135 printk("PREEMPT ");
14cf11af
PM		 136#endif
137#ifdef CONFIG_SMP
34c2a14f 138 printk("SMP NR_CPUS=%d ", NR_CPUS);
14cf11af
PM		 139#endif
140#ifdef CONFIG_DEBUG_PAGEALLOC
34c2a14f 141 printk("DEBUG_PAGEALLOC ");
14cf11af
PM		 142#endif
143#ifdef CONFIG_NUMA
34c2a14f 144 printk("NUMA ");
14cf11af 145#endif
ae7f4463 146 printk("%s\n", ppc_md.name ? ppc_md.name : "");
34c2a14f 147
66fcb105
AB		 148 if (notify_die(DIE_OOPS, str, regs, err, 255,
149 SIGSEGV) == NOTIFY_STOP)
150 return 1;
151
34c2a14f 152 print_modules();
153 show_regs(regs);
154 } else {
155 printk("Recursive die() failure, output suppressed\n");
156 }
e8222502 157
14cf11af 158 bust_spinlocks(0);
34c2a14f 159 die.lock_owner = -1;
bcdcd8e7 160 add_taint(TAINT_DIE);
b8f87782 161 raw_spin_unlock_irqrestore(&die.lock, flags);
cc532915 162
c0ce7d08
DW		 163 if (kexec_should_crash(current) ||
164 kexec_sr_activated(smp_processor_id()))
cc532915 165 crash_kexec(regs);
c0ce7d08 166 crash_kexec_secondary(regs);
14cf11af
PM		 167
168 if (in_interrupt())
169 panic("Fatal exception in interrupt");
170
cea6a4ba 171 if (panic_on_oops)
012c437d 172 panic("Fatal exception");
cea6a4ba 173
293e4688 174 oops_exit();
14cf11af
PM		 175 do_exit(err);
176
177 return 0;
178}
179
25baa35b
ON		 180void user_single_step_siginfo(struct task_struct *tsk,
181 struct pt_regs *regs, siginfo_t *info)
182{
183 memset(info, 0, sizeof(*info));
184 info->si_signo = SIGTRAP;
185 info->si_code = TRAP_TRACE;
186 info->si_addr = (void __user *)regs->nip;
187}
188
14cf11af
PM		 189void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
190{
191 siginfo_t info;
d0c3d534
OJ		 192 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
193 "at %08lx nip %08lx lr %08lx code %x\n";
194 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
195 "at %016lx nip %016lx lr %016lx code %x\n";
14cf11af
PM		 196
197 if (!user_mode(regs)) {
198 if (die("Exception in kernel mode", regs, signr))
199 return;
d0c3d534 200 } else if (show_unhandled_signals &&
76462232
CD		 201 unhandled_signal(current, signr)) {
202 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
203 current->comm, current->pid, signr,
204 addr, regs->nip, regs->link, code);
205 }
14cf11af
PM		 206
207 memset(&info, 0, sizeof(info));
208 info.si_signo = signr;
209 info.si_code = code;
210 info.si_addr = (void __user *) addr;
211 force_sig_info(signr, &info, current);
14cf11af
PM		 212}
213
214#ifdef CONFIG_PPC64
215void system_reset_exception(struct pt_regs *regs)
216{
217 /* See if any machine dependent calls */
c902be71
AB		 218 if (ppc_md.system_reset_exception) {
219 if (ppc_md.system_reset_exception(regs))
220 return;
221 }
14cf11af 222
c0ce7d08 223#ifdef CONFIG_KEXEC
104699c0 224 cpumask_set_cpu(smp_processor_id(), &cpus_in_sr);
c0ce7d08
DW		 225#endif
226
8dad3f92 227 die("System Reset", regs, SIGABRT);
14cf11af 228
eac8392f
DW		 229 /*
230 * Some CPUs when released from the debugger will execute this path.
231 * These CPUs entered the debugger via a soft-reset. If the CPU was
232 * hung before entering the debugger it will return to the hung
233 * state when exiting this function. This causes a problem in
234 * kdump since the hung CPU(s) will not respond to the IPI sent
235 * from kdump. To prevent the problem we call crash_kexec_secondary()
236 * here. If a kdump had not been initiated or we exit the debugger
237 * with the "exit and recover" command (x) crash_kexec_secondary()
238 * will return after 5ms and the CPU returns to its previous state.
239 */
240 crash_kexec_secondary(regs);
241
14cf11af
PM		 242 /* Must die if the interrupt is not recoverable */
243 if (!(regs->msr & MSR_RI))
244 panic("Unrecoverable System Reset");
245
246 /* What should we do here? We could issue a shutdown or hard reset. */
247}
248#endif
249
250/*
251 * I/O accesses can cause machine checks on powermacs.
252 * Check if the NIP corresponds to the address of a sync
253 * instruction for which there is an entry in the exception
254 * table.
255 * Note that the 601 only takes a machine check on TEA
256 * (transfer error ack) signal assertion, and does not
257 * set any of the top 16 bits of SRR1.
258 * -- paulus.
259 */
260static inline int check_io_access(struct pt_regs *regs)
261{
68a64357 262#ifdef CONFIG_PPC32
14cf11af
PM		 263 unsigned long msr = regs->msr;
264 const struct exception_table_entry *entry;
265 unsigned int *nip = (unsigned int *)regs->nip;
266
267 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
268 && (entry = search_exception_tables(regs->nip)) != NULL) {
269 /*
270 * Check that it's a sync instruction, or somewhere
271 * in the twi; isync; nop sequence that inb/inw/inl uses.
272 * As the address is in the exception table
273 * we should be able to read the instr there.
274 * For the debug message, we look at the preceding
275 * load or store.
276 */
277 if (*nip == 0x60000000) /* nop */
278 nip -= 2;
279 else if (*nip == 0x4c00012c) /* isync */
280 --nip;
281 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
282 /* sync or twi */
283 unsigned int rb;
284
285 --nip;
286 rb = (*nip >> 11) & 0x1f;
287 printk(KERN_DEBUG "%s bad port %lx at %p\n",
288 (*nip & 0x100)? "OUT to": "IN from",
289 regs->gpr[rb] - _IO_BASE, nip);
290 regs->msr |= MSR_RI;
291 regs->nip = entry->fixup;
292 return 1;
293 }
294 }
68a64357 295#endif /* CONFIG_PPC32 */
14cf11af
PM		 296 return 0;
297}
298
172ae2e7 299#ifdef CONFIG_PPC_ADV_DEBUG_REGS
14cf11af
PM		 300/* On 4xx, the reason for the machine check or program exception
301 is in the ESR. */
302#define get_reason(regs) ((regs)->dsisr)
303#ifndef CONFIG_FSL_BOOKE
304#define get_mc_reason(regs) ((regs)->dsisr)
305#else
fe04b112 306#define get_mc_reason(regs) (mfspr(SPRN_MCSR))
14cf11af
PM		 307#endif
308#define REASON_FP ESR_FP
309#define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
310#define REASON_PRIVILEGED ESR_PPR
311#define REASON_TRAP ESR_PTR
312
313/* single-step stuff */
314#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
315#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
316
317#else
318/* On non-4xx, the reason for the machine check or program
319 exception is in the MSR. */
320#define get_reason(regs) ((regs)->msr)
321#define get_mc_reason(regs) ((regs)->msr)
322#define REASON_FP 0x100000
323#define REASON_ILLEGAL 0x80000
324#define REASON_PRIVILEGED 0x40000
325#define REASON_TRAP 0x20000
326
327#define single_stepping(regs) ((regs)->msr & MSR_SE)
328#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
329#endif
330
47c0bd1a
BH		 331#if defined(CONFIG_4xx)
332int machine_check_4xx(struct pt_regs *regs)
14cf11af 333{
1a6a4ffe 334 unsigned long reason = get_mc_reason(regs);
14cf11af 335
14cf11af
PM		 336 if (reason & ESR_IMCP) {
337 printk("Instruction");
338 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
339 } else
340 printk("Data");
341 printk(" machine check in kernel mode.\n");
47c0bd1a
BH		 342
343 return 0;
344}
345
346int machine_check_440A(struct pt_regs *regs)
347{
348 unsigned long reason = get_mc_reason(regs);
349
14cf11af
PM		 350 printk("Machine check in kernel mode.\n");
351 if (reason & ESR_IMCP){
352 printk("Instruction Synchronous Machine Check exception\n");
353 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
354 }
355 else {
356 u32 mcsr = mfspr(SPRN_MCSR);
357 if (mcsr & MCSR_IB)
358 printk("Instruction Read PLB Error\n");
359 if (mcsr & MCSR_DRB)
360 printk("Data Read PLB Error\n");
361 if (mcsr & MCSR_DWB)
362 printk("Data Write PLB Error\n");
363 if (mcsr & MCSR_TLBP)
364 printk("TLB Parity Error\n");
365 if (mcsr & MCSR_ICP){
366 flush_instruction_cache();
367 printk("I-Cache Parity Error\n");
368 }
369 if (mcsr & MCSR_DCSP)
370 printk("D-Cache Search Parity Error\n");
371 if (mcsr & MCSR_DCFP)
372 printk("D-Cache Flush Parity Error\n");
373 if (mcsr & MCSR_IMPE)
374 printk("Machine Check exception is imprecise\n");
375
376 /* Clear MCSR */
377 mtspr(SPRN_MCSR, mcsr);
378 }
47c0bd1a
BH		 379 return 0;
380}
fc5e7097
DK		 381
382int machine_check_47x(struct pt_regs *regs)
383{
384 unsigned long reason = get_mc_reason(regs);
385 u32 mcsr;
386
387 printk(KERN_ERR "Machine check in kernel mode.\n");
388 if (reason & ESR_IMCP) {
389 printk(KERN_ERR
390 "Instruction Synchronous Machine Check exception\n");
391 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
392 return 0;
393 }
394 mcsr = mfspr(SPRN_MCSR);
395 if (mcsr & MCSR_IB)
396 printk(KERN_ERR "Instruction Read PLB Error\n");
397 if (mcsr & MCSR_DRB)
398 printk(KERN_ERR "Data Read PLB Error\n");
399 if (mcsr & MCSR_DWB)
400 printk(KERN_ERR "Data Write PLB Error\n");
401 if (mcsr & MCSR_TLBP)
402 printk(KERN_ERR "TLB Parity Error\n");
403 if (mcsr & MCSR_ICP) {
404 flush_instruction_cache();
405 printk(KERN_ERR "I-Cache Parity Error\n");
406 }
407 if (mcsr & MCSR_DCSP)
408 printk(KERN_ERR "D-Cache Search Parity Error\n");
409 if (mcsr & PPC47x_MCSR_GPR)
410 printk(KERN_ERR "GPR Parity Error\n");
411 if (mcsr & PPC47x_MCSR_FPR)
412 printk(KERN_ERR "FPR Parity Error\n");
413 if (mcsr & PPC47x_MCSR_IPR)
414 printk(KERN_ERR "Machine Check exception is imprecise\n");
415
416 /* Clear MCSR */
417 mtspr(SPRN_MCSR, mcsr);
418
419 return 0;
420}
47c0bd1a 421#elif defined(CONFIG_E500)
fe04b112
SW		 422int machine_check_e500mc(struct pt_regs *regs)
423{
424 unsigned long mcsr = mfspr(SPRN_MCSR);
425 unsigned long reason = mcsr;
426 int recoverable = 1;
427
82a9a480 428 if (reason & MCSR_LD) {
cce1f106
SX		 429 recoverable = fsl_rio_mcheck_exception(regs);
430 if (recoverable == 1)
431 goto silent_out;
432 }
433
fe04b112
SW		 434 printk("Machine check in kernel mode.\n");
435 printk("Caused by (from MCSR=%lx): ", reason);
436
437 if (reason & MCSR_MCP)
438 printk("Machine Check Signal\n");
439
440 if (reason & MCSR_ICPERR) {
441 printk("Instruction Cache Parity Error\n");
442
443 /*
444 * This is recoverable by invalidating the i-cache.
445 */
446 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
447 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
448 ;
449
450 /*
451 * This will generally be accompanied by an instruction
452 * fetch error report -- only treat MCSR_IF as fatal
453 * if it wasn't due to an L1 parity error.
454 */
455 reason &= ~MCSR_IF;
456 }
457
458 if (reason & MCSR_DCPERR_MC) {
459 printk("Data Cache Parity Error\n");
37caf9f2
KG		 460
461 /*
462 * In write shadow mode we auto-recover from the error, but it
463 * may still get logged and cause a machine check. We should
464 * only treat the non-write shadow case as non-recoverable.
465 */
466 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
467 recoverable = 0;
fe04b112
SW		 468 }
469
470 if (reason & MCSR_L2MMU_MHIT) {
471 printk("Hit on multiple TLB entries\n");
472 recoverable = 0;
473 }
474
475 if (reason & MCSR_NMI)
476 printk("Non-maskable interrupt\n");
477
478 if (reason & MCSR_IF) {
479 printk("Instruction Fetch Error Report\n");
480 recoverable = 0;
481 }
482
483 if (reason & MCSR_LD) {
484 printk("Load Error Report\n");
485 recoverable = 0;
486 }
487
488 if (reason & MCSR_ST) {
489 printk("Store Error Report\n");
490 recoverable = 0;
491 }
492
493 if (reason & MCSR_LDG) {
494 printk("Guarded Load Error Report\n");
495 recoverable = 0;
496 }
497
498 if (reason & MCSR_TLBSYNC)
499 printk("Simultaneous tlbsync operations\n");
500
501 if (reason & MCSR_BSL2_ERR) {
502 printk("Level 2 Cache Error\n");
503 recoverable = 0;
504 }
505
506 if (reason & MCSR_MAV) {
507 u64 addr;
508
509 addr = mfspr(SPRN_MCAR);
510 addr |= (u64)mfspr(SPRN_MCARU) << 32;
511
512 printk("Machine Check %s Address: %#llx\n",
513 reason & MCSR_MEA ? "Effective" : "Physical", addr);
514 }
515
cce1f106 516silent_out:
fe04b112
SW		 517 mtspr(SPRN_MCSR, mcsr);
518 return mfspr(SPRN_MCSR) == 0 && recoverable;
519}
520
47c0bd1a
BH		 521int machine_check_e500(struct pt_regs *regs)
522{
523 unsigned long reason = get_mc_reason(regs);
524
cce1f106
SX		 525 if (reason & MCSR_BUS_RBERR) {
526 if (fsl_rio_mcheck_exception(regs))
527 return 1;
528 }
529
14cf11af
PM		 530 printk("Machine check in kernel mode.\n");
531 printk("Caused by (from MCSR=%lx): ", reason);
532
533 if (reason & MCSR_MCP)
534 printk("Machine Check Signal\n");
535 if (reason & MCSR_ICPERR)
536 printk("Instruction Cache Parity Error\n");
537 if (reason & MCSR_DCP_PERR)
538 printk("Data Cache Push Parity Error\n");
539 if (reason & MCSR_DCPERR)
540 printk("Data Cache Parity Error\n");
14cf11af
PM		 541 if (reason & MCSR_BUS_IAERR)
542 printk("Bus - Instruction Address Error\n");
543 if (reason & MCSR_BUS_RAERR)
544 printk("Bus - Read Address Error\n");
545 if (reason & MCSR_BUS_WAERR)
546 printk("Bus - Write Address Error\n");
547 if (reason & MCSR_BUS_IBERR)
548 printk("Bus - Instruction Data Error\n");
549 if (reason & MCSR_BUS_RBERR)
550 printk("Bus - Read Data Bus Error\n");
551 if (reason & MCSR_BUS_WBERR)
552 printk("Bus - Read Data Bus Error\n");
553 if (reason & MCSR_BUS_IPERR)
554 printk("Bus - Instruction Parity Error\n");
555 if (reason & MCSR_BUS_RPERR)
556 printk("Bus - Read Parity Error\n");
47c0bd1a
BH		 557
558 return 0;
559}
4490c06b
KG		 560
561int machine_check_generic(struct pt_regs *regs)
562{
563 return 0;
564}
47c0bd1a
BH		 565#elif defined(CONFIG_E200)
566int machine_check_e200(struct pt_regs *regs)
567{
568 unsigned long reason = get_mc_reason(regs);
569
14cf11af
PM		 570 printk("Machine check in kernel mode.\n");
571 printk("Caused by (from MCSR=%lx): ", reason);
572
573 if (reason & MCSR_MCP)
574 printk("Machine Check Signal\n");
575 if (reason & MCSR_CP_PERR)
576 printk("Cache Push Parity Error\n");
577 if (reason & MCSR_CPERR)
578 printk("Cache Parity Error\n");
579 if (reason & MCSR_EXCP_ERR)
580 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
581 if (reason & MCSR_BUS_IRERR)
582 printk("Bus - Read Bus Error on instruction fetch\n");
583 if (reason & MCSR_BUS_DRERR)
584 printk("Bus - Read Bus Error on data load\n");
585 if (reason & MCSR_BUS_WRERR)
586 printk("Bus - Write Bus Error on buffered store or cache line push\n");
47c0bd1a
BH		 587
588 return 0;
589}
590#else
591int machine_check_generic(struct pt_regs *regs)
592{
593 unsigned long reason = get_mc_reason(regs);
594
14cf11af
PM		 595 printk("Machine check in kernel mode.\n");
596 printk("Caused by (from SRR1=%lx): ", reason);
597 switch (reason & 0x601F0000) {
598 case 0x80000:
599 printk("Machine check signal\n");
600 break;
601 case 0: /* for 601 */
602 case 0x40000:
603 case 0x140000: /* 7450 MSS error and TEA */
604 printk("Transfer error ack signal\n");
605 break;
606 case 0x20000:
607 printk("Data parity error signal\n");
608 break;
609 case 0x10000:
610 printk("Address parity error signal\n");
611 break;
612 case 0x20000000:
613 printk("L1 Data Cache error\n");
614 break;
615 case 0x40000000:
616 printk("L1 Instruction Cache error\n");
617 break;
618 case 0x00100000:
619 printk("L2 data cache parity error\n");
620 break;
621 default:
622 printk("Unknown values in msr\n");
623 }
75918a4b
OJ		 624 return 0;
625}
47c0bd1a 626#endif /* everything else */
75918a4b
OJ		 627
628void machine_check_exception(struct pt_regs *regs)
629{
630 int recover = 0;
631
89713ed1
AB		 632 __get_cpu_var(irq_stat).mce_exceptions++;
633
47c0bd1a
BH		 634 /* See if any machine dependent calls. In theory, we would want
635 * to call the CPU first, and call the ppc_md. one if the CPU
636 * one returns a positive number. However there is existing code
637 * that assumes the board gets a first chance, so let's keep it
638 * that way for now and fix things later. --BenH.
639 */
75918a4b
OJ		 640 if (ppc_md.machine_check_exception)
641 recover = ppc_md.machine_check_exception(regs);
47c0bd1a
BH		 642 else if (cur_cpu_spec->machine_check)
643 recover = cur_cpu_spec->machine_check(regs);
75918a4b 644
47c0bd1a 645 if (recover > 0)
75918a4b
OJ		 646 return;
647
75918a4b 648#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
47c0bd1a
BH		 649 /* the qspan pci read routines can cause machine checks -- Cort
650 *
651 * yuck !!! that totally needs to go away ! There are better ways
652 * to deal with that than having a wart in the mcheck handler.
653 * -- BenH
654 */
75918a4b
OJ		 655 bad_page_fault(regs, regs->dar, SIGBUS);
656 return;
657#endif
658
a443506b 659 if (debugger_fault_handler(regs))
75918a4b 660 return;
75918a4b
OJ		 661
662 if (check_io_access(regs))
663 return;
664
8dad3f92 665 die("Machine check", regs, SIGBUS);
14cf11af
PM		 666
667 /* Must die if the interrupt is not recoverable */
668 if (!(regs->msr & MSR_RI))
669 panic("Unrecoverable Machine check");
670}
671
672void SMIException(struct pt_regs *regs)
673{
674 die("System Management Interrupt", regs, SIGABRT);
675}
676
dc1c1ca3 677void unknown_exception(struct pt_regs *regs)
14cf11af
PM		 678{
679 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
680 regs->nip, regs->msr, regs->trap);
681
682 _exception(SIGTRAP, regs, 0, 0);
683}
684
dc1c1ca3 685void instruction_breakpoint_exception(struct pt_regs *regs)
14cf11af
PM		 686{
687 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
688 5, SIGTRAP) == NOTIFY_STOP)
689 return;
690 if (debugger_iabr_match(regs))
691 return;
692 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
693}
694
695void RunModeException(struct pt_regs *regs)
696{
697 _exception(SIGTRAP, regs, 0, 0);
698}
699
8dad3f92 700void __kprobes single_step_exception(struct pt_regs *regs)
14cf11af 701{
2538c2d0 702 clear_single_step(regs);
14cf11af
PM		 703
704 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
705 5, SIGTRAP) == NOTIFY_STOP)
706 return;
707 if (debugger_sstep(regs))
708 return;
709
710 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
711}
712
713/*
714 * After we have successfully emulated an instruction, we have to
715 * check if the instruction was being single-stepped, and if so,
716 * pretend we got a single-step exception. This was pointed out
717 * by Kumar Gala. -- paulus
718 */
8dad3f92 719static void emulate_single_step(struct pt_regs *regs)
14cf11af 720{
2538c2d0
P		 721 if (single_stepping(regs))
722 single_step_exception(regs);
14cf11af
PM		 723}
724
5fad293b 725static inline int __parse_fpscr(unsigned long fpscr)
dc1c1ca3 726{
5fad293b 727 int ret = 0;
dc1c1ca3
SR		 728
729 /* Invalid operation */
730 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
5fad293b 731 ret = FPE_FLTINV;
dc1c1ca3
SR		 732
733 /* Overflow */
734 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
5fad293b 735 ret = FPE_FLTOVF;
dc1c1ca3
SR		 736
737 /* Underflow */
738 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
5fad293b 739 ret = FPE_FLTUND;
dc1c1ca3
SR		 740
741 /* Divide by zero */
742 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
5fad293b 743 ret = FPE_FLTDIV;
dc1c1ca3
SR		 744
745 /* Inexact result */
746 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
5fad293b
KG		 747 ret = FPE_FLTRES;
748
749 return ret;
750}
751
752static void parse_fpe(struct pt_regs *regs)
753{
754 int code = 0;
755
756 flush_fp_to_thread(current);
757
758 code = __parse_fpscr(current->thread.fpscr.val);
dc1c1ca3
SR		 759
760 _exception(SIGFPE, regs, code, regs->nip);
761}
762
763/*
764 * Illegal instruction emulation support. Originally written to
14cf11af
PM		 765 * provide the PVR to user applications using the mfspr rd, PVR.
766 * Return non-zero if we can't emulate, or -EFAULT if the associated
767 * memory access caused an access fault. Return zero on success.
768 *
769 * There are a couple of ways to do this, either "decode" the instruction
770 * or directly match lots of bits. In this case, matching lots of
771 * bits is faster and easier.
86417780 772 *
14cf11af 773 */
14cf11af
PM		 774static int emulate_string_inst(struct pt_regs *regs, u32 instword)
775{
776 u8 rT = (instword >> 21) & 0x1f;
777 u8 rA = (instword >> 16) & 0x1f;
778 u8 NB_RB = (instword >> 11) & 0x1f;
779 u32 num_bytes;
780 unsigned long EA;
781 int pos = 0;
782
783 /* Early out if we are an invalid form of lswx */
16c57b36 784 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
14cf11af
PM		 785 if ((rT == rA) || (rT == NB_RB))
786 return -EINVAL;
787
788 EA = (rA == 0) ? 0 : regs->gpr[rA];
789
16c57b36
KG		 790 switch (instword & PPC_INST_STRING_MASK) {
791 case PPC_INST_LSWX:
792 case PPC_INST_STSWX:
14cf11af
PM		 793 EA += NB_RB;
794 num_bytes = regs->xer & 0x7f;
795 break;
16c57b36
KG		 796 case PPC_INST_LSWI:
797 case PPC_INST_STSWI:
14cf11af
PM		 798 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
799 break;
800 default:
801 return -EINVAL;
802 }
803
804 while (num_bytes != 0)
805 {
806 u8 val;
807 u32 shift = 8 * (3 - (pos & 0x3));
808
16c57b36
KG		 809 switch ((instword & PPC_INST_STRING_MASK)) {
810 case PPC_INST_LSWX:
811 case PPC_INST_LSWI:
14cf11af
PM		 812 if (get_user(val, (u8 __user *)EA))
813 return -EFAULT;
814 /* first time updating this reg,
815 * zero it out */
816 if (pos == 0)
817 regs->gpr[rT] = 0;
818 regs->gpr[rT] |= val << shift;
819 break;
16c57b36
KG		 820 case PPC_INST_STSWI:
821 case PPC_INST_STSWX:
14cf11af
PM		 822 val = regs->gpr[rT] >> shift;
823 if (put_user(val, (u8 __user *)EA))
824 return -EFAULT;
825 break;
826 }
827 /* move EA to next address */
828 EA += 1;
829 num_bytes--;
830
831 /* manage our position within the register */
832 if (++pos == 4) {
833 pos = 0;
834 if (++rT == 32)
835 rT = 0;
836 }
837 }
838
839 return 0;
840}
841
c3412dcb
WS		 842static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
843{
844 u32 ra,rs;
845 unsigned long tmp;
846
847 ra = (instword >> 16) & 0x1f;
848 rs = (instword >> 21) & 0x1f;
849
850 tmp = regs->gpr[rs];
851 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
852 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
853 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
854 regs->gpr[ra] = tmp;
855
856 return 0;
857}
858
c1469f13
KG		 859static int emulate_isel(struct pt_regs *regs, u32 instword)
860{
861 u8 rT = (instword >> 21) & 0x1f;
862 u8 rA = (instword >> 16) & 0x1f;
863 u8 rB = (instword >> 11) & 0x1f;
864 u8 BC = (instword >> 6) & 0x1f;
865 u8 bit;
866 unsigned long tmp;
867
868 tmp = (rA == 0) ? 0 : regs->gpr[rA];
869 bit = (regs->ccr >> (31 - BC)) & 0x1;
870
871 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
872
873 return 0;
874}
875
14cf11af
PM		 876static int emulate_instruction(struct pt_regs *regs)
877{
878 u32 instword;
879 u32 rd;
880
fab5db97 881 if (!user_mode(regs) || (regs->msr & MSR_LE))
14cf11af
PM		 882 return -EINVAL;
883 CHECK_FULL_REGS(regs);
884
885 if (get_user(instword, (u32 __user *)(regs->nip)))
886 return -EFAULT;
887
888 /* Emulate the mfspr rD, PVR. */
16c57b36 889 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
eecff81d 890 PPC_WARN_EMULATED(mfpvr, regs);
14cf11af
PM		 891 rd = (instword >> 21) & 0x1f;
892 regs->gpr[rd] = mfspr(SPRN_PVR);
893 return 0;
894 }
895
896 /* Emulating the dcba insn is just a no-op. */
80947e7c 897 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
eecff81d 898 PPC_WARN_EMULATED(dcba, regs);
14cf11af 899 return 0;
80947e7c 900 }
14cf11af
PM		 901
902 /* Emulate the mcrxr insn. */
16c57b36 903 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
86417780 904 int shift = (instword >> 21) & 0x1c;
14cf11af
PM		 905 unsigned long msk = 0xf0000000UL >> shift;
906
eecff81d 907 PPC_WARN_EMULATED(mcrxr, regs);
14cf11af
PM		 908 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
909 regs->xer &= ~0xf0000000UL;
910 return 0;
911 }
912
913 /* Emulate load/store string insn. */
80947e7c 914 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
eecff81d 915 PPC_WARN_EMULATED(string, regs);
14cf11af 916 return emulate_string_inst(regs, instword);
80947e7c 917 }
14cf11af 918
c3412dcb 919 /* Emulate the popcntb (Population Count Bytes) instruction. */
16c57b36 920 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
eecff81d 921 PPC_WARN_EMULATED(popcntb, regs);
c3412dcb
WS		 922 return emulate_popcntb_inst(regs, instword);
923 }
924
c1469f13 925 /* Emulate isel (Integer Select) instruction */
16c57b36 926 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
eecff81d 927 PPC_WARN_EMULATED(isel, regs);
c1469f13
KG		 928 return emulate_isel(regs, instword);
929 }
930
efcac658
AK		 931#ifdef CONFIG_PPC64
932 /* Emulate the mfspr rD, DSCR. */
933 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
934 cpu_has_feature(CPU_FTR_DSCR)) {
935 PPC_WARN_EMULATED(mfdscr, regs);
936 rd = (instword >> 21) & 0x1f;
937 regs->gpr[rd] = mfspr(SPRN_DSCR);
938 return 0;
939 }
940 /* Emulate the mtspr DSCR, rD. */
941 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
942 cpu_has_feature(CPU_FTR_DSCR)) {
943 PPC_WARN_EMULATED(mtdscr, regs);
944 rd = (instword >> 21) & 0x1f;
945 mtspr(SPRN_DSCR, regs->gpr[rd]);
946 current->thread.dscr_inherit = 1;
947 return 0;
948 }
949#endif
950
14cf11af
PM		 951 return -EINVAL;
952}
953
73c9ceab 954int is_valid_bugaddr(unsigned long addr)
14cf11af 955{
73c9ceab 956 return is_kernel_addr(addr);
14cf11af
PM		 957}
958
8dad3f92 959void __kprobes program_check_exception(struct pt_regs *regs)
14cf11af
PM		 960{
961 unsigned int reason = get_reason(regs);
962 extern int do_mathemu(struct pt_regs *regs);
963
aa42c69c 964 /* We can now get here via a FP Unavailable exception if the core
04903a30 965 * has no FPU, in that case the reason flags will be 0 */
14cf11af 966
dc1c1ca3
SR		 967 if (reason & REASON_FP) {
968 /* IEEE FP exception */
969 parse_fpe(regs);
8dad3f92
PM		 970 return;
971 }
972 if (reason & REASON_TRAP) {
ba797b28
JW		 973 /* Debugger is first in line to stop recursive faults in
974 * rcu_lock, notify_die, or atomic_notifier_call_chain */
975 if (debugger_bpt(regs))
976 return;
977
14cf11af 978 /* trap exception */
dc1c1ca3
SR		 979 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
980 == NOTIFY_STOP)
981 return;
73c9ceab
JF		 982
983 if (!(regs->msr & MSR_PR) && /* not user-mode */
608e2619 984 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
14cf11af
PM		 985 regs->nip += 4;
986 return;
987 }
8dad3f92
PM		 988 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
989 return;
990 }
991
cd8a5673
PM		 992 local_irq_enable();
993
04903a30
KG		 994#ifdef CONFIG_MATH_EMULATION
995 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
996 * but there seems to be a hardware bug on the 405GP (RevD)
997 * that means ESR is sometimes set incorrectly - either to
998 * ESR_DST (!?) or 0. In the process of chasing this with the
999 * hardware people - not sure if it can happen on any illegal
1000 * instruction or only on FP instructions, whether there is a
25985edc 1001 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
5fad293b
KG		 1002 switch (do_mathemu(regs)) {
1003 case 0:
04903a30
KG		 1004 emulate_single_step(regs);
1005 return;
5fad293b
KG		 1006 case 1: {
1007 int code = 0;
1008 code = __parse_fpscr(current->thread.fpscr.val);
1009 _exception(SIGFPE, regs, code, regs->nip);
1010 return;
1011 }
1012 case -EFAULT:
1013 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1014 return;
04903a30 1015 }
5fad293b 1016 /* fall through on any other errors */
04903a30
KG		 1017#endif /* CONFIG_MATH_EMULATION */
1018
8dad3f92
PM		 1019 /* Try to emulate it if we should. */
1020 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
14cf11af
PM		 1021 switch (emulate_instruction(regs)) {
1022 case 0:
1023 regs->nip += 4;
1024 emulate_single_step(regs);
8dad3f92 1025 return;
14cf11af
PM		 1026 case -EFAULT:
1027 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
8dad3f92 1028 return;
14cf11af
PM		 1029 }
1030 }
8dad3f92
PM		 1031
1032 if (reason & REASON_PRIVILEGED)
1033 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1034 else
1035 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
14cf11af
PM		 1036}
1037
dc1c1ca3 1038void alignment_exception(struct pt_regs *regs)
14cf11af 1039{
4393c4f6 1040 int sig, code, fixed = 0;
14cf11af 1041
e9370ae1
PM		 1042 /* we don't implement logging of alignment exceptions */
1043 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1044 fixed = fix_alignment(regs);
14cf11af
PM		 1045
1046 if (fixed == 1) {
1047 regs->nip += 4; /* skip over emulated instruction */
1048 emulate_single_step(regs);
1049 return;
1050 }
1051
dc1c1ca3 1052 /* Operand address was bad */
14cf11af 1053 if (fixed == -EFAULT) {
4393c4f6
BH		 1054 sig = SIGSEGV;
1055 code = SEGV_ACCERR;
1056 } else {
1057 sig = SIGBUS;
1058 code = BUS_ADRALN;
14cf11af 1059 }
4393c4f6
BH		 1060 if (user_mode(regs))
1061 _exception(sig, regs, code, regs->dar);
1062 else
1063 bad_page_fault(regs, regs->dar, sig);
14cf11af
PM		 1064}
1065
1066void StackOverflow(struct pt_regs *regs)
1067{
1068 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1069 current, regs->gpr[1]);
1070 debugger(regs);
1071 show_regs(regs);
1072 panic("kernel stack overflow");
1073}
1074
1075void nonrecoverable_exception(struct pt_regs *regs)
1076{
1077 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1078 regs->nip, regs->msr);
1079 debugger(regs);
1080 die("nonrecoverable exception", regs, SIGKILL);
1081}
1082
1083void trace_syscall(struct pt_regs *regs)
1084{
1085 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
19c5870c 1086 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
14cf11af
PM		 1087 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1088}
dc1c1ca3 1089
dc1c1ca3
SR		 1090void kernel_fp_unavailable_exception(struct pt_regs *regs)
1091{
1092 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1093 "%lx at %lx\n", regs->trap, regs->nip);
1094 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1095}
dc1c1ca3
SR		 1096
1097void altivec_unavailable_exception(struct pt_regs *regs)
1098{
dc1c1ca3
SR		 1099 if (user_mode(regs)) {
1100 /* A user program has executed an altivec instruction,
1101 but this kernel doesn't support altivec. */
1102 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1103 return;
1104 }
6c4841c2 1105
dc1c1ca3
SR		 1106 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1107 "%lx at %lx\n", regs->trap, regs->nip);
1108 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
dc1c1ca3
SR		 1109}
1110
ce48b210
MN		 1111void vsx_unavailable_exception(struct pt_regs *regs)
1112{
1113 if (user_mode(regs)) {
1114 /* A user program has executed an vsx instruction,
1115 but this kernel doesn't support vsx. */
1116 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1117 return;
1118 }
1119
1120 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1121 "%lx at %lx\n", regs->trap, regs->nip);
1122 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1123}
1124
dc1c1ca3
SR		 1125void performance_monitor_exception(struct pt_regs *regs)
1126{
89713ed1
AB		 1127 __get_cpu_var(irq_stat).pmu_irqs++;
1128
dc1c1ca3
SR		 1129 perf_irq(regs);
1130}
dc1c1ca3 1131
8dad3f92 1132#ifdef CONFIG_8xx
14cf11af
PM		 1133void SoftwareEmulation(struct pt_regs *regs)
1134{
1135 extern int do_mathemu(struct pt_regs *);
1136 extern int Soft_emulate_8xx(struct pt_regs *);
5dd57a13 1137#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 1138 int errcode;
5dd57a13 1139#endif
14cf11af
PM		 1140
1141 CHECK_FULL_REGS(regs);
1142
1143 if (!user_mode(regs)) {
1144 debugger(regs);
1145 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1146 }
1147
1148#ifdef CONFIG_MATH_EMULATION
1149 errcode = do_mathemu(regs);
80947e7c 1150 if (errcode >= 0)
eecff81d 1151 PPC_WARN_EMULATED(math, regs);
5fad293b
KG		 1152
1153 switch (errcode) {
1154 case 0:
1155 emulate_single_step(regs);
1156 return;
1157 case 1: {
1158 int code = 0;
1159 code = __parse_fpscr(current->thread.fpscr.val);
1160 _exception(SIGFPE, regs, code, regs->nip);
1161 return;
1162 }
1163 case -EFAULT:
1164 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1165 return;
1166 default:
1167 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1168 return;
1169 }
1170
5dd57a13 1171#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
14cf11af 1172 errcode = Soft_emulate_8xx(regs);
80947e7c 1173 if (errcode >= 0)
eecff81d 1174 PPC_WARN_EMULATED(8xx, regs);
80947e7c 1175
5fad293b
KG		 1176 switch (errcode) {
1177 case 0:
14cf11af 1178 emulate_single_step(regs);
5fad293b
KG		 1179 return;
1180 case 1:
1181 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1182 return;
1183 case -EFAULT:
1184 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1185 return;
1186 }
5dd57a13
SW		 1187#else
1188 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
5fad293b 1189#endif
14cf11af 1190}
8dad3f92 1191#endif /* CONFIG_8xx */
14cf11af 1192
172ae2e7 1193#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3bffb652
DK		 1194static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1195{
1196 int changed = 0;
1197 /*
1198 * Determine the cause of the debug event, clear the
1199 * event flags and send a trap to the handler. Torez
1200 */
1201 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1202 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1203#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1204 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1205#endif
1206 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1207 5);
1208 changed |= 0x01;
1209 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1210 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1211 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1212 6);
1213 changed |= 0x01;
1214 } else if (debug_status & DBSR_IAC1) {
1215 current->thread.dbcr0 &= ~DBCR0_IAC1;
1216 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1217 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1218 1);
1219 changed |= 0x01;
1220 } else if (debug_status & DBSR_IAC2) {
1221 current->thread.dbcr0 &= ~DBCR0_IAC2;
1222 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1223 2);
1224 changed |= 0x01;
1225 } else if (debug_status & DBSR_IAC3) {
1226 current->thread.dbcr0 &= ~DBCR0_IAC3;
1227 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1228 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1229 3);
1230 changed |= 0x01;
1231 } else if (debug_status & DBSR_IAC4) {
1232 current->thread.dbcr0 &= ~DBCR0_IAC4;
1233 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1234 4);
1235 changed |= 0x01;
1236 }
1237 /*
1238 * At the point this routine was called, the MSR(DE) was turned off.
1239 * Check all other debug flags and see if that bit needs to be turned
1240 * back on or not.
1241 */
1242 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1243 regs->msr |= MSR_DE;
1244 else
1245 /* Make sure the IDM flag is off */
1246 current->thread.dbcr0 &= ~DBCR0_IDM;
1247
1248 if (changed & 0x01)
1249 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1250}
14cf11af 1251
f8279621 1252void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
14cf11af 1253{
3bffb652
DK		 1254 current->thread.dbsr = debug_status;
1255
ec097c84
RM		 1256 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1257 * on server, it stops on the target of the branch. In order to simulate
1258 * the server behaviour, we thus restart right away with a single step
1259 * instead of stopping here when hitting a BT
1260 */
1261 if (debug_status & DBSR_BT) {
1262 regs->msr &= ~MSR_DE;
1263
1264 /* Disable BT */
1265 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1266 /* Clear the BT event */
1267 mtspr(SPRN_DBSR, DBSR_BT);
1268
1269 /* Do the single step trick only when coming from userspace */
1270 if (user_mode(regs)) {
1271 current->thread.dbcr0 &= ~DBCR0_BT;
1272 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1273 regs->msr |= MSR_DE;
1274 return;
1275 }
1276
1277 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1278 5, SIGTRAP) == NOTIFY_STOP) {
1279 return;
1280 }
1281 if (debugger_sstep(regs))
1282 return;
1283 } else if (debug_status & DBSR_IC) { /* Instruction complete */
14cf11af 1284 regs->msr &= ~MSR_DE;
f8279621
KG		 1285
1286 /* Disable instruction completion */
1287 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1288 /* Clear the instruction completion event */
1289 mtspr(SPRN_DBSR, DBSR_IC);
1290
1291 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1292 5, SIGTRAP) == NOTIFY_STOP) {
1293 return;
1294 }
1295
1296 if (debugger_sstep(regs))
1297 return;
1298
d6a61bfc 1299 if (user_mode(regs)) {
3bffb652 1300 current->thread.dbcr0 &= ~DBCR0_IC;
3bffb652
DK		 1301 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1302 current->thread.dbcr1))
1303 regs->msr |= MSR_DE;
1304 else
1305 /* Make sure the IDM bit is off */
1306 current->thread.dbcr0 &= ~DBCR0_IDM;
d6a61bfc 1307 }
3bffb652
DK		 1308
1309 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1310 } else
1311 handle_debug(regs, debug_status);
14cf11af 1312}
172ae2e7 1313#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
14cf11af
PM		 1314
1315#if !defined(CONFIG_TAU_INT)
1316void TAUException(struct pt_regs *regs)
1317{
1318 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1319 regs->nip, regs->msr, regs->trap, print_tainted());
1320}
1321#endif /* CONFIG_INT_TAU */
14cf11af
PM		 1322
1323#ifdef CONFIG_ALTIVEC
dc1c1ca3 1324void altivec_assist_exception(struct pt_regs *regs)
14cf11af
PM		 1325{
1326 int err;
1327
14cf11af
PM		 1328 if (!user_mode(regs)) {
1329 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1330 " at %lx\n", regs->nip);
8dad3f92 1331 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
14cf11af
PM		 1332 }
1333
dc1c1ca3 1334 flush_altivec_to_thread(current);
dc1c1ca3 1335
eecff81d 1336 PPC_WARN_EMULATED(altivec, regs);
14cf11af
PM		 1337 err = emulate_altivec(regs);
1338 if (err == 0) {
1339 regs->nip += 4; /* skip emulated instruction */
1340 emulate_single_step(regs);
1341 return;
1342 }
1343
1344 if (err == -EFAULT) {
1345 /* got an error reading the instruction */
1346 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1347 } else {
1348 /* didn't recognize the instruction */
1349 /* XXX quick hack for now: set the non-Java bit in the VSCR */
76462232
CD		 1350 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1351 "in %s at %lx\n", current->comm, regs->nip);
14cf11af
PM		 1352 current->thread.vscr.u[3] |= 0x10000;
1353 }
1354}
1355#endif /* CONFIG_ALTIVEC */
1356
ce48b210
MN		 1357#ifdef CONFIG_VSX
1358void vsx_assist_exception(struct pt_regs *regs)
1359{
1360 if (!user_mode(regs)) {
1361 printk(KERN_EMERG "VSX assist exception in kernel mode"
1362 " at %lx\n", regs->nip);
1363 die("Kernel VSX assist exception", regs, SIGILL);
1364 }
1365
1366 flush_vsx_to_thread(current);
1367 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1368 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1369}
1370#endif /* CONFIG_VSX */
1371
14cf11af
PM		 1372#ifdef CONFIG_FSL_BOOKE
1373void CacheLockingException(struct pt_regs *regs, unsigned long address,
1374 unsigned long error_code)
1375{
1376 /* We treat cache locking instructions from the user
1377 * as priv ops, in the future we could try to do
1378 * something smarter
1379 */
1380 if (error_code & (ESR_DLK|ESR_ILK))
1381 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1382 return;
1383}
1384#endif /* CONFIG_FSL_BOOKE */
1385
1386#ifdef CONFIG_SPE
1387void SPEFloatingPointException(struct pt_regs *regs)
1388{
6a800f36 1389 extern int do_spe_mathemu(struct pt_regs *regs);
14cf11af
PM		 1390 unsigned long spefscr;
1391 int fpexc_mode;
1392 int code = 0;
6a800f36
LY		 1393 int err;
1394
685659ee 1395 flush_spe_to_thread(current);
14cf11af
PM		 1396
1397 spefscr = current->thread.spefscr;
1398 fpexc_mode = current->thread.fpexc_mode;
1399
14cf11af
PM		 1400 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1401 code = FPE_FLTOVF;
14cf11af
PM		 1402 }
1403 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1404 code = FPE_FLTUND;
14cf11af
PM		 1405 }
1406 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1407 code = FPE_FLTDIV;
1408 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1409 code = FPE_FLTINV;
14cf11af
PM		 1410 }
1411 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1412 code = FPE_FLTRES;
1413
6a800f36
LY		 1414 err = do_spe_mathemu(regs);
1415 if (err == 0) {
1416 regs->nip += 4; /* skip emulated instruction */
1417 emulate_single_step(regs);
1418 return;
1419 }
1420
1421 if (err == -EFAULT) {
1422 /* got an error reading the instruction */
1423 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1424 } else if (err == -EINVAL) {
1425 /* didn't recognize the instruction */
1426 printk(KERN_ERR "unrecognized spe instruction "
1427 "in %s at %lx\n", current->comm, regs->nip);
1428 } else {
1429 _exception(SIGFPE, regs, code, regs->nip);
1430 }
14cf11af 1431
14cf11af
PM		 1432 return;
1433}
6a800f36
LY		 1434
1435void SPEFloatingPointRoundException(struct pt_regs *regs)
1436{
1437 extern int speround_handler(struct pt_regs *regs);
1438 int err;
1439
1440 preempt_disable();
1441 if (regs->msr & MSR_SPE)
1442 giveup_spe(current);
1443 preempt_enable();
1444
1445 regs->nip -= 4;
1446 err = speround_handler(regs);
1447 if (err == 0) {
1448 regs->nip += 4; /* skip emulated instruction */
1449 emulate_single_step(regs);
1450 return;
1451 }
1452
1453 if (err == -EFAULT) {
1454 /* got an error reading the instruction */
1455 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1456 } else if (err == -EINVAL) {
1457 /* didn't recognize the instruction */
1458 printk(KERN_ERR "unrecognized spe instruction "
1459 "in %s at %lx\n", current->comm, regs->nip);
1460 } else {
1461 _exception(SIGFPE, regs, 0, regs->nip);
1462 return;
1463 }
1464}
14cf11af
PM		 1465#endif
1466
dc1c1ca3
SR		 1467/*
1468 * We enter here if we get an unrecoverable exception, that is, one
1469 * that happened at a point where the RI (recoverable interrupt) bit
1470 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1471 * we therefore lost state by taking this exception.
1472 */
1473void unrecoverable_exception(struct pt_regs *regs)
1474{
1475 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1476 regs->trap, regs->nip);
1477 die("Unrecoverable exception", regs, SIGABRT);
1478}
dc1c1ca3 1479
14cf11af
PM		 1480#ifdef CONFIG_BOOKE_WDT
1481/*
1482 * Default handler for a Watchdog exception,
1483 * spins until a reboot occurs
1484 */
1485void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1486{
1487 /* Generic WatchdogHandler, implement your own */
1488 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1489 return;
1490}
1491
1492void WatchdogException(struct pt_regs *regs)
1493{
1494 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1495 WatchdogHandler(regs);
1496}
1497#endif
dc1c1ca3 1498
dc1c1ca3
SR		 1499/*
1500 * We enter here if we discover during exception entry that we are
1501 * running in supervisor mode with a userspace value in the stack pointer.
1502 */
1503void kernel_bad_stack(struct pt_regs *regs)
1504{
1505 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1506 regs->gpr[1], regs->nip);
1507 die("Bad kernel stack pointer", regs, SIGABRT);
1508}
14cf11af
PM		 1509
1510void __init trap_init(void)
1511{
1512}
80947e7c
GU		 1513
1514
1515#ifdef CONFIG_PPC_EMULATED_STATS
1516
1517#define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1518
1519struct ppc_emulated ppc_emulated = {
1520#ifdef CONFIG_ALTIVEC
1521 WARN_EMULATED_SETUP(altivec),
1522#endif
1523 WARN_EMULATED_SETUP(dcba),
1524 WARN_EMULATED_SETUP(dcbz),
1525 WARN_EMULATED_SETUP(fp_pair),
1526 WARN_EMULATED_SETUP(isel),
1527 WARN_EMULATED_SETUP(mcrxr),
1528 WARN_EMULATED_SETUP(mfpvr),
1529 WARN_EMULATED_SETUP(multiple),
1530 WARN_EMULATED_SETUP(popcntb),
1531 WARN_EMULATED_SETUP(spe),
1532 WARN_EMULATED_SETUP(string),
1533 WARN_EMULATED_SETUP(unaligned),
1534#ifdef CONFIG_MATH_EMULATION
1535 WARN_EMULATED_SETUP(math),
1536#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1537 WARN_EMULATED_SETUP(8xx),
1538#endif
1539#ifdef CONFIG_VSX
1540 WARN_EMULATED_SETUP(vsx),
1541#endif
efcac658
AK		 1542#ifdef CONFIG_PPC64
1543 WARN_EMULATED_SETUP(mfdscr),
1544 WARN_EMULATED_SETUP(mtdscr),
1545#endif
80947e7c
GU		 1546};
1547
1548u32 ppc_warn_emulated;
1549
1550void ppc_warn_emulated_print(const char *type)
1551{
76462232
CD		 1552 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1553 type);
80947e7c
GU		 1554}
1555
1556static int __init ppc_warn_emulated_init(void)
1557{
1558 struct dentry *dir, *d;
1559 unsigned int i;
1560 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1561
1562 if (!powerpc_debugfs_root)
1563 return -ENODEV;
1564
1565 dir = debugfs_create_dir("emulated_instructions",
1566 powerpc_debugfs_root);
1567 if (!dir)
1568 return -ENOMEM;
1569
1570 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1571 &ppc_warn_emulated);
1572 if (!d)
1573 goto fail;
1574
1575 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1576 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1577 (u32 *)&entries[i].val.counter);
1578 if (!d)
1579 goto fail;
1580 }
1581
1582 return 0;
1583
1584fail:
1585 debugfs_remove_recursive(dir);
1586 return -ENOMEM;
1587}
1588
1589device_initcall(ppc_warn_emulated_init);
1590
1591#endif /* CONFIG_PPC_EMULATED_STATS */
Linux kernel - Deliverables
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