[deliverable/linux.git] / arch / powerpc / kvm / 44x_tlb.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright IBM Corp. 2007
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

#include <linux/types.h>
#include <linux/string.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/highmem.h>
#include <asm/mmu-44x.h>
#include <asm/kvm_ppc.h>

#include "44x_tlb.h"

#define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
#define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)

static unsigned int kvmppc_tlb_44x_pos;

#ifdef DEBUG
void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
{
	struct kvmppc_44x_tlbe *tlbe;
	int i;

	printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
	printk("| %2s | %3s | %8s | %8s | %8s |\n",
			"nr", "tid", "word0", "word1", "word2");

	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
		tlbe = &vcpu->arch.guest_tlb[i];
		if (tlbe->word0 & PPC44x_TLB_VALID)
			printk(" G%2d |  %02X | %08X | %08X | %08X |\n",
			       i, tlbe->tid, tlbe->word0, tlbe->word1,
			       tlbe->word2);
	}

	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
		tlbe = &vcpu->arch.shadow_tlb[i];
		if (tlbe->word0 & PPC44x_TLB_VALID)
			printk(" S%2d | %02X | %08X | %08X | %08X |\n",
			       i, tlbe->tid, tlbe->word0, tlbe->word1,
			       tlbe->word2);
	}
}
#endif

static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
{
	/* Mask off reserved bits. */
	attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_ATTR_MASK;

	if (!usermode) {
		/* Guest is in supervisor mode, so we need to translate guest
		 * supervisor permissions into user permissions. */
		attrib &= ~PPC44x_TLB_USER_PERM_MASK;
		attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
	}

	/* Make sure host can always access this memory. */
	attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;

	return attrib;
}

/* Search the guest TLB for a matching entry. */
int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
                         unsigned int as)
{
	int i;

	/* XXX Replace loop with fancy data structures. */
	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
		struct kvmppc_44x_tlbe *tlbe = &vcpu->arch.guest_tlb[i];
		unsigned int tid;

		if (eaddr < get_tlb_eaddr(tlbe))
			continue;

		if (eaddr > get_tlb_end(tlbe))
			continue;

		tid = get_tlb_tid(tlbe);
		if (tid && (tid != pid))
			continue;

		if (!get_tlb_v(tlbe))
			continue;

		if (get_tlb_ts(tlbe) != as)
			continue;

		return i;
	}

	return -1;
}

struct kvmppc_44x_tlbe *kvmppc_44x_itlb_search(struct kvm_vcpu *vcpu,
                                               gva_t eaddr)
{
	unsigned int as = !!(vcpu->arch.msr & MSR_IS);
	unsigned int index;

	index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
	if (index == -1)
		return NULL;
	return &vcpu->arch.guest_tlb[index];
}

struct kvmppc_44x_tlbe *kvmppc_44x_dtlb_search(struct kvm_vcpu *vcpu,
                                               gva_t eaddr)
{
	unsigned int as = !!(vcpu->arch.msr & MSR_DS);
	unsigned int index;

	index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
	if (index == -1)
		return NULL;
	return &vcpu->arch.guest_tlb[index];
}

static int kvmppc_44x_tlbe_is_writable(struct kvmppc_44x_tlbe *tlbe)
{
	return tlbe->word2 & (PPC44x_TLB_SW|PPC44x_TLB_UW);
}

static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu,
                                      unsigned int index)
{
	struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[index];
	struct page *page = vcpu->arch.shadow_pages[index];

	if (get_tlb_v(stlbe)) {
		if (kvmppc_44x_tlbe_is_writable(stlbe))
			kvm_release_page_dirty(page);
		else
			kvm_release_page_clean(page);
	}
}

void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
{
	int i;

	for (i = 0; i <= tlb_44x_hwater; i++)
		kvmppc_44x_shadow_release(vcpu, i);
}

void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i)
{
    vcpu->arch.shadow_tlb_mod[i] = 1;
}

/* Caller must ensure that the specified guest TLB entry is safe to insert into
 * the shadow TLB. */
void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid,
                    u32 flags)
{
	struct page *new_page;
	struct kvmppc_44x_tlbe *stlbe;
	hpa_t hpaddr;
	unsigned int victim;

	/* Future optimization: don't overwrite the TLB entry containing the
	 * current PC (or stack?). */
	victim = kvmppc_tlb_44x_pos++;
	if (kvmppc_tlb_44x_pos > tlb_44x_hwater)
		kvmppc_tlb_44x_pos = 0;
	stlbe = &vcpu->arch.shadow_tlb[victim];

	/* Get reference to new page. */
	new_page = gfn_to_page(vcpu->kvm, gfn);
	if (is_error_page(new_page)) {
		printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
		kvm_release_page_clean(new_page);
		return;
	}
	hpaddr = page_to_phys(new_page);

	/* Drop reference to old page. */
	kvmppc_44x_shadow_release(vcpu, victim);

	vcpu->arch.shadow_pages[victim] = new_page;

	/* XXX Make sure (va, size) doesn't overlap any other
	 * entries. 440x6 user manual says the result would be
	 * "undefined." */

	/* XXX what about AS? */

	stlbe->tid = !(asid & 0xff);

	/* Force TS=1 for all guest mappings. */
	/* For now we hardcode 4KB mappings, but it will be important to
	 * use host large pages in the future. */
	stlbe->word0 = (gvaddr & PAGE_MASK) | PPC44x_TLB_VALID | PPC44x_TLB_TS
	               | PPC44x_TLB_4K;
	stlbe->word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
	stlbe->word2 = kvmppc_44x_tlb_shadow_attrib(flags,
	                                            vcpu->arch.msr & MSR_PR);
	kvmppc_tlbe_set_modified(vcpu, victim);

	KVMTRACE_5D(STLB_WRITE, vcpu, victim,
			stlbe->tid, stlbe->word0, stlbe->word1, stlbe->word2,
			handler);
}

static void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
                                  gva_t eend, u32 asid)
{
	unsigned int pid = !(asid & 0xff);
	int i;

	/* XXX Replace loop with fancy data structures. */
	for (i = 0; i <= tlb_44x_hwater; i++) {
		struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
		unsigned int tid;

		if (!get_tlb_v(stlbe))
			continue;

		if (eend < get_tlb_eaddr(stlbe))
			continue;

		if (eaddr > get_tlb_end(stlbe))
			continue;

		tid = get_tlb_tid(stlbe);
		if (tid && (tid != pid))
			continue;

		kvmppc_44x_shadow_release(vcpu, i);
		stlbe->word0 = 0;
		kvmppc_tlbe_set_modified(vcpu, i);
		KVMTRACE_5D(STLB_INVAL, vcpu, i,
				stlbe->tid, stlbe->word0, stlbe->word1,
				stlbe->word2, handler);
	}
}

/* Invalidate all mappings on the privilege switch after PID has been changed.
 * The guest always runs with PID=1, so we must clear the entire TLB when
 * switching address spaces. */
void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
{
	int i;

	if (vcpu->arch.swap_pid) {
		/* XXX Replace loop with fancy data structures. */
		for (i = 0; i <= tlb_44x_hwater; i++) {
			struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];

			/* Future optimization: clear only userspace mappings. */
			kvmppc_44x_shadow_release(vcpu, i);
			stlbe->word0 = 0;
			kvmppc_tlbe_set_modified(vcpu, i);
			KVMTRACE_5D(STLB_INVAL, vcpu, i,
			            stlbe->tid, stlbe->word0, stlbe->word1,
			            stlbe->word2, handler);
		}
		vcpu->arch.swap_pid = 0;
	}

	vcpu->arch.shadow_pid = !usermode;
}

static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
                             const struct kvmppc_44x_tlbe *tlbe)
{
	gpa_t gpa;

	if (!get_tlb_v(tlbe))
		return 0;

	/* Does it match current guest AS? */
	/* XXX what about IS != DS? */
	if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
		return 0;

	gpa = get_tlb_raddr(tlbe);
	if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
		/* Mapping is not for RAM. */
		return 0;

	return 1;
}

int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
{
	u64 eaddr;
	u64 raddr;
	u64 asid;
	u32 flags;
	struct kvmppc_44x_tlbe *tlbe;
	unsigned int index;

	index = vcpu->arch.gpr[ra];
	if (index > PPC44x_TLB_SIZE) {
		printk("%s: index %d\n", __func__, index);
		kvmppc_dump_vcpu(vcpu);
		return EMULATE_FAIL;
	}

	tlbe = &vcpu->arch.guest_tlb[index];

	/* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
	if (tlbe->word0 & PPC44x_TLB_VALID) {
		eaddr = get_tlb_eaddr(tlbe);
		asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
		kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
	}

	switch (ws) {
	case PPC44x_TLB_PAGEID:
		tlbe->tid = vcpu->arch.mmucr & 0xff;
		tlbe->word0 = vcpu->arch.gpr[rs];
		break;

	case PPC44x_TLB_XLAT:
		tlbe->word1 = vcpu->arch.gpr[rs];
		break;

	case PPC44x_TLB_ATTRIB:
		tlbe->word2 = vcpu->arch.gpr[rs];
		break;

	default:
		return EMULATE_FAIL;
	}

	if (tlbe_is_host_safe(vcpu, tlbe)) {
		eaddr = get_tlb_eaddr(tlbe);
		raddr = get_tlb_raddr(tlbe);
		asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
		flags = tlbe->word2 & 0xffff;

		/* Create a 4KB mapping on the host. If the guest wanted a
		 * large page, only the first 4KB is mapped here and the rest
		 * are mapped on the fly. */
		kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
	}

	KVMTRACE_5D(GTLB_WRITE, vcpu, index,
	            tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
	            handler);

	return EMULATE_DONE;
}

int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
{
	u32 ea;
	int index;
	unsigned int as = get_mmucr_sts(vcpu);
	unsigned int pid = get_mmucr_stid(vcpu);

	ea = vcpu->arch.gpr[rb];
	if (ra)
		ea += vcpu->arch.gpr[ra];

	index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
	if (rc) {
		if (index < 0)
			vcpu->arch.cr &= ~0x20000000;
		else
			vcpu->arch.cr |= 0x20000000;
	}
	vcpu->arch.gpr[rt] = index;

	return EMULATE_DONE;
}
Commit	Line	Data
bbf45ba5 HB	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright IBM Corp. 2007
	16	*
	17	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	18	*/
	19
	20	#include <linux/types.h>
	21	#include <linux/string.h>
31711f22	22	#include <linux/kvm.h>
bbf45ba5 HB	23	#include <linux/kvm_host.h>
	24	#include <linux/highmem.h>
	25	#include <asm/mmu-44x.h>
	26	#include <asm/kvm_ppc.h>
	27
	28	#include "44x_tlb.h"
	29
	30	#define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX\|PPC44x_TLB_UR\|PPC44x_TLB_UW)
	31	#define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX\|PPC44x_TLB_SR\|PPC44x_TLB_SW)
	32
	33	static unsigned int kvmppc_tlb_44x_pos;
	34
a0d7b9f2 HB	35	#ifdef DEBUG
	36	void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
	37	{
	38	struct kvmppc_44x_tlbe *tlbe;
	39	int i;
	40
	41	printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
	42	printk("\| %2s \| %3s \| %8s \| %8s \| %8s \|\n",
	43	"nr", "tid", "word0", "word1", "word2");
	44
	45	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
	46	tlbe = &vcpu->arch.guest_tlb[i];
	47	if (tlbe->word0 & PPC44x_TLB_VALID)
	48	printk(" G%2d \| %02X \| %08X \| %08X \| %08X \|\n",
	49	i, tlbe->tid, tlbe->word0, tlbe->word1,
	50	tlbe->word2);
	51	}
	52
	53	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
	54	tlbe = &vcpu->arch.shadow_tlb[i];
	55	if (tlbe->word0 & PPC44x_TLB_VALID)
	56	printk(" S%2d \| %02X \| %08X \| %08X \| %08X \|\n",
	57	i, tlbe->tid, tlbe->word0, tlbe->word1,
	58	tlbe->word2);
	59	}
	60	}
	61	#endif
	62
bbf45ba5 HB	63	static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
	64	{
	65	/* Mask off reserved bits. */
	66	attrib &= PPC44x_TLB_PERM_MASK\|PPC44x_TLB_ATTR_MASK;
	67
	68	if (!usermode) {
	69	/* Guest is in supervisor mode, so we need to translate guest
	70	* supervisor permissions into user permissions. */
	71	attrib &= ~PPC44x_TLB_USER_PERM_MASK;
	72	attrib \|= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
	73	}
	74
	75	/* Make sure host can always access this memory. */
	76	attrib \|= PPC44x_TLB_SX\|PPC44x_TLB_SR\|PPC44x_TLB_SW;
	77
	78	return attrib;
	79	}
	80
	81	/* Search the guest TLB for a matching entry. */
	82	int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
	83	unsigned int as)
	84	{
	85	int i;
	86
	87	/* XXX Replace loop with fancy data structures. */
	88	for (i = 0; i < PPC44x_TLB_SIZE; i++) {
0f55dc48	89	struct kvmppc_44x_tlbe *tlbe = &vcpu->arch.guest_tlb[i];
bbf45ba5 HB	90	unsigned int tid;
	91
	92	if (eaddr < get_tlb_eaddr(tlbe))
	93	continue;
	94
	95	if (eaddr > get_tlb_end(tlbe))
	96	continue;
	97
	98	tid = get_tlb_tid(tlbe);
	99	if (tid && (tid != pid))
	100	continue;
	101
	102	if (!get_tlb_v(tlbe))
	103	continue;
	104
	105	if (get_tlb_ts(tlbe) != as)
	106	continue;
	107
	108	return i;
	109	}
	110
	111	return -1;
	112	}
	113
0f55dc48 HB	114	struct kvmppc_44x_tlbe kvmppc_44x_itlb_search(struct kvm_vcpu vcpu,
0f55dc48 HB	115	gva_t eaddr)
bbf45ba5 HB	116	{
	117	unsigned int as = !!(vcpu->arch.msr & MSR_IS);
	118	unsigned int index;
	119
	120	index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
	121	if (index == -1)
	122	return NULL;
	123	return &vcpu->arch.guest_tlb[index];
	124	}
	125
0f55dc48 HB	126	struct kvmppc_44x_tlbe kvmppc_44x_dtlb_search(struct kvm_vcpu vcpu,
0f55dc48 HB	127	gva_t eaddr)
bbf45ba5 HB	128	{
	129	unsigned int as = !!(vcpu->arch.msr & MSR_DS);
	130	unsigned int index;
	131
	132	index = kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
	133	if (index == -1)
	134	return NULL;
	135	return &vcpu->arch.guest_tlb[index];
	136	}
	137
0f55dc48	138	static int kvmppc_44x_tlbe_is_writable(struct kvmppc_44x_tlbe *tlbe)
bbf45ba5 HB	139	{
	140	return tlbe->word2 & (PPC44x_TLB_SW\|PPC44x_TLB_UW);
	141	}
	142
bbf45ba5 HB	143	static void kvmppc_44x_shadow_release(struct kvm_vcpu *vcpu,
	144	unsigned int index)
	145	{
0f55dc48	146	struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[index];
bbf45ba5 HB	147	struct page *page = vcpu->arch.shadow_pages[index];
bbf45ba5 HB	148
bbf45ba5 HB	149	if (get_tlb_v(stlbe)) {
	150	if (kvmppc_44x_tlbe_is_writable(stlbe))
	151	kvm_release_page_dirty(page);
	152	else
	153	kvm_release_page_clean(page);
	154	}
	155	}
	156
c30f8a6c HB	157	void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
	158	{
	159	int i;
	160
	161	for (i = 0; i <= tlb_44x_hwater; i++)
	162	kvmppc_44x_shadow_release(vcpu, i);
	163	}
	164
83aae4a8 HB	165	void kvmppc_tlbe_set_modified(struct kvm_vcpu *vcpu, unsigned int i)
	166	{
	167	vcpu->arch.shadow_tlb_mod[i] = 1;
	168	}
	169
bbf45ba5 HB	170	/* Caller must ensure that the specified guest TLB entry is safe to insert into
	171	* the shadow TLB. */
	172	void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gfn_t gfn, u64 asid,
	173	u32 flags)
	174	{
	175	struct page *new_page;
0f55dc48	176	struct kvmppc_44x_tlbe *stlbe;
bbf45ba5 HB	177	hpa_t hpaddr;
	178	unsigned int victim;
	179
	180	/* Future optimization: don't overwrite the TLB entry containing the
	181	* current PC (or stack?). */
	182	victim = kvmppc_tlb_44x_pos++;
	183	if (kvmppc_tlb_44x_pos > tlb_44x_hwater)
	184	kvmppc_tlb_44x_pos = 0;
	185	stlbe = &vcpu->arch.shadow_tlb[victim];
	186
	187	/* Get reference to new page. */
bbf45ba5 HB	188	new_page = gfn_to_page(vcpu->kvm, gfn);
bbf45ba5 HB	189	if (is_error_page(new_page)) {
9dcb40e1	190	printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
bbf45ba5 HB	191	kvm_release_page_clean(new_page);
	192	return;
	193	}
	194	hpaddr = page_to_phys(new_page);
	195
	196	/* Drop reference to old page. */
	197	kvmppc_44x_shadow_release(vcpu, victim);
bbf45ba5 HB	198
	199	vcpu->arch.shadow_pages[victim] = new_page;
	200
	201	/* XXX Make sure (va, size) doesn't overlap any other
	202	* entries. 440x6 user manual says the result would be
	203	* "undefined." */
	204
	205	/* XXX what about AS? */
	206
49dd2c49	207	stlbe->tid = !(asid & 0xff);
bbf45ba5 HB	208
	209	/* Force TS=1 for all guest mappings. */
	210	/* For now we hardcode 4KB mappings, but it will be important to
	211	* use host large pages in the future. */
	212	stlbe->word0 = (gvaddr & PAGE_MASK) \| PPC44x_TLB_VALID \| PPC44x_TLB_TS
	213	\| PPC44x_TLB_4K;
bbf45ba5 HB	214	stlbe->word1 = (hpaddr & 0xfffffc00) \| ((hpaddr >> 32) & 0xf);
	215	stlbe->word2 = kvmppc_44x_tlb_shadow_attrib(flags,
	216	vcpu->arch.msr & MSR_PR);
83aae4a8	217	kvmppc_tlbe_set_modified(vcpu, victim);
31711f22 JY	218
	219	KVMTRACE_5D(STLB_WRITE, vcpu, victim,
	220	stlbe->tid, stlbe->word0, stlbe->word1, stlbe->word2,
	221	handler);
bbf45ba5 HB	222	}
bbf45ba5 HB	223
a0d7b9f2 HB	224	static void kvmppc_mmu_invalidate(struct kvm_vcpu *vcpu, gva_t eaddr,
a0d7b9f2 HB	225	gva_t eend, u32 asid)
bbf45ba5	226	{
49dd2c49	227	unsigned int pid = !(asid & 0xff);
bbf45ba5 HB	228	int i;
	229
	230	/* XXX Replace loop with fancy data structures. */
bbf45ba5	231	for (i = 0; i <= tlb_44x_hwater; i++) {
0f55dc48	232	struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
bbf45ba5 HB	233	unsigned int tid;
	234
	235	if (!get_tlb_v(stlbe))
	236	continue;
	237
cc04454f	238	if (eend < get_tlb_eaddr(stlbe))
bbf45ba5 HB	239	continue;
	240
	241	if (eaddr > get_tlb_end(stlbe))
	242	continue;
	243
	244	tid = get_tlb_tid(stlbe);
	245	if (tid && (tid != pid))
	246	continue;
	247
	248	kvmppc_44x_shadow_release(vcpu, i);
	249	stlbe->word0 = 0;
83aae4a8	250	kvmppc_tlbe_set_modified(vcpu, i);
31711f22 JY	251	KVMTRACE_5D(STLB_INVAL, vcpu, i,
	252	stlbe->tid, stlbe->word0, stlbe->word1,
	253	stlbe->word2, handler);
bbf45ba5	254	}
bbf45ba5 HB	255	}
bbf45ba5 HB	256
49dd2c49 HB	257	/* Invalidate all mappings on the privilege switch after PID has been changed.
	258	* The guest always runs with PID=1, so we must clear the entire TLB when
	259	* switching address spaces. */
bbf45ba5 HB	260	void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
	261	{
	262	int i;
	263
49dd2c49 HB	264	if (vcpu->arch.swap_pid) {
49dd2c49 HB	265	/* XXX Replace loop with fancy data structures. */
49dd2c49	266	for (i = 0; i <= tlb_44x_hwater; i++) {
0f55dc48	267	struct kvmppc_44x_tlbe *stlbe = &vcpu->arch.shadow_tlb[i];
49dd2c49 HB	268
	269	/* Future optimization: clear only userspace mappings. */
	270	kvmppc_44x_shadow_release(vcpu, i);
	271	stlbe->word0 = 0;
	272	kvmppc_tlbe_set_modified(vcpu, i);
	273	KVMTRACE_5D(STLB_INVAL, vcpu, i,
	274	stlbe->tid, stlbe->word0, stlbe->word1,
	275	stlbe->word2, handler);
	276	}
49dd2c49	277	vcpu->arch.swap_pid = 0;
bbf45ba5	278	}
49dd2c49 HB	279
49dd2c49 HB	280	vcpu->arch.shadow_pid = !usermode;
bbf45ba5	281	}
a0d7b9f2 HB	282
a0d7b9f2 HB	283	static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
0f55dc48	284	const struct kvmppc_44x_tlbe *tlbe)
a0d7b9f2 HB	285	{
	286	gpa_t gpa;
	287
	288	if (!get_tlb_v(tlbe))
	289	return 0;
	290
	291	/* Does it match current guest AS? */
	292	/* XXX what about IS != DS? */
	293	if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
	294	return 0;
	295
	296	gpa = get_tlb_raddr(tlbe);
	297	if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
	298	/* Mapping is not for RAM. */
	299	return 0;
	300
	301	return 1;
	302	}
	303
75f74f0d	304	int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
a0d7b9f2 HB	305	{
	306	u64 eaddr;
	307	u64 raddr;
	308	u64 asid;
	309	u32 flags;
0f55dc48	310	struct kvmppc_44x_tlbe *tlbe;
a0d7b9f2 HB	311	unsigned int index;
	312
	313	index = vcpu->arch.gpr[ra];
	314	if (index > PPC44x_TLB_SIZE) {
	315	printk("%s: index %d\n", __func__, index);
	316	kvmppc_dump_vcpu(vcpu);
	317	return EMULATE_FAIL;
	318	}
	319
	320	tlbe = &vcpu->arch.guest_tlb[index];
	321
	322	/* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
	323	if (tlbe->word0 & PPC44x_TLB_VALID) {
	324	eaddr = get_tlb_eaddr(tlbe);
	325	asid = (tlbe->word0 & PPC44x_TLB_TS) \| tlbe->tid;
	326	kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
	327	}
	328
	329	switch (ws) {
	330	case PPC44x_TLB_PAGEID:
	331	tlbe->tid = vcpu->arch.mmucr & 0xff;
	332	tlbe->word0 = vcpu->arch.gpr[rs];
	333	break;
	334
	335	case PPC44x_TLB_XLAT:
	336	tlbe->word1 = vcpu->arch.gpr[rs];
	337	break;
	338
	339	case PPC44x_TLB_ATTRIB:
	340	tlbe->word2 = vcpu->arch.gpr[rs];
	341	break;
	342
	343	default:
	344	return EMULATE_FAIL;
	345	}
	346
	347	if (tlbe_is_host_safe(vcpu, tlbe)) {
	348	eaddr = get_tlb_eaddr(tlbe);
	349	raddr = get_tlb_raddr(tlbe);
	350	asid = (tlbe->word0 & PPC44x_TLB_TS) \| tlbe->tid;
	351	flags = tlbe->word2 & 0xffff;
	352
	353	/* Create a 4KB mapping on the host. If the guest wanted a
	354	* large page, only the first 4KB is mapped here and the rest
	355	* are mapped on the fly. */
	356	kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
	357	}
	358
	359	KVMTRACE_5D(GTLB_WRITE, vcpu, index,
	360	tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
	361	handler);
	362
	363	return EMULATE_DONE;
	364	}
	365
75f74f0d	366	int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
a0d7b9f2 HB	367	{
	368	u32 ea;
	369	int index;
	370	unsigned int as = get_mmucr_sts(vcpu);
	371	unsigned int pid = get_mmucr_stid(vcpu);
	372
	373	ea = vcpu->arch.gpr[rb];
	374	if (ra)
	375	ea += vcpu->arch.gpr[ra];
	376
	377	index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
	378	if (rc) {
	379	if (index < 0)
	380	vcpu->arch.cr &= ~0x20000000;
	381	else
	382	vcpu->arch.cr \|= 0x20000000;
	383	}
	384	vcpu->arch.gpr[rt] = index;
	385
	386	return EMULATE_DONE;
	387	}