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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
14 | * | |
15 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
16 | * | |
17 | * Derived from book3s_interrupts.S, which is: | |
18 | * Copyright SUSE Linux Products GmbH 2009 | |
19 | * | |
20 | * Authors: Alexander Graf <agraf@suse.de> | |
21 | */ | |
22 | ||
23 | #include <asm/ppc_asm.h> | |
24 | #include <asm/kvm_asm.h> | |
25 | #include <asm/reg.h> | |
26 | #include <asm/page.h> | |
27 | #include <asm/asm-offsets.h> | |
28 | #include <asm/exception-64s.h> | |
29 | #include <asm/ppc-opcode.h> | |
30 | ||
31 | /***************************************************************************** | |
32 | * * | |
33 | * Guest entry / exit code that is in kernel module memory (vmalloc) * | |
34 | * * | |
35 | ****************************************************************************/ | |
36 | ||
37 | /* Registers: | |
38 | * r4: vcpu pointer | |
39 | */ | |
40 | _GLOBAL(__kvmppc_vcore_entry) | |
41 | ||
42 | /* Write correct stack frame */ | |
43 | mflr r0 | |
44 | std r0,PPC_LR_STKOFF(r1) | |
45 | ||
46 | /* Save host state to the stack */ | |
47 | stdu r1, -SWITCH_FRAME_SIZE(r1) | |
48 | ||
a5ddea0e | 49 | /* Save non-volatile registers (r14 - r31) and CR */ |
de56a948 | 50 | SAVE_NVGPRS(r1) |
a5ddea0e PM |
51 | mfcr r3 |
52 | std r3, _CCR(r1) | |
de56a948 PM |
53 | |
54 | /* Save host DSCR */ | |
9e368f29 | 55 | BEGIN_FTR_SECTION |
de56a948 PM |
56 | mfspr r3, SPRN_DSCR |
57 | std r3, HSTATE_DSCR(r13) | |
9e368f29 | 58 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
59 | |
60 | /* Save host DABR */ | |
61 | mfspr r3, SPRN_DABR | |
62 | std r3, HSTATE_DABR(r13) | |
63 | ||
64 | /* Hard-disable interrupts */ | |
65 | mfmsr r10 | |
66 | std r10, HSTATE_HOST_MSR(r13) | |
67 | rldicl r10,r10,48,1 | |
68 | rotldi r10,r10,16 | |
69 | mtmsrd r10,1 | |
70 | ||
8943633c | 71 | /* Save host PMU registers */ |
de56a948 PM |
72 | /* R4 is live here (vcpu pointer) but not r3 or r5 */ |
73 | li r3, 1 | |
74 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
75 | mfspr r7, SPRN_MMCR0 /* save MMCR0 */ | |
76 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */ | |
8943633c PM |
77 | mfspr r6, SPRN_MMCRA |
78 | BEGIN_FTR_SECTION | |
79 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
80 | li r5, 0 | |
81 | mtspr SPRN_MMCRA, r5 | |
82 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
83 | isync |
84 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
85 | lbz r5, LPPACA_PMCINUSE(r3) | |
86 | cmpwi r5, 0 | |
87 | beq 31f /* skip if not */ | |
88 | mfspr r5, SPRN_MMCR1 | |
de56a948 PM |
89 | std r7, HSTATE_MMCR(r13) |
90 | std r5, HSTATE_MMCR + 8(r13) | |
91 | std r6, HSTATE_MMCR + 16(r13) | |
92 | mfspr r3, SPRN_PMC1 | |
93 | mfspr r5, SPRN_PMC2 | |
94 | mfspr r6, SPRN_PMC3 | |
95 | mfspr r7, SPRN_PMC4 | |
96 | mfspr r8, SPRN_PMC5 | |
97 | mfspr r9, SPRN_PMC6 | |
9e368f29 PM |
98 | BEGIN_FTR_SECTION |
99 | mfspr r10, SPRN_PMC7 | |
100 | mfspr r11, SPRN_PMC8 | |
101 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
102 | stw r3, HSTATE_PMC(r13) |
103 | stw r5, HSTATE_PMC + 4(r13) | |
104 | stw r6, HSTATE_PMC + 8(r13) | |
105 | stw r7, HSTATE_PMC + 12(r13) | |
106 | stw r8, HSTATE_PMC + 16(r13) | |
107 | stw r9, HSTATE_PMC + 20(r13) | |
9e368f29 PM |
108 | BEGIN_FTR_SECTION |
109 | stw r10, HSTATE_PMC + 24(r13) | |
110 | stw r11, HSTATE_PMC + 28(r13) | |
111 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
112 | 31: |
113 | ||
114 | /* | |
115 | * Put whatever is in the decrementer into the | |
116 | * hypervisor decrementer. | |
117 | */ | |
118 | mfspr r8,SPRN_DEC | |
119 | mftb r7 | |
120 | mtspr SPRN_HDEC,r8 | |
121 | extsw r8,r8 | |
122 | add r8,r8,r7 | |
123 | std r8,HSTATE_DECEXP(r13) | |
124 | ||
9e368f29 PM |
125 | /* |
126 | * On PPC970, if the guest vcpu has an external interrupt pending, | |
127 | * send ourselves an IPI so as to interrupt the guest once it | |
128 | * enables interrupts. (It must have interrupts disabled, | |
129 | * otherwise we would already have delivered the interrupt.) | |
130 | */ | |
131 | BEGIN_FTR_SECTION | |
132 | ld r0, VCPU_PENDING_EXC(r4) | |
133 | li r7, (1 << BOOK3S_IRQPRIO_EXTERNAL) | |
134 | oris r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h | |
135 | and. r0, r0, r7 | |
136 | beq 32f | |
137 | mr r31, r4 | |
138 | lhz r3, PACAPACAINDEX(r13) | |
139 | bl smp_send_reschedule | |
140 | nop | |
141 | mr r4, r31 | |
142 | 32: | |
143 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
144 | ||
de56a948 PM |
145 | /* Jump to partition switch code */ |
146 | bl .kvmppc_hv_entry_trampoline | |
147 | nop | |
148 | ||
149 | /* | |
150 | * We return here in virtual mode after the guest exits | |
151 | * with something that we can't handle in real mode. | |
152 | * Interrupts are enabled again at this point. | |
153 | */ | |
154 | ||
155 | .global kvmppc_handler_highmem | |
156 | kvmppc_handler_highmem: | |
157 | ||
158 | /* | |
159 | * Register usage at this point: | |
160 | * | |
161 | * R1 = host R1 | |
162 | * R2 = host R2 | |
163 | * R12 = exit handler id | |
164 | * R13 = PACA | |
165 | */ | |
166 | ||
a5ddea0e | 167 | /* Restore non-volatile host registers (r14 - r31) and CR */ |
de56a948 | 168 | REST_NVGPRS(r1) |
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169 | ld r4, _CCR(r1) |
170 | mtcr r4 | |
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171 | |
172 | addi r1, r1, SWITCH_FRAME_SIZE | |
173 | ld r0, PPC_LR_STKOFF(r1) | |
174 | mtlr r0 | |
175 | blr |