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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
29 | ||
30 | /***************************************************************************** | |
31 | * * | |
32 | * Real Mode handlers that need to be in the linear mapping * | |
33 | * * | |
34 | ****************************************************************************/ | |
35 | ||
de56a948 PM |
36 | .globl kvmppc_skip_interrupt |
37 | kvmppc_skip_interrupt: | |
38 | mfspr r13,SPRN_SRR0 | |
39 | addi r13,r13,4 | |
40 | mtspr SPRN_SRR0,r13 | |
41 | GET_SCRATCH0(r13) | |
42 | rfid | |
43 | b . | |
44 | ||
45 | .globl kvmppc_skip_Hinterrupt | |
46 | kvmppc_skip_Hinterrupt: | |
47 | mfspr r13,SPRN_HSRR0 | |
48 | addi r13,r13,4 | |
49 | mtspr SPRN_HSRR0,r13 | |
50 | GET_SCRATCH0(r13) | |
51 | hrfid | |
52 | b . | |
53 | ||
54 | /* | |
19ccb76a | 55 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
56 | * Must be called with interrupts hard-disabled. |
57 | * | |
58 | * Input Registers: | |
59 | * | |
60 | * LR = return address to continue at after eventually re-enabling MMU | |
61 | */ | |
62 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
63 | mfmsr r10 | |
64 | LOAD_REG_ADDR(r5, kvmppc_hv_entry) | |
65 | li r0,MSR_RI | |
66 | andc r0,r10,r0 | |
67 | li r6,MSR_IR | MSR_DR | |
68 | andc r6,r10,r6 | |
69 | mtmsrd r0,1 /* clear RI in MSR */ | |
70 | mtsrr0 r5 | |
71 | mtsrr1 r6 | |
72 | RFI | |
73 | ||
74 | #define ULONG_SIZE 8 | |
75 | #define VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) | |
76 | ||
77 | /****************************************************************************** | |
78 | * * | |
79 | * Entry code * | |
80 | * * | |
81 | *****************************************************************************/ | |
82 | ||
371fefd6 PM |
83 | #define XICS_XIRR 4 |
84 | #define XICS_QIRR 0xc | |
85 | ||
86 | /* | |
87 | * We come in here when wakened from nap mode on a secondary hw thread. | |
88 | * Relocation is off and most register values are lost. | |
89 | * r13 points to the PACA. | |
90 | */ | |
91 | .globl kvm_start_guest | |
92 | kvm_start_guest: | |
93 | ld r1,PACAEMERGSP(r13) | |
94 | subi r1,r1,STACK_FRAME_OVERHEAD | |
19ccb76a PM |
95 | ld r2,PACATOC(r13) |
96 | ||
97 | /* were we napping due to cede? */ | |
98 | lbz r0,HSTATE_NAPPING(r13) | |
99 | cmpwi r0,0 | |
100 | bne kvm_end_cede | |
371fefd6 PM |
101 | |
102 | /* get vcpu pointer */ | |
103 | ld r4, HSTATE_KVM_VCPU(r13) | |
104 | ||
105 | /* We got here with an IPI; clear it */ | |
106 | ld r5, HSTATE_XICS_PHYS(r13) | |
107 | li r0, 0xff | |
108 | li r6, XICS_QIRR | |
109 | li r7, XICS_XIRR | |
110 | lwzcix r8, r5, r7 /* ack the interrupt */ | |
111 | sync | |
112 | stbcix r0, r5, r6 /* clear it */ | |
113 | stwcix r8, r5, r7 /* EOI it */ | |
114 | ||
2fde6d20 PM |
115 | /* NV GPR values from power7_idle() will no longer be valid */ |
116 | stb r0, PACA_NAPSTATELOST(r13) | |
117 | ||
de56a948 PM |
118 | .global kvmppc_hv_entry |
119 | kvmppc_hv_entry: | |
120 | ||
121 | /* Required state: | |
122 | * | |
123 | * R4 = vcpu pointer | |
124 | * MSR = ~IR|DR | |
125 | * R13 = PACA | |
126 | * R1 = host R1 | |
127 | * all other volatile GPRS = free | |
128 | */ | |
129 | mflr r0 | |
130 | std r0, HSTATE_VMHANDLER(r13) | |
131 | ||
132 | ld r14, VCPU_GPR(r14)(r4) | |
133 | ld r15, VCPU_GPR(r15)(r4) | |
134 | ld r16, VCPU_GPR(r16)(r4) | |
135 | ld r17, VCPU_GPR(r17)(r4) | |
136 | ld r18, VCPU_GPR(r18)(r4) | |
137 | ld r19, VCPU_GPR(r19)(r4) | |
138 | ld r20, VCPU_GPR(r20)(r4) | |
139 | ld r21, VCPU_GPR(r21)(r4) | |
140 | ld r22, VCPU_GPR(r22)(r4) | |
141 | ld r23, VCPU_GPR(r23)(r4) | |
142 | ld r24, VCPU_GPR(r24)(r4) | |
143 | ld r25, VCPU_GPR(r25)(r4) | |
144 | ld r26, VCPU_GPR(r26)(r4) | |
145 | ld r27, VCPU_GPR(r27)(r4) | |
146 | ld r28, VCPU_GPR(r28)(r4) | |
147 | ld r29, VCPU_GPR(r29)(r4) | |
148 | ld r30, VCPU_GPR(r30)(r4) | |
149 | ld r31, VCPU_GPR(r31)(r4) | |
150 | ||
151 | /* Load guest PMU registers */ | |
152 | /* R4 is live here (vcpu pointer) */ | |
153 | li r3, 1 | |
154 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
155 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
156 | isync | |
157 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ | |
158 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
159 | lwz r6, VCPU_PMC + 8(r4) | |
160 | lwz r7, VCPU_PMC + 12(r4) | |
161 | lwz r8, VCPU_PMC + 16(r4) | |
162 | lwz r9, VCPU_PMC + 20(r4) | |
9e368f29 PM |
163 | BEGIN_FTR_SECTION |
164 | lwz r10, VCPU_PMC + 24(r4) | |
165 | lwz r11, VCPU_PMC + 28(r4) | |
166 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
167 | mtspr SPRN_PMC1, r3 |
168 | mtspr SPRN_PMC2, r5 | |
169 | mtspr SPRN_PMC3, r6 | |
170 | mtspr SPRN_PMC4, r7 | |
171 | mtspr SPRN_PMC5, r8 | |
172 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
173 | BEGIN_FTR_SECTION |
174 | mtspr SPRN_PMC7, r10 | |
175 | mtspr SPRN_PMC8, r11 | |
176 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
177 | ld r3, VCPU_MMCR(r4) |
178 | ld r5, VCPU_MMCR + 8(r4) | |
179 | ld r6, VCPU_MMCR + 16(r4) | |
180 | mtspr SPRN_MMCR1, r5 | |
181 | mtspr SPRN_MMCRA, r6 | |
182 | mtspr SPRN_MMCR0, r3 | |
183 | isync | |
184 | ||
185 | /* Load up FP, VMX and VSX registers */ | |
186 | bl kvmppc_load_fp | |
187 | ||
9e368f29 | 188 | BEGIN_FTR_SECTION |
de56a948 PM |
189 | /* Switch DSCR to guest value */ |
190 | ld r5, VCPU_DSCR(r4) | |
191 | mtspr SPRN_DSCR, r5 | |
9e368f29 | 192 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
193 | |
194 | /* | |
195 | * Set the decrementer to the guest decrementer. | |
196 | */ | |
197 | ld r8,VCPU_DEC_EXPIRES(r4) | |
198 | mftb r7 | |
199 | subf r3,r7,r8 | |
200 | mtspr SPRN_DEC,r3 | |
201 | stw r3,VCPU_DEC(r4) | |
202 | ||
203 | ld r5, VCPU_SPRG0(r4) | |
204 | ld r6, VCPU_SPRG1(r4) | |
205 | ld r7, VCPU_SPRG2(r4) | |
206 | ld r8, VCPU_SPRG3(r4) | |
207 | mtspr SPRN_SPRG0, r5 | |
208 | mtspr SPRN_SPRG1, r6 | |
209 | mtspr SPRN_SPRG2, r7 | |
210 | mtspr SPRN_SPRG3, r8 | |
211 | ||
212 | /* Save R1 in the PACA */ | |
213 | std r1, HSTATE_HOST_R1(r13) | |
214 | ||
a8606e20 PM |
215 | /* Increment yield count if they have a VPA */ |
216 | ld r3, VCPU_VPA(r4) | |
217 | cmpdi r3, 0 | |
218 | beq 25f | |
219 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
220 | addi r5, r5, 1 | |
221 | stw r5, LPPACA_YIELDCOUNT(r3) | |
222 | 25: | |
de56a948 PM |
223 | /* Load up DAR and DSISR */ |
224 | ld r5, VCPU_DAR(r4) | |
225 | lwz r6, VCPU_DSISR(r4) | |
226 | mtspr SPRN_DAR, r5 | |
227 | mtspr SPRN_DSISR, r6 | |
228 | ||
229 | /* Set partition DABR */ | |
230 | li r5,3 | |
231 | ld r6,VCPU_DABR(r4) | |
232 | mtspr SPRN_DABRX,r5 | |
233 | mtspr SPRN_DABR,r6 | |
234 | ||
9e368f29 | 235 | BEGIN_FTR_SECTION |
de56a948 PM |
236 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
237 | ld r5,VCPU_AMR(r4) | |
238 | ld r6,VCPU_UAMOR(r4) | |
239 | li r7,-1 | |
240 | mtspr SPRN_AMR,r5 | |
241 | mtspr SPRN_UAMOR,r6 | |
242 | mtspr SPRN_AMOR,r7 | |
9e368f29 | 243 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
244 | |
245 | /* Clear out SLB */ | |
246 | li r6,0 | |
247 | slbmte r6,r6 | |
248 | slbia | |
249 | ptesync | |
250 | ||
9e368f29 PM |
251 | BEGIN_FTR_SECTION |
252 | b 30f | |
253 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
254 | /* | |
255 | * POWER7 host -> guest partition switch code. | |
256 | * We don't have to lock against concurrent tlbies, | |
257 | * but we do have to coordinate across hardware threads. | |
258 | */ | |
371fefd6 PM |
259 | /* Increment entry count iff exit count is zero. */ |
260 | ld r5,HSTATE_KVM_VCORE(r13) | |
261 | addi r9,r5,VCORE_ENTRY_EXIT | |
262 | 21: lwarx r3,0,r9 | |
263 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
264 | bge secondary_too_late /* if so we're too late to the party */ | |
265 | addi r3,r3,1 | |
266 | stwcx. r3,0,r9 | |
267 | bne 21b | |
268 | ||
269 | /* Primary thread switches to guest partition. */ | |
aa04b4cc | 270 | ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ |
371fefd6 PM |
271 | lwz r6,VCPU_PTID(r4) |
272 | cmpwi r6,0 | |
273 | bne 20f | |
de56a948 PM |
274 | ld r6,KVM_SDR1(r9) |
275 | lwz r7,KVM_LPID(r9) | |
276 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
277 | mtspr SPRN_LPID,r0 | |
278 | ptesync | |
279 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
280 | mtspr SPRN_LPID,r7 | |
281 | isync | |
371fefd6 PM |
282 | li r0,1 |
283 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ | |
284 | b 10f | |
285 | ||
286 | /* Secondary threads wait for primary to have done partition switch */ | |
287 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
288 | cmpwi r0,0 | |
289 | beq 20b | |
aa04b4cc | 290 | |
19ccb76a | 291 | /* Set LPCR and RMOR. */ |
aa04b4cc | 292 | 10: ld r8,KVM_LPCR(r9) |
19ccb76a | 293 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
294 | ld r8,KVM_RMOR(r9) |
295 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
296 | isync |
297 | ||
298 | /* Check if HDEC expires soon */ | |
299 | mfspr r3,SPRN_HDEC | |
300 | cmpwi r3,10 | |
301 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
302 | mr r9,r4 | |
303 | blt hdec_soon | |
304 | ||
305 | /* | |
306 | * Invalidate the TLB if we could possibly have stale TLB | |
307 | * entries for this partition on this core due to the use | |
308 | * of tlbiel. | |
371fefd6 | 309 | * XXX maybe only need this on primary thread? |
de56a948 PM |
310 | */ |
311 | ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ | |
312 | lwz r5,VCPU_VCPUID(r4) | |
313 | lhz r6,PACAPACAINDEX(r13) | |
371fefd6 | 314 | rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */ |
de56a948 PM |
315 | lhz r8,VCPU_LAST_CPU(r4) |
316 | sldi r7,r6,1 /* see if this is the same vcpu */ | |
317 | add r7,r7,r9 /* as last ran on this pcpu */ | |
318 | lhz r0,KVM_LAST_VCPU(r7) | |
319 | cmpw r6,r8 /* on the same cpu core as last time? */ | |
320 | bne 3f | |
321 | cmpw r0,r5 /* same vcpu as this core last ran? */ | |
322 | beq 1f | |
323 | 3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */ | |
324 | sth r5,KVM_LAST_VCPU(r7) | |
325 | li r6,128 | |
326 | mtctr r6 | |
327 | li r7,0x800 /* IS field = 0b10 */ | |
328 | ptesync | |
329 | 2: tlbiel r7 | |
330 | addi r7,r7,0x1000 | |
331 | bdnz 2b | |
332 | ptesync | |
333 | 1: | |
334 | ||
335 | /* Save purr/spurr */ | |
336 | mfspr r5,SPRN_PURR | |
337 | mfspr r6,SPRN_SPURR | |
338 | std r5,HSTATE_PURR(r13) | |
339 | std r6,HSTATE_SPURR(r13) | |
340 | ld r7,VCPU_PURR(r4) | |
341 | ld r8,VCPU_SPURR(r4) | |
342 | mtspr SPRN_PURR,r7 | |
343 | mtspr SPRN_SPURR,r8 | |
9e368f29 PM |
344 | b 31f |
345 | ||
346 | /* | |
347 | * PPC970 host -> guest partition switch code. | |
348 | * We have to lock against concurrent tlbies, | |
349 | * using native_tlbie_lock to lock against host tlbies | |
350 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
351 | * We also have to invalidate the TLB since its | |
352 | * entries aren't tagged with the LPID. | |
353 | */ | |
354 | 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ | |
355 | ||
356 | /* first take native_tlbie_lock */ | |
357 | .section ".toc","aw" | |
358 | toc_tlbie_lock: | |
359 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
360 | .previous | |
361 | ld r3,toc_tlbie_lock@toc(2) | |
362 | lwz r8,PACA_LOCK_TOKEN(r13) | |
363 | 24: lwarx r0,0,r3 | |
364 | cmpwi r0,0 | |
365 | bne 24b | |
366 | stwcx. r8,0,r3 | |
367 | bne 24b | |
368 | isync | |
369 | ||
370 | ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */ | |
371 | li r0,0x18f | |
372 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
373 | or r0,r7,r0 | |
374 | ptesync | |
375 | sync | |
376 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
377 | isync | |
378 | li r0,0 | |
379 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
380 | ||
381 | /* invalidate the whole TLB */ | |
382 | li r0,256 | |
383 | mtctr r0 | |
384 | li r6,0 | |
385 | 25: tlbiel r6 | |
386 | addi r6,r6,0x1000 | |
387 | bdnz 25b | |
388 | ptesync | |
389 | ||
390 | /* Take the guest's tlbie_lock */ | |
391 | addi r3,r9,KVM_TLBIE_LOCK | |
392 | 24: lwarx r0,0,r3 | |
393 | cmpwi r0,0 | |
394 | bne 24b | |
395 | stwcx. r8,0,r3 | |
396 | bne 24b | |
397 | isync | |
398 | ld r6,KVM_SDR1(r9) | |
399 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
400 | ||
401 | /* Set up HID4 with the guest's LPID etc. */ | |
402 | sync | |
403 | mtspr SPRN_HID4,r7 | |
404 | isync | |
405 | ||
406 | /* drop the guest's tlbie_lock */ | |
407 | li r0,0 | |
408 | stw r0,0(r3) | |
409 | ||
410 | /* Check if HDEC expires soon */ | |
411 | mfspr r3,SPRN_HDEC | |
412 | cmpwi r3,10 | |
413 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
414 | mr r9,r4 | |
415 | blt hdec_soon | |
416 | ||
417 | /* Enable HDEC interrupts */ | |
418 | mfspr r0,SPRN_HID0 | |
419 | li r3,1 | |
420 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
421 | sync | |
422 | mtspr SPRN_HID0,r0 | |
423 | mfspr r0,SPRN_HID0 | |
424 | mfspr r0,SPRN_HID0 | |
425 | mfspr r0,SPRN_HID0 | |
426 | mfspr r0,SPRN_HID0 | |
427 | mfspr r0,SPRN_HID0 | |
428 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
429 | |
430 | /* Load up guest SLB entries */ | |
9e368f29 | 431 | 31: lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
432 | cmpwi r5,0 |
433 | beq 9f | |
434 | mtctr r5 | |
435 | addi r6,r4,VCPU_SLB | |
436 | 1: ld r8,VCPU_SLB_E(r6) | |
437 | ld r9,VCPU_SLB_V(r6) | |
438 | slbmte r9,r8 | |
439 | addi r6,r6,VCPU_SLB_SIZE | |
440 | bdnz 1b | |
441 | 9: | |
442 | ||
443 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
444 | lwz r5,VCPU_CTRL(r4) | |
445 | andi. r5,r5,1 | |
446 | bne 4f | |
447 | mfspr r6,SPRN_CTRLF | |
448 | clrrdi r6,r6,1 | |
449 | mtspr SPRN_CTRLT,r6 | |
450 | 4: | |
451 | ld r6, VCPU_CTR(r4) | |
452 | lwz r7, VCPU_XER(r4) | |
453 | ||
454 | mtctr r6 | |
455 | mtxer r7 | |
456 | ||
19ccb76a | 457 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
de56a948 PM |
458 | ld r6, VCPU_SRR0(r4) |
459 | ld r7, VCPU_SRR1(r4) | |
de56a948 | 460 | ld r10, VCPU_PC(r4) |
19ccb76a | 461 | ld r11, VCPU_MSR(r4) /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 | 462 | |
de56a948 PM |
463 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
464 | rotldi r11, r11, 1 + MSR_HV_LG | |
465 | ori r11, r11, MSR_ME | |
466 | ||
19ccb76a PM |
467 | /* Check if we can deliver an external or decrementer interrupt now */ |
468 | ld r0,VCPU_PENDING_EXC(r4) | |
469 | li r8,(1 << BOOK3S_IRQPRIO_EXTERNAL) | |
470 | oris r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h | |
471 | and r0,r0,r8 | |
472 | cmpdi cr1,r0,0 | |
473 | andi. r0,r11,MSR_EE | |
474 | beq cr1,11f | |
475 | BEGIN_FTR_SECTION | |
476 | mfspr r8,SPRN_LPCR | |
477 | ori r8,r8,LPCR_MER | |
478 | mtspr SPRN_LPCR,r8 | |
479 | isync | |
480 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
481 | beq 5f | |
482 | li r0,BOOK3S_INTERRUPT_EXTERNAL | |
483 | 12: mr r6,r10 | |
484 | mr r10,r0 | |
485 | mr r7,r11 | |
486 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
487 | rotldi r11,r11,63 | |
488 | b 5f | |
489 | 11: beq 5f | |
490 | mfspr r0,SPRN_DEC | |
491 | cmpwi r0,0 | |
492 | li r0,BOOK3S_INTERRUPT_DECREMENTER | |
493 | blt 12b | |
494 | ||
495 | /* Move SRR0 and SRR1 into the respective regs */ | |
496 | 5: mtspr SPRN_SRR0, r6 | |
497 | mtspr SPRN_SRR1, r7 | |
498 | li r0,0 | |
499 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
500 | ||
de56a948 PM |
501 | fast_guest_return: |
502 | mtspr SPRN_HSRR0,r10 | |
503 | mtspr SPRN_HSRR1,r11 | |
504 | ||
505 | /* Activate guest mode, so faults get handled by KVM */ | |
506 | li r9, KVM_GUEST_MODE_GUEST | |
507 | stb r9, HSTATE_IN_GUEST(r13) | |
508 | ||
509 | /* Enter guest */ | |
510 | ||
511 | ld r5, VCPU_LR(r4) | |
512 | lwz r6, VCPU_CR(r4) | |
513 | mtlr r5 | |
514 | mtcr r6 | |
515 | ||
516 | ld r0, VCPU_GPR(r0)(r4) | |
517 | ld r1, VCPU_GPR(r1)(r4) | |
518 | ld r2, VCPU_GPR(r2)(r4) | |
519 | ld r3, VCPU_GPR(r3)(r4) | |
520 | ld r5, VCPU_GPR(r5)(r4) | |
521 | ld r6, VCPU_GPR(r6)(r4) | |
522 | ld r7, VCPU_GPR(r7)(r4) | |
523 | ld r8, VCPU_GPR(r8)(r4) | |
524 | ld r9, VCPU_GPR(r9)(r4) | |
525 | ld r10, VCPU_GPR(r10)(r4) | |
526 | ld r11, VCPU_GPR(r11)(r4) | |
527 | ld r12, VCPU_GPR(r12)(r4) | |
528 | ld r13, VCPU_GPR(r13)(r4) | |
529 | ||
530 | ld r4, VCPU_GPR(r4)(r4) | |
531 | ||
532 | hrfid | |
533 | b . | |
534 | ||
535 | /****************************************************************************** | |
536 | * * | |
537 | * Exit code * | |
538 | * * | |
539 | *****************************************************************************/ | |
540 | ||
541 | /* | |
542 | * We come here from the first-level interrupt handlers. | |
543 | */ | |
544 | .globl kvmppc_interrupt | |
545 | kvmppc_interrupt: | |
546 | /* | |
547 | * Register contents: | |
548 | * R12 = interrupt vector | |
549 | * R13 = PACA | |
550 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
551 | * guest R13 saved in SPRN_SCRATCH0 | |
552 | */ | |
553 | /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */ | |
554 | std r9, HSTATE_HOST_R2(r13) | |
555 | ld r9, HSTATE_KVM_VCPU(r13) | |
556 | ||
557 | /* Save registers */ | |
558 | ||
559 | std r0, VCPU_GPR(r0)(r9) | |
560 | std r1, VCPU_GPR(r1)(r9) | |
561 | std r2, VCPU_GPR(r2)(r9) | |
562 | std r3, VCPU_GPR(r3)(r9) | |
563 | std r4, VCPU_GPR(r4)(r9) | |
564 | std r5, VCPU_GPR(r5)(r9) | |
565 | std r6, VCPU_GPR(r6)(r9) | |
566 | std r7, VCPU_GPR(r7)(r9) | |
567 | std r8, VCPU_GPR(r8)(r9) | |
568 | ld r0, HSTATE_HOST_R2(r13) | |
569 | std r0, VCPU_GPR(r9)(r9) | |
570 | std r10, VCPU_GPR(r10)(r9) | |
571 | std r11, VCPU_GPR(r11)(r9) | |
572 | ld r3, HSTATE_SCRATCH0(r13) | |
573 | lwz r4, HSTATE_SCRATCH1(r13) | |
574 | std r3, VCPU_GPR(r12)(r9) | |
575 | stw r4, VCPU_CR(r9) | |
576 | ||
577 | /* Restore R1/R2 so we can handle faults */ | |
578 | ld r1, HSTATE_HOST_R1(r13) | |
579 | ld r2, PACATOC(r13) | |
580 | ||
581 | mfspr r10, SPRN_SRR0 | |
582 | mfspr r11, SPRN_SRR1 | |
583 | std r10, VCPU_SRR0(r9) | |
584 | std r11, VCPU_SRR1(r9) | |
585 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
586 | beq 1f | |
587 | mfspr r10, SPRN_HSRR0 | |
588 | mfspr r11, SPRN_HSRR1 | |
589 | clrrdi r12, r12, 2 | |
590 | 1: std r10, VCPU_PC(r9) | |
591 | std r11, VCPU_MSR(r9) | |
592 | ||
593 | GET_SCRATCH0(r3) | |
594 | mflr r4 | |
595 | std r3, VCPU_GPR(r13)(r9) | |
596 | std r4, VCPU_LR(r9) | |
597 | ||
598 | /* Unset guest mode */ | |
599 | li r0, KVM_GUEST_MODE_NONE | |
600 | stb r0, HSTATE_IN_GUEST(r13) | |
601 | ||
602 | stw r12,VCPU_TRAP(r9) | |
603 | ||
697d3899 PM |
604 | /* Save HEIR (HV emulation assist reg) in last_inst |
605 | if this is an HEI (HV emulation interrupt, e40) */ | |
606 | li r3,KVM_INST_FETCH_FAILED | |
607 | BEGIN_FTR_SECTION | |
608 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
609 | bne 11f | |
610 | mfspr r3,SPRN_HEIR | |
611 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
612 | 11: stw r3,VCPU_LAST_INST(r9) | |
613 | ||
614 | /* these are volatile across C function calls */ | |
615 | mfctr r3 | |
616 | mfxer r4 | |
617 | std r3, VCPU_CTR(r9) | |
618 | stw r4, VCPU_XER(r9) | |
619 | ||
620 | BEGIN_FTR_SECTION | |
621 | /* If this is a page table miss then see if it's theirs or ours */ | |
622 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
623 | beq kvmppc_hdsi | |
342d3db7 PM |
624 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
625 | beq kvmppc_hisi | |
697d3899 PM |
626 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
627 | ||
de56a948 PM |
628 | /* See if this is a leftover HDEC interrupt */ |
629 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
630 | bne 2f | |
631 | mfspr r3,SPRN_HDEC | |
632 | cmpwi r3,0 | |
633 | bge ignore_hdec | |
634 | 2: | |
697d3899 | 635 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
636 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
637 | beq hcall_try_real_mode | |
de56a948 PM |
638 | |
639 | /* Check for mediated interrupts (could be done earlier really ...) */ | |
9e368f29 | 640 | BEGIN_FTR_SECTION |
de56a948 PM |
641 | cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL |
642 | bne+ 1f | |
de56a948 PM |
643 | andi. r0,r11,MSR_EE |
644 | beq 1f | |
19ccb76a | 645 | mfspr r5,SPRN_LPCR |
de56a948 PM |
646 | andi. r0,r5,LPCR_MER |
647 | bne bounce_ext_interrupt | |
648 | 1: | |
9e368f29 | 649 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 | 650 | |
697d3899 | 651 | nohpte_cont: |
19ccb76a | 652 | hcall_real_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 PM |
653 | /* Save DEC */ |
654 | mfspr r5,SPRN_DEC | |
655 | mftb r6 | |
656 | extsw r5,r5 | |
657 | add r5,r5,r6 | |
658 | std r5,VCPU_DEC_EXPIRES(r9) | |
659 | ||
de56a948 | 660 | /* Save more register state */ |
de56a948 PM |
661 | mfdar r6 |
662 | mfdsisr r7 | |
de56a948 PM |
663 | std r6, VCPU_DAR(r9) |
664 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 665 | BEGIN_FTR_SECTION |
697d3899 | 666 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
667 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
668 | beq 6f | |
9e368f29 | 669 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 670 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
671 | stw r7, VCPU_FAULT_DSISR(r9) |
672 | ||
673 | /* Save guest CTRL register, set runlatch to 1 */ | |
697d3899 | 674 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
675 | stw r6,VCPU_CTRL(r9) |
676 | andi. r0,r6,1 | |
677 | bne 4f | |
678 | ori r6,r6,1 | |
679 | mtspr SPRN_CTRLT,r6 | |
680 | 4: | |
681 | /* Read the guest SLB and save it away */ | |
682 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
683 | mtctr r0 | |
684 | li r6,0 | |
685 | addi r7,r9,VCPU_SLB | |
686 | li r5,0 | |
687 | 1: slbmfee r8,r6 | |
688 | andis. r0,r8,SLB_ESID_V@h | |
689 | beq 2f | |
690 | add r8,r8,r6 /* put index in */ | |
691 | slbmfev r3,r6 | |
692 | std r8,VCPU_SLB_E(r7) | |
693 | std r3,VCPU_SLB_V(r7) | |
694 | addi r7,r7,VCPU_SLB_SIZE | |
695 | addi r5,r5,1 | |
696 | 2: addi r6,r6,1 | |
697 | bdnz 1b | |
698 | stw r5,VCPU_SLB_MAX(r9) | |
699 | ||
700 | /* | |
701 | * Save the guest PURR/SPURR | |
702 | */ | |
9e368f29 | 703 | BEGIN_FTR_SECTION |
de56a948 PM |
704 | mfspr r5,SPRN_PURR |
705 | mfspr r6,SPRN_SPURR | |
706 | ld r7,VCPU_PURR(r9) | |
707 | ld r8,VCPU_SPURR(r9) | |
708 | std r5,VCPU_PURR(r9) | |
709 | std r6,VCPU_SPURR(r9) | |
710 | subf r5,r7,r5 | |
711 | subf r6,r8,r6 | |
712 | ||
713 | /* | |
714 | * Restore host PURR/SPURR and add guest times | |
715 | * so that the time in the guest gets accounted. | |
716 | */ | |
717 | ld r3,HSTATE_PURR(r13) | |
718 | ld r4,HSTATE_SPURR(r13) | |
719 | add r3,r3,r5 | |
720 | add r4,r4,r6 | |
721 | mtspr SPRN_PURR,r3 | |
722 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 723 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 PM |
724 | |
725 | /* Clear out SLB */ | |
726 | li r5,0 | |
727 | slbmte r5,r5 | |
728 | slbia | |
729 | ptesync | |
730 | ||
19ccb76a | 731 | hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */ |
9e368f29 PM |
732 | BEGIN_FTR_SECTION |
733 | b 32f | |
734 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
735 | /* | |
736 | * POWER7 guest -> host partition switch code. | |
737 | * We don't have to lock against tlbies but we do | |
738 | * have to coordinate the hardware threads. | |
739 | */ | |
371fefd6 PM |
740 | /* Increment the threads-exiting-guest count in the 0xff00 |
741 | bits of vcore->entry_exit_count */ | |
742 | lwsync | |
743 | ld r5,HSTATE_KVM_VCORE(r13) | |
744 | addi r6,r5,VCORE_ENTRY_EXIT | |
745 | 41: lwarx r3,0,r6 | |
746 | addi r0,r3,0x100 | |
747 | stwcx. r0,0,r6 | |
748 | bne 41b | |
19ccb76a | 749 | lwsync |
371fefd6 PM |
750 | |
751 | /* | |
752 | * At this point we have an interrupt that we have to pass | |
753 | * up to the kernel or qemu; we can't handle it in real mode. | |
754 | * Thus we have to do a partition switch, so we have to | |
755 | * collect the other threads, if we are the first thread | |
756 | * to take an interrupt. To do this, we set the HDEC to 0, | |
757 | * which causes an HDEC interrupt in all threads within 2ns | |
758 | * because the HDEC register is shared between all 4 threads. | |
759 | * However, we don't need to bother if this is an HDEC | |
760 | * interrupt, since the other threads will already be on their | |
761 | * way here in that case. | |
762 | */ | |
19ccb76a PM |
763 | cmpwi r3,0x100 /* Are we the first here? */ |
764 | bge 43f | |
765 | cmpwi r3,1 /* Are any other threads in the guest? */ | |
766 | ble 43f | |
371fefd6 PM |
767 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
768 | beq 40f | |
371fefd6 PM |
769 | li r0,0 |
770 | mtspr SPRN_HDEC,r0 | |
771 | 40: | |
19ccb76a PM |
772 | /* |
773 | * Send an IPI to any napping threads, since an HDEC interrupt | |
774 | * doesn't wake CPUs up from nap. | |
775 | */ | |
776 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
777 | lwz r4,VCPU_PTID(r9) | |
778 | li r0,1 | |
779 | sldi r0,r0,r4 | |
780 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ | |
781 | beq 43f | |
782 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
783 | subf r6,r4,r13 | |
784 | 42: andi. r0,r3,1 | |
785 | beq 44f | |
786 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
787 | li r0,IPI_PRIORITY | |
788 | li r7,XICS_QIRR | |
789 | stbcix r0,r7,r8 /* trigger the IPI */ | |
790 | 44: srdi. r3,r3,1 | |
791 | addi r6,r6,PACA_SIZE | |
792 | bne 42b | |
371fefd6 PM |
793 | |
794 | /* Secondary threads wait for primary to do partition switch */ | |
19ccb76a | 795 | 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ |
371fefd6 PM |
796 | ld r5,HSTATE_KVM_VCORE(r13) |
797 | lwz r3,VCPU_PTID(r9) | |
798 | cmpwi r3,0 | |
799 | beq 15f | |
800 | HMT_LOW | |
801 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
802 | cmpwi r3,0 | |
803 | bne 13b | |
804 | HMT_MEDIUM | |
805 | b 16f | |
806 | ||
807 | /* Primary thread waits for all the secondaries to exit guest */ | |
808 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
809 | srwi r0,r3,8 | |
810 | clrldi r3,r3,56 | |
811 | cmpw r3,r0 | |
812 | bne 15b | |
813 | isync | |
814 | ||
815 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
816 | ld r6,KVM_HOST_SDR1(r4) |
817 | lwz r7,KVM_HOST_LPID(r4) | |
818 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
819 | mtspr SPRN_LPID,r8 | |
820 | ptesync | |
821 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
822 | mtspr SPRN_LPID,r7 | |
823 | isync | |
371fefd6 PM |
824 | li r0,0 |
825 | stb r0,VCORE_IN_GUEST(r5) | |
de56a948 PM |
826 | lis r8,0x7fff /* MAX_INT@h */ |
827 | mtspr SPRN_HDEC,r8 | |
828 | ||
371fefd6 | 829 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
830 | mtspr SPRN_LPCR,r8 |
831 | isync | |
9e368f29 PM |
832 | b 33f |
833 | ||
834 | /* | |
835 | * PPC970 guest -> host partition switch code. | |
836 | * We have to lock against concurrent tlbies, and | |
837 | * we have to flush the whole TLB. | |
838 | */ | |
839 | 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ | |
840 | ||
841 | /* Take the guest's tlbie_lock */ | |
842 | lwz r8,PACA_LOCK_TOKEN(r13) | |
843 | addi r3,r4,KVM_TLBIE_LOCK | |
844 | 24: lwarx r0,0,r3 | |
845 | cmpwi r0,0 | |
846 | bne 24b | |
847 | stwcx. r8,0,r3 | |
848 | bne 24b | |
849 | isync | |
850 | ||
851 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
852 | li r0,0x18f | |
853 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
854 | or r0,r7,r0 | |
855 | ptesync | |
856 | sync | |
857 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
858 | isync | |
859 | li r0,0 | |
860 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
861 | ||
862 | /* invalidate the whole TLB */ | |
863 | li r0,256 | |
864 | mtctr r0 | |
865 | li r6,0 | |
866 | 25: tlbiel r6 | |
867 | addi r6,r6,0x1000 | |
868 | bdnz 25b | |
869 | ptesync | |
870 | ||
871 | /* take native_tlbie_lock */ | |
872 | ld r3,toc_tlbie_lock@toc(2) | |
873 | 24: lwarx r0,0,r3 | |
874 | cmpwi r0,0 | |
875 | bne 24b | |
876 | stwcx. r8,0,r3 | |
877 | bne 24b | |
878 | isync | |
879 | ||
880 | ld r6,KVM_HOST_SDR1(r4) | |
881 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
882 | ||
883 | /* Set up host HID4 value */ | |
884 | sync | |
885 | mtspr SPRN_HID4,r7 | |
886 | isync | |
887 | li r0,0 | |
888 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
889 | ||
890 | lis r8,0x7fff /* MAX_INT@h */ | |
891 | mtspr SPRN_HDEC,r8 | |
892 | ||
893 | /* Disable HDEC interrupts */ | |
894 | mfspr r0,SPRN_HID0 | |
895 | li r3,0 | |
896 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
897 | sync | |
898 | mtspr SPRN_HID0,r0 | |
899 | mfspr r0,SPRN_HID0 | |
900 | mfspr r0,SPRN_HID0 | |
901 | mfspr r0,SPRN_HID0 | |
902 | mfspr r0,SPRN_HID0 | |
903 | mfspr r0,SPRN_HID0 | |
904 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
905 | |
906 | /* load host SLB entries */ | |
9e368f29 | 907 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
908 | |
909 | .rept SLB_NUM_BOLTED | |
910 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
911 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
912 | andis. r7,r5,SLB_ESID_V@h | |
913 | beq 1f | |
914 | slbmte r6,r5 | |
915 | 1: addi r8,r8,16 | |
916 | .endr | |
917 | ||
918 | /* Save and reset AMR and UAMOR before turning on the MMU */ | |
9e368f29 | 919 | BEGIN_FTR_SECTION |
de56a948 PM |
920 | mfspr r5,SPRN_AMR |
921 | mfspr r6,SPRN_UAMOR | |
922 | std r5,VCPU_AMR(r9) | |
923 | std r6,VCPU_UAMOR(r9) | |
924 | li r6,0 | |
925 | mtspr SPRN_AMR,r6 | |
9e368f29 | 926 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
927 | |
928 | /* Restore host DABR and DABRX */ | |
929 | ld r5,HSTATE_DABR(r13) | |
930 | li r6,7 | |
931 | mtspr SPRN_DABR,r5 | |
932 | mtspr SPRN_DABRX,r6 | |
933 | ||
934 | /* Switch DSCR back to host value */ | |
9e368f29 | 935 | BEGIN_FTR_SECTION |
de56a948 PM |
936 | mfspr r8, SPRN_DSCR |
937 | ld r7, HSTATE_DSCR(r13) | |
938 | std r8, VCPU_DSCR(r7) | |
939 | mtspr SPRN_DSCR, r7 | |
9e368f29 | 940 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
941 | |
942 | /* Save non-volatile GPRs */ | |
943 | std r14, VCPU_GPR(r14)(r9) | |
944 | std r15, VCPU_GPR(r15)(r9) | |
945 | std r16, VCPU_GPR(r16)(r9) | |
946 | std r17, VCPU_GPR(r17)(r9) | |
947 | std r18, VCPU_GPR(r18)(r9) | |
948 | std r19, VCPU_GPR(r19)(r9) | |
949 | std r20, VCPU_GPR(r20)(r9) | |
950 | std r21, VCPU_GPR(r21)(r9) | |
951 | std r22, VCPU_GPR(r22)(r9) | |
952 | std r23, VCPU_GPR(r23)(r9) | |
953 | std r24, VCPU_GPR(r24)(r9) | |
954 | std r25, VCPU_GPR(r25)(r9) | |
955 | std r26, VCPU_GPR(r26)(r9) | |
956 | std r27, VCPU_GPR(r27)(r9) | |
957 | std r28, VCPU_GPR(r28)(r9) | |
958 | std r29, VCPU_GPR(r29)(r9) | |
959 | std r30, VCPU_GPR(r30)(r9) | |
960 | std r31, VCPU_GPR(r31)(r9) | |
961 | ||
962 | /* Save SPRGs */ | |
963 | mfspr r3, SPRN_SPRG0 | |
964 | mfspr r4, SPRN_SPRG1 | |
965 | mfspr r5, SPRN_SPRG2 | |
966 | mfspr r6, SPRN_SPRG3 | |
967 | std r3, VCPU_SPRG0(r9) | |
968 | std r4, VCPU_SPRG1(r9) | |
969 | std r5, VCPU_SPRG2(r9) | |
970 | std r6, VCPU_SPRG3(r9) | |
971 | ||
a8606e20 PM |
972 | /* Increment yield count if they have a VPA */ |
973 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
974 | cmpdi r8, 0 | |
975 | beq 25f | |
976 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
977 | addi r3, r3, 1 | |
978 | stw r3, LPPACA_YIELDCOUNT(r8) | |
979 | 25: | |
980 | /* Save PMU registers if requested */ | |
981 | /* r8 and cr0.eq are live here */ | |
de56a948 PM |
982 | li r3, 1 |
983 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
984 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
985 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
986 | isync | |
a8606e20 PM |
987 | beq 21f /* if no VPA, save PMU stuff anyway */ |
988 | lbz r7, LPPACA_PMCINUSE(r8) | |
989 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
990 | bne 21f | |
991 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
992 | b 22f | |
993 | 21: mfspr r5, SPRN_MMCR1 | |
de56a948 PM |
994 | mfspr r6, SPRN_MMCRA |
995 | std r4, VCPU_MMCR(r9) | |
996 | std r5, VCPU_MMCR + 8(r9) | |
997 | std r6, VCPU_MMCR + 16(r9) | |
998 | mfspr r3, SPRN_PMC1 | |
999 | mfspr r4, SPRN_PMC2 | |
1000 | mfspr r5, SPRN_PMC3 | |
1001 | mfspr r6, SPRN_PMC4 | |
1002 | mfspr r7, SPRN_PMC5 | |
1003 | mfspr r8, SPRN_PMC6 | |
9e368f29 PM |
1004 | BEGIN_FTR_SECTION |
1005 | mfspr r10, SPRN_PMC7 | |
1006 | mfspr r11, SPRN_PMC8 | |
1007 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1008 | stw r3, VCPU_PMC(r9) |
1009 | stw r4, VCPU_PMC + 4(r9) | |
1010 | stw r5, VCPU_PMC + 8(r9) | |
1011 | stw r6, VCPU_PMC + 12(r9) | |
1012 | stw r7, VCPU_PMC + 16(r9) | |
1013 | stw r8, VCPU_PMC + 20(r9) | |
9e368f29 PM |
1014 | BEGIN_FTR_SECTION |
1015 | stw r10, VCPU_PMC + 24(r9) | |
1016 | stw r11, VCPU_PMC + 28(r9) | |
1017 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1018 | 22: |
1019 | /* save FP state */ | |
1020 | mr r3, r9 | |
1021 | bl .kvmppc_save_fp | |
1022 | ||
9e368f29 PM |
1023 | /* Secondary threads go off to take a nap on POWER7 */ |
1024 | BEGIN_FTR_SECTION | |
371fefd6 PM |
1025 | lwz r0,VCPU_PTID(r3) |
1026 | cmpwi r0,0 | |
1027 | bne secondary_nap | |
9e368f29 | 1028 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
371fefd6 | 1029 | |
de56a948 PM |
1030 | /* |
1031 | * Reload DEC. HDEC interrupts were disabled when | |
1032 | * we reloaded the host's LPCR value. | |
1033 | */ | |
1034 | ld r3, HSTATE_DECEXP(r13) | |
1035 | mftb r4 | |
1036 | subf r4, r4, r3 | |
1037 | mtspr SPRN_DEC, r4 | |
1038 | ||
1039 | /* Reload the host's PMU registers */ | |
1040 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
1041 | lbz r4, LPPACA_PMCINUSE(r3) | |
1042 | cmpwi r4, 0 | |
1043 | beq 23f /* skip if not */ | |
1044 | lwz r3, HSTATE_PMC(r13) | |
1045 | lwz r4, HSTATE_PMC + 4(r13) | |
1046 | lwz r5, HSTATE_PMC + 8(r13) | |
1047 | lwz r6, HSTATE_PMC + 12(r13) | |
1048 | lwz r8, HSTATE_PMC + 16(r13) | |
1049 | lwz r9, HSTATE_PMC + 20(r13) | |
9e368f29 PM |
1050 | BEGIN_FTR_SECTION |
1051 | lwz r10, HSTATE_PMC + 24(r13) | |
1052 | lwz r11, HSTATE_PMC + 28(r13) | |
1053 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1054 | mtspr SPRN_PMC1, r3 |
1055 | mtspr SPRN_PMC2, r4 | |
1056 | mtspr SPRN_PMC3, r5 | |
1057 | mtspr SPRN_PMC4, r6 | |
1058 | mtspr SPRN_PMC5, r8 | |
1059 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
1060 | BEGIN_FTR_SECTION |
1061 | mtspr SPRN_PMC7, r10 | |
1062 | mtspr SPRN_PMC8, r11 | |
1063 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1064 | ld r3, HSTATE_MMCR(r13) |
1065 | ld r4, HSTATE_MMCR + 8(r13) | |
1066 | ld r5, HSTATE_MMCR + 16(r13) | |
1067 | mtspr SPRN_MMCR1, r4 | |
1068 | mtspr SPRN_MMCRA, r5 | |
1069 | mtspr SPRN_MMCR0, r3 | |
1070 | isync | |
1071 | 23: | |
1072 | /* | |
1073 | * For external and machine check interrupts, we need | |
1074 | * to call the Linux handler to process the interrupt. | |
1075 | * We do that by jumping to the interrupt vector address | |
1076 | * which we have in r12. The [h]rfid at the end of the | |
1077 | * handler will return to the book3s_hv_interrupts.S code. | |
1078 | * For other interrupts we do the rfid to get back | |
1079 | * to the book3s_interrupts.S code here. | |
1080 | */ | |
1081 | ld r8, HSTATE_VMHANDLER(r13) | |
1082 | ld r7, HSTATE_HOST_MSR(r13) | |
1083 | ||
1084 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1085 | beq 11f | |
1086 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1087 | ||
1088 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
9e368f29 | 1089 | 12: mfmsr r6 |
de56a948 PM |
1090 | mtctr r12 |
1091 | li r0, MSR_RI | |
1092 | andc r6, r6, r0 | |
1093 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
1094 | mtsrr0 r8 | |
1095 | mtsrr1 r7 | |
1096 | beqctr | |
1097 | RFI | |
1098 | ||
9e368f29 PM |
1099 | 11: |
1100 | BEGIN_FTR_SECTION | |
1101 | b 12b | |
1102 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
1103 | mtspr SPRN_HSRR0, r8 | |
de56a948 PM |
1104 | mtspr SPRN_HSRR1, r7 |
1105 | ba 0x500 | |
1106 | ||
697d3899 PM |
1107 | /* |
1108 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1109 | * If it is an HPTE not found fault that is due to the guest accessing | |
1110 | * a page that they have mapped but which we have paged out, then | |
1111 | * we continue on with the guest exit path. In all other cases, | |
1112 | * reflect the HDSI to the guest as a DSI. | |
1113 | */ | |
1114 | kvmppc_hdsi: | |
1115 | mfspr r4, SPRN_HDAR | |
1116 | mfspr r6, SPRN_HDSISR | |
1117 | /* HPTE not found fault? */ | |
1118 | andis. r0, r6, DSISR_NOHPTE@h | |
1119 | beq 1f /* if not, send it to the guest */ | |
1120 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1121 | beq 3f | |
1122 | clrrdi r0, r4, 28 | |
1123 | PPC_SLBFEE_DOT(r5, r0) /* if so, look up SLB */ | |
1124 | bne 1f /* if no SLB entry found */ | |
1125 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1126 | stw r6, VCPU_FAULT_DSISR(r9) | |
1127 | ||
1128 | /* Search the hash table. */ | |
1129 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1130 | li r7, 1 /* data fault */ |
697d3899 PM |
1131 | bl .kvmppc_hpte_hv_fault |
1132 | ld r9, HSTATE_KVM_VCPU(r13) | |
1133 | ld r10, VCPU_PC(r9) | |
1134 | ld r11, VCPU_MSR(r9) | |
1135 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1136 | cmpdi r3, 0 /* retry the instruction */ | |
1137 | beq 6f | |
1138 | cmpdi r3, -1 /* handle in kernel mode */ | |
1139 | beq nohpte_cont | |
1140 | cmpdi r3, -2 /* MMIO emulation; need instr word */ | |
1141 | beq 2f | |
1142 | ||
1143 | /* Synthesize a DSI for the guest */ | |
1144 | ld r4, VCPU_FAULT_DAR(r9) | |
1145 | mr r6, r3 | |
1146 | 1: mtspr SPRN_DAR, r4 | |
1147 | mtspr SPRN_DSISR, r6 | |
1148 | mtspr SPRN_SRR0, r10 | |
1149 | mtspr SPRN_SRR1, r11 | |
1150 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
1151 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1152 | rotldi r11, r11, 63 | |
1153 | 6: ld r7, VCPU_CTR(r9) | |
1154 | lwz r8, VCPU_XER(r9) | |
1155 | mtctr r7 | |
1156 | mtxer r8 | |
1157 | mr r4, r9 | |
1158 | b fast_guest_return | |
1159 | ||
1160 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1161 | ld r5, KVM_VRMA_SLB_V(r5) | |
1162 | b 4b | |
1163 | ||
1164 | /* If this is for emulated MMIO, load the instruction word */ | |
1165 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1166 | ||
1167 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1168 | * we'll just continue at the next IP. */ | |
1169 | li r0, KVM_GUEST_MODE_SKIP | |
1170 | stb r0, HSTATE_IN_GUEST(r13) | |
1171 | ||
1172 | /* Do the access with MSR:DR enabled */ | |
1173 | mfmsr r3 | |
1174 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1175 | mtmsrd r4 | |
1176 | lwz r8, 0(r10) | |
1177 | mtmsrd r3 | |
1178 | ||
1179 | /* Store the result */ | |
1180 | stw r8, VCPU_LAST_INST(r9) | |
1181 | ||
1182 | /* Unset guest mode. */ | |
1183 | li r0, KVM_GUEST_MODE_NONE | |
1184 | stb r0, HSTATE_IN_GUEST(r13) | |
1185 | b nohpte_cont | |
de56a948 | 1186 | |
342d3db7 PM |
1187 | /* |
1188 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1189 | * it is an HPTE not found fault for a page that we have paged out. | |
1190 | */ | |
1191 | kvmppc_hisi: | |
1192 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1193 | beq 1f | |
1194 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1195 | beq 3f | |
1196 | clrrdi r0, r10, 28 | |
1197 | PPC_SLBFEE_DOT(r5, r0) /* if so, look up SLB */ | |
1198 | bne 1f /* if no SLB entry found */ | |
1199 | 4: | |
1200 | /* Search the hash table. */ | |
1201 | mr r3, r9 /* vcpu pointer */ | |
1202 | mr r4, r10 | |
1203 | mr r6, r11 | |
1204 | li r7, 0 /* instruction fault */ | |
1205 | bl .kvmppc_hpte_hv_fault | |
1206 | ld r9, HSTATE_KVM_VCPU(r13) | |
1207 | ld r10, VCPU_PC(r9) | |
1208 | ld r11, VCPU_MSR(r9) | |
1209 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1210 | cmpdi r3, 0 /* retry the instruction */ | |
1211 | beq 6f | |
1212 | cmpdi r3, -1 /* handle in kernel mode */ | |
1213 | beq nohpte_cont | |
1214 | ||
1215 | /* Synthesize an ISI for the guest */ | |
1216 | mr r11, r3 | |
1217 | 1: mtspr SPRN_SRR0, r10 | |
1218 | mtspr SPRN_SRR1, r11 | |
1219 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
1220 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1221 | rotldi r11, r11, 63 | |
1222 | 6: ld r7, VCPU_CTR(r9) | |
1223 | lwz r8, VCPU_XER(r9) | |
1224 | mtctr r7 | |
1225 | mtxer r8 | |
1226 | mr r4, r9 | |
1227 | b fast_guest_return | |
1228 | ||
1229 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1230 | ld r5, KVM_VRMA_SLB_V(r6) | |
1231 | b 4b | |
1232 | ||
a8606e20 PM |
1233 | /* |
1234 | * Try to handle an hcall in real mode. | |
1235 | * Returns to the guest if we handle it, or continues on up to | |
1236 | * the kernel if we can't (i.e. if we don't have a handler for | |
1237 | * it, or if the handler returns H_TOO_HARD). | |
1238 | */ | |
1239 | .globl hcall_try_real_mode | |
1240 | hcall_try_real_mode: | |
1241 | ld r3,VCPU_GPR(r3)(r9) | |
1242 | andi. r0,r11,MSR_PR | |
1243 | bne hcall_real_cont | |
1244 | clrrdi r3,r3,2 | |
1245 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
1246 | bge hcall_real_cont | |
1247 | LOAD_REG_ADDR(r4, hcall_real_table) | |
1248 | lwzx r3,r3,r4 | |
1249 | cmpwi r3,0 | |
1250 | beq hcall_real_cont | |
1251 | add r3,r3,r4 | |
1252 | mtctr r3 | |
1253 | mr r3,r9 /* get vcpu pointer */ | |
1254 | ld r4,VCPU_GPR(r4)(r9) | |
1255 | bctrl | |
1256 | cmpdi r3,H_TOO_HARD | |
1257 | beq hcall_real_fallback | |
1258 | ld r4,HSTATE_KVM_VCPU(r13) | |
1259 | std r3,VCPU_GPR(r3)(r4) | |
1260 | ld r10,VCPU_PC(r4) | |
1261 | ld r11,VCPU_MSR(r4) | |
1262 | b fast_guest_return | |
1263 | ||
1264 | /* We've attempted a real mode hcall, but it's punted it back | |
1265 | * to userspace. We need to restore some clobbered volatiles | |
1266 | * before resuming the pass-it-to-qemu path */ | |
1267 | hcall_real_fallback: | |
1268 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1269 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 PM |
1270 | |
1271 | b hcall_real_cont | |
1272 | ||
1273 | .globl hcall_real_table | |
1274 | hcall_real_table: | |
1275 | .long 0 /* 0 - unused */ | |
1276 | .long .kvmppc_h_remove - hcall_real_table | |
1277 | .long .kvmppc_h_enter - hcall_real_table | |
1278 | .long .kvmppc_h_read - hcall_real_table | |
1279 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1280 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1281 | .long .kvmppc_h_protect - hcall_real_table | |
1282 | .long 0 /* 0x1c - H_GET_TCE */ | |
54738c09 | 1283 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1284 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1285 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1286 | .long 0 /* 0x2c */ | |
1287 | .long 0 /* 0x30 */ | |
1288 | .long 0 /* 0x34 */ | |
1289 | .long 0 /* 0x38 */ | |
1290 | .long 0 /* 0x3c */ | |
1291 | .long 0 /* 0x40 */ | |
1292 | .long 0 /* 0x44 */ | |
1293 | .long 0 /* 0x48 */ | |
1294 | .long 0 /* 0x4c */ | |
1295 | .long 0 /* 0x50 */ | |
1296 | .long 0 /* 0x54 */ | |
1297 | .long 0 /* 0x58 */ | |
1298 | .long 0 /* 0x5c */ | |
1299 | .long 0 /* 0x60 */ | |
1300 | .long 0 /* 0x64 */ | |
1301 | .long 0 /* 0x68 */ | |
1302 | .long 0 /* 0x6c */ | |
1303 | .long 0 /* 0x70 */ | |
1304 | .long 0 /* 0x74 */ | |
1305 | .long 0 /* 0x78 */ | |
1306 | .long 0 /* 0x7c */ | |
1307 | .long 0 /* 0x80 */ | |
1308 | .long 0 /* 0x84 */ | |
1309 | .long 0 /* 0x88 */ | |
1310 | .long 0 /* 0x8c */ | |
1311 | .long 0 /* 0x90 */ | |
1312 | .long 0 /* 0x94 */ | |
1313 | .long 0 /* 0x98 */ | |
1314 | .long 0 /* 0x9c */ | |
1315 | .long 0 /* 0xa0 */ | |
1316 | .long 0 /* 0xa4 */ | |
1317 | .long 0 /* 0xa8 */ | |
1318 | .long 0 /* 0xac */ | |
1319 | .long 0 /* 0xb0 */ | |
1320 | .long 0 /* 0xb4 */ | |
1321 | .long 0 /* 0xb8 */ | |
1322 | .long 0 /* 0xbc */ | |
1323 | .long 0 /* 0xc0 */ | |
1324 | .long 0 /* 0xc4 */ | |
1325 | .long 0 /* 0xc8 */ | |
1326 | .long 0 /* 0xcc */ | |
1327 | .long 0 /* 0xd0 */ | |
1328 | .long 0 /* 0xd4 */ | |
1329 | .long 0 /* 0xd8 */ | |
1330 | .long 0 /* 0xdc */ | |
19ccb76a | 1331 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
1332 | .long 0 /* 0xe4 */ |
1333 | .long 0 /* 0xe8 */ | |
1334 | .long 0 /* 0xec */ | |
1335 | .long 0 /* 0xf0 */ | |
1336 | .long 0 /* 0xf4 */ | |
1337 | .long 0 /* 0xf8 */ | |
1338 | .long 0 /* 0xfc */ | |
1339 | .long 0 /* 0x100 */ | |
1340 | .long 0 /* 0x104 */ | |
1341 | .long 0 /* 0x108 */ | |
1342 | .long 0 /* 0x10c */ | |
1343 | .long 0 /* 0x110 */ | |
1344 | .long 0 /* 0x114 */ | |
1345 | .long 0 /* 0x118 */ | |
1346 | .long 0 /* 0x11c */ | |
1347 | .long 0 /* 0x120 */ | |
1348 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
1349 | hcall_real_table_end: | |
1350 | ||
de56a948 PM |
1351 | ignore_hdec: |
1352 | mr r4,r9 | |
1353 | b fast_guest_return | |
1354 | ||
1355 | bounce_ext_interrupt: | |
1356 | mr r4,r9 | |
1357 | mtspr SPRN_SRR0,r10 | |
1358 | mtspr SPRN_SRR1,r11 | |
1359 | li r10,BOOK3S_INTERRUPT_EXTERNAL | |
19ccb76a PM |
1360 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ |
1361 | rotldi r11,r11,63 | |
de56a948 PM |
1362 | b fast_guest_return |
1363 | ||
a8606e20 PM |
1364 | _GLOBAL(kvmppc_h_set_dabr) |
1365 | std r4,VCPU_DABR(r3) | |
1366 | mtspr SPRN_DABR,r4 | |
1367 | li r3,0 | |
1368 | blr | |
1369 | ||
19ccb76a PM |
1370 | _GLOBAL(kvmppc_h_cede) |
1371 | ori r11,r11,MSR_EE | |
1372 | std r11,VCPU_MSR(r3) | |
1373 | li r0,1 | |
1374 | stb r0,VCPU_CEDED(r3) | |
1375 | sync /* order setting ceded vs. testing prodded */ | |
1376 | lbz r5,VCPU_PRODDED(r3) | |
1377 | cmpwi r5,0 | |
1378 | bne 1f | |
1379 | li r0,0 /* set trap to 0 to say hcall is handled */ | |
1380 | stw r0,VCPU_TRAP(r3) | |
1381 | li r0,H_SUCCESS | |
1382 | std r0,VCPU_GPR(r3)(r3) | |
1383 | BEGIN_FTR_SECTION | |
1384 | b 2f /* just send it up to host on 970 */ | |
1385 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |
1386 | ||
1387 | /* | |
1388 | * Set our bit in the bitmask of napping threads unless all the | |
1389 | * other threads are already napping, in which case we send this | |
1390 | * up to the host. | |
1391 | */ | |
1392 | ld r5,HSTATE_KVM_VCORE(r13) | |
1393 | lwz r6,VCPU_PTID(r3) | |
1394 | lwz r8,VCORE_ENTRY_EXIT(r5) | |
1395 | clrldi r8,r8,56 | |
1396 | li r0,1 | |
1397 | sld r0,r0,r6 | |
1398 | addi r6,r5,VCORE_NAPPING_THREADS | |
1399 | 31: lwarx r4,0,r6 | |
1400 | or r4,r4,r0 | |
ad61d64e | 1401 | PPC_POPCNTW(r7,r4) |
19ccb76a PM |
1402 | cmpw r7,r8 |
1403 | bge 2f | |
1404 | stwcx. r4,0,r6 | |
1405 | bne 31b | |
1406 | li r0,1 | |
1407 | stb r0,HSTATE_NAPPING(r13) | |
1408 | /* order napping_threads update vs testing entry_exit_count */ | |
1409 | lwsync | |
1410 | mr r4,r3 | |
1411 | lwz r7,VCORE_ENTRY_EXIT(r5) | |
1412 | cmpwi r7,0x100 | |
1413 | bge 33f /* another thread already exiting */ | |
1414 | ||
1415 | /* | |
1416 | * Although not specifically required by the architecture, POWER7 | |
1417 | * preserves the following registers in nap mode, even if an SMT mode | |
1418 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
1419 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
1420 | */ | |
1421 | /* Save non-volatile GPRs */ | |
1422 | std r14, VCPU_GPR(r14)(r3) | |
1423 | std r15, VCPU_GPR(r15)(r3) | |
1424 | std r16, VCPU_GPR(r16)(r3) | |
1425 | std r17, VCPU_GPR(r17)(r3) | |
1426 | std r18, VCPU_GPR(r18)(r3) | |
1427 | std r19, VCPU_GPR(r19)(r3) | |
1428 | std r20, VCPU_GPR(r20)(r3) | |
1429 | std r21, VCPU_GPR(r21)(r3) | |
1430 | std r22, VCPU_GPR(r22)(r3) | |
1431 | std r23, VCPU_GPR(r23)(r3) | |
1432 | std r24, VCPU_GPR(r24)(r3) | |
1433 | std r25, VCPU_GPR(r25)(r3) | |
1434 | std r26, VCPU_GPR(r26)(r3) | |
1435 | std r27, VCPU_GPR(r27)(r3) | |
1436 | std r28, VCPU_GPR(r28)(r3) | |
1437 | std r29, VCPU_GPR(r29)(r3) | |
1438 | std r30, VCPU_GPR(r30)(r3) | |
1439 | std r31, VCPU_GPR(r31)(r3) | |
1440 | ||
1441 | /* save FP state */ | |
1442 | bl .kvmppc_save_fp | |
1443 | ||
1444 | /* | |
1445 | * Take a nap until a decrementer or external interrupt occurs, | |
1446 | * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR | |
1447 | */ | |
1448 | li r0,0x80 | |
1449 | stb r0,PACAPROCSTART(r13) | |
1450 | mfspr r5,SPRN_LPCR | |
1451 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
1452 | mtspr SPRN_LPCR,r5 | |
1453 | isync | |
1454 | li r0, 0 | |
1455 | std r0, HSTATE_SCRATCH0(r13) | |
1456 | ptesync | |
1457 | ld r0, HSTATE_SCRATCH0(r13) | |
1458 | 1: cmpd r0, r0 | |
1459 | bne 1b | |
1460 | nap | |
1461 | b . | |
1462 | ||
1463 | kvm_end_cede: | |
1464 | /* Woken by external or decrementer interrupt */ | |
1465 | ld r1, HSTATE_HOST_R1(r13) | |
1466 | ld r2, PACATOC(r13) | |
1467 | ||
1468 | /* If we're a secondary thread and we got here by an IPI, ack it */ | |
1469 | ld r4,HSTATE_KVM_VCPU(r13) | |
1470 | lwz r3,VCPU_PTID(r4) | |
1471 | cmpwi r3,0 | |
1472 | beq 27f | |
1473 | mfspr r3,SPRN_SRR1 | |
1474 | rlwinm r3,r3,44-31,0x7 /* extract wake reason field */ | |
1475 | cmpwi r3,4 /* was it an external interrupt? */ | |
1476 | bne 27f | |
1477 | ld r5, HSTATE_XICS_PHYS(r13) | |
1478 | li r0,0xff | |
1479 | li r6,XICS_QIRR | |
1480 | li r7,XICS_XIRR | |
1481 | lwzcix r8,r5,r7 /* ack the interrupt */ | |
1482 | sync | |
1483 | stbcix r0,r5,r6 /* clear it */ | |
1484 | stwcix r8,r5,r7 /* EOI it */ | |
1485 | 27: | |
1486 | /* load up FP state */ | |
1487 | bl kvmppc_load_fp | |
1488 | ||
1489 | /* Load NV GPRS */ | |
1490 | ld r14, VCPU_GPR(r14)(r4) | |
1491 | ld r15, VCPU_GPR(r15)(r4) | |
1492 | ld r16, VCPU_GPR(r16)(r4) | |
1493 | ld r17, VCPU_GPR(r17)(r4) | |
1494 | ld r18, VCPU_GPR(r18)(r4) | |
1495 | ld r19, VCPU_GPR(r19)(r4) | |
1496 | ld r20, VCPU_GPR(r20)(r4) | |
1497 | ld r21, VCPU_GPR(r21)(r4) | |
1498 | ld r22, VCPU_GPR(r22)(r4) | |
1499 | ld r23, VCPU_GPR(r23)(r4) | |
1500 | ld r24, VCPU_GPR(r24)(r4) | |
1501 | ld r25, VCPU_GPR(r25)(r4) | |
1502 | ld r26, VCPU_GPR(r26)(r4) | |
1503 | ld r27, VCPU_GPR(r27)(r4) | |
1504 | ld r28, VCPU_GPR(r28)(r4) | |
1505 | ld r29, VCPU_GPR(r29)(r4) | |
1506 | ld r30, VCPU_GPR(r30)(r4) | |
1507 | ld r31, VCPU_GPR(r31)(r4) | |
1508 | ||
1509 | /* clear our bit in vcore->napping_threads */ | |
1510 | 33: ld r5,HSTATE_KVM_VCORE(r13) | |
1511 | lwz r3,VCPU_PTID(r4) | |
1512 | li r0,1 | |
1513 | sld r0,r0,r3 | |
1514 | addi r6,r5,VCORE_NAPPING_THREADS | |
1515 | 32: lwarx r7,0,r6 | |
1516 | andc r7,r7,r0 | |
1517 | stwcx. r7,0,r6 | |
1518 | bne 32b | |
1519 | li r0,0 | |
1520 | stb r0,HSTATE_NAPPING(r13) | |
1521 | ||
1522 | /* see if any other thread is already exiting */ | |
1523 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
1524 | cmpwi r0,0x100 | |
1525 | blt kvmppc_cede_reentry /* if not go back to guest */ | |
1526 | ||
1527 | /* some threads are exiting, so go to the guest exit path */ | |
1528 | b hcall_real_fallback | |
1529 | ||
1530 | /* cede when already previously prodded case */ | |
1531 | 1: li r0,0 | |
1532 | stb r0,VCPU_PRODDED(r3) | |
1533 | sync /* order testing prodded vs. clearing ceded */ | |
1534 | stb r0,VCPU_CEDED(r3) | |
1535 | li r3,H_SUCCESS | |
1536 | blr | |
1537 | ||
1538 | /* we've ceded but we want to give control to the host */ | |
1539 | 2: li r3,H_TOO_HARD | |
1540 | blr | |
1541 | ||
371fefd6 PM |
1542 | secondary_too_late: |
1543 | ld r5,HSTATE_KVM_VCORE(r13) | |
1544 | HMT_LOW | |
1545 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1546 | cmpwi r3,0 | |
1547 | bne 13b | |
1548 | HMT_MEDIUM | |
1549 | ld r11,PACA_SLBSHADOWPTR(r13) | |
1550 | ||
1551 | .rept SLB_NUM_BOLTED | |
1552 | ld r5,SLBSHADOW_SAVEAREA(r11) | |
1553 | ld r6,SLBSHADOW_SAVEAREA+8(r11) | |
1554 | andis. r7,r5,SLB_ESID_V@h | |
1555 | beq 1f | |
1556 | slbmte r6,r5 | |
1557 | 1: addi r11,r11,16 | |
1558 | .endr | |
371fefd6 PM |
1559 | |
1560 | secondary_nap: | |
19ccb76a PM |
1561 | /* Clear any pending IPI - assume we're a secondary thread */ |
1562 | ld r5, HSTATE_XICS_PHYS(r13) | |
1563 | li r7, XICS_XIRR | |
1564 | lwzcix r3, r5, r7 /* ack any pending interrupt */ | |
1565 | rlwinm. r0, r3, 0, 0xffffff /* any pending? */ | |
1566 | beq 37f | |
1567 | sync | |
371fefd6 PM |
1568 | li r0, 0xff |
1569 | li r6, XICS_QIRR | |
19ccb76a PM |
1570 | stbcix r0, r5, r6 /* clear the IPI */ |
1571 | stwcix r3, r5, r7 /* EOI it */ | |
1572 | 37: sync | |
371fefd6 PM |
1573 | |
1574 | /* increment the nap count and then go to nap mode */ | |
1575 | ld r4, HSTATE_KVM_VCORE(r13) | |
1576 | addi r4, r4, VCORE_NAP_COUNT | |
1577 | lwsync /* make previous updates visible */ | |
1578 | 51: lwarx r3, 0, r4 | |
1579 | addi r3, r3, 1 | |
1580 | stwcx. r3, 0, r4 | |
1581 | bne 51b | |
371fefd6 | 1582 | |
19ccb76a | 1583 | li r3, LPCR_PECE0 |
371fefd6 | 1584 | mfspr r4, SPRN_LPCR |
19ccb76a | 1585 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 |
371fefd6 | 1586 | mtspr SPRN_LPCR, r4 |
19ccb76a | 1587 | isync |
371fefd6 PM |
1588 | li r0, 0 |
1589 | std r0, HSTATE_SCRATCH0(r13) | |
1590 | ptesync | |
1591 | ld r0, HSTATE_SCRATCH0(r13) | |
1592 | 1: cmpd r0, r0 | |
1593 | bne 1b | |
1594 | nap | |
1595 | b . | |
1596 | ||
de56a948 PM |
1597 | /* |
1598 | * Save away FP, VMX and VSX registers. | |
1599 | * r3 = vcpu pointer | |
a8606e20 | 1600 | */ |
de56a948 PM |
1601 | _GLOBAL(kvmppc_save_fp) |
1602 | mfmsr r9 | |
1603 | ori r8,r9,MSR_FP | |
1604 | #ifdef CONFIG_ALTIVEC | |
1605 | BEGIN_FTR_SECTION | |
1606 | oris r8,r8,MSR_VEC@h | |
1607 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1608 | #endif | |
1609 | #ifdef CONFIG_VSX | |
1610 | BEGIN_FTR_SECTION | |
1611 | oris r8,r8,MSR_VSX@h | |
1612 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1613 | #endif | |
1614 | mtmsrd r8 | |
1615 | isync | |
1616 | #ifdef CONFIG_VSX | |
1617 | BEGIN_FTR_SECTION | |
1618 | reg = 0 | |
1619 | .rept 32 | |
1620 | li r6,reg*16+VCPU_VSRS | |
2c740c58 | 1621 | STXVD2X(reg,r6,r3) |
de56a948 PM |
1622 | reg = reg + 1 |
1623 | .endr | |
1624 | FTR_SECTION_ELSE | |
1625 | #endif | |
1626 | reg = 0 | |
1627 | .rept 32 | |
1628 | stfd reg,reg*8+VCPU_FPRS(r3) | |
1629 | reg = reg + 1 | |
1630 | .endr | |
1631 | #ifdef CONFIG_VSX | |
1632 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1633 | #endif | |
1634 | mffs fr0 | |
1635 | stfd fr0,VCPU_FPSCR(r3) | |
1636 | ||
1637 | #ifdef CONFIG_ALTIVEC | |
1638 | BEGIN_FTR_SECTION | |
1639 | reg = 0 | |
1640 | .rept 32 | |
1641 | li r6,reg*16+VCPU_VRS | |
1642 | stvx reg,r6,r3 | |
1643 | reg = reg + 1 | |
1644 | .endr | |
1645 | mfvscr vr0 | |
1646 | li r6,VCPU_VSCR | |
1647 | stvx vr0,r6,r3 | |
1648 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1649 | #endif | |
1650 | mfspr r6,SPRN_VRSAVE | |
1651 | stw r6,VCPU_VRSAVE(r3) | |
1652 | mtmsrd r9 | |
1653 | isync | |
1654 | blr | |
1655 | ||
1656 | /* | |
1657 | * Load up FP, VMX and VSX registers | |
1658 | * r4 = vcpu pointer | |
1659 | */ | |
1660 | .globl kvmppc_load_fp | |
1661 | kvmppc_load_fp: | |
1662 | mfmsr r9 | |
1663 | ori r8,r9,MSR_FP | |
1664 | #ifdef CONFIG_ALTIVEC | |
1665 | BEGIN_FTR_SECTION | |
1666 | oris r8,r8,MSR_VEC@h | |
1667 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1668 | #endif | |
1669 | #ifdef CONFIG_VSX | |
1670 | BEGIN_FTR_SECTION | |
1671 | oris r8,r8,MSR_VSX@h | |
1672 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1673 | #endif | |
1674 | mtmsrd r8 | |
1675 | isync | |
1676 | lfd fr0,VCPU_FPSCR(r4) | |
1677 | MTFSF_L(fr0) | |
1678 | #ifdef CONFIG_VSX | |
1679 | BEGIN_FTR_SECTION | |
1680 | reg = 0 | |
1681 | .rept 32 | |
1682 | li r7,reg*16+VCPU_VSRS | |
2c740c58 | 1683 | LXVD2X(reg,r7,r4) |
de56a948 PM |
1684 | reg = reg + 1 |
1685 | .endr | |
1686 | FTR_SECTION_ELSE | |
1687 | #endif | |
1688 | reg = 0 | |
1689 | .rept 32 | |
1690 | lfd reg,reg*8+VCPU_FPRS(r4) | |
1691 | reg = reg + 1 | |
1692 | .endr | |
1693 | #ifdef CONFIG_VSX | |
1694 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1695 | #endif | |
1696 | ||
1697 | #ifdef CONFIG_ALTIVEC | |
1698 | BEGIN_FTR_SECTION | |
1699 | li r7,VCPU_VSCR | |
1700 | lvx vr0,r7,r4 | |
1701 | mtvscr vr0 | |
1702 | reg = 0 | |
1703 | .rept 32 | |
1704 | li r7,reg*16+VCPU_VRS | |
1705 | lvx reg,r7,r4 | |
1706 | reg = reg + 1 | |
1707 | .endr | |
1708 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1709 | #endif | |
1710 | lwz r7,VCPU_VRSAVE(r4) | |
1711 | mtspr SPRN_VRSAVE,r7 | |
1712 | blr |