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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
de56a948 PM |
31 | |
32 | /***************************************************************************** | |
33 | * * | |
34 | * Real Mode handlers that need to be in the linear mapping * | |
35 | * * | |
36 | ****************************************************************************/ | |
37 | ||
de56a948 PM |
38 | .globl kvmppc_skip_interrupt |
39 | kvmppc_skip_interrupt: | |
40 | mfspr r13,SPRN_SRR0 | |
41 | addi r13,r13,4 | |
42 | mtspr SPRN_SRR0,r13 | |
43 | GET_SCRATCH0(r13) | |
44 | rfid | |
45 | b . | |
46 | ||
47 | .globl kvmppc_skip_Hinterrupt | |
48 | kvmppc_skip_Hinterrupt: | |
49 | mfspr r13,SPRN_HSRR0 | |
50 | addi r13,r13,4 | |
51 | mtspr SPRN_HSRR0,r13 | |
52 | GET_SCRATCH0(r13) | |
53 | hrfid | |
54 | b . | |
55 | ||
56 | /* | |
19ccb76a | 57 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
58 | * Must be called with interrupts hard-disabled. |
59 | * | |
60 | * Input Registers: | |
61 | * | |
62 | * LR = return address to continue at after eventually re-enabling MMU | |
63 | */ | |
64 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
65 | mfmsr r10 | |
66 | LOAD_REG_ADDR(r5, kvmppc_hv_entry) | |
67 | li r0,MSR_RI | |
68 | andc r0,r10,r0 | |
69 | li r6,MSR_IR | MSR_DR | |
70 | andc r6,r10,r6 | |
71 | mtmsrd r0,1 /* clear RI in MSR */ | |
72 | mtsrr0 r5 | |
73 | mtsrr1 r6 | |
74 | RFI | |
75 | ||
de56a948 PM |
76 | /****************************************************************************** |
77 | * * | |
78 | * Entry code * | |
79 | * * | |
80 | *****************************************************************************/ | |
81 | ||
371fefd6 PM |
82 | #define XICS_XIRR 4 |
83 | #define XICS_QIRR 0xc | |
f0888f70 | 84 | #define XICS_IPI 2 /* interrupt source # for IPIs */ |
371fefd6 PM |
85 | |
86 | /* | |
87 | * We come in here when wakened from nap mode on a secondary hw thread. | |
88 | * Relocation is off and most register values are lost. | |
89 | * r13 points to the PACA. | |
90 | */ | |
91 | .globl kvm_start_guest | |
92 | kvm_start_guest: | |
93 | ld r1,PACAEMERGSP(r13) | |
94 | subi r1,r1,STACK_FRAME_OVERHEAD | |
19ccb76a PM |
95 | ld r2,PACATOC(r13) |
96 | ||
f0888f70 PM |
97 | li r0,KVM_HWTHREAD_IN_KVM |
98 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 99 | |
f0888f70 PM |
100 | /* NV GPR values from power7_idle() will no longer be valid */ |
101 | li r0,1 | |
102 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 103 | |
f0888f70 PM |
104 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
105 | ld r4,HSTATE_KVM_VCPU(r13) | |
106 | cmpdi cr1,r4,0 | |
107 | ||
108 | /* Check the wake reason in SRR1 to see why we got here */ | |
109 | mfspr r3,SPRN_SRR1 | |
110 | rlwinm r3,r3,44-31,0x7 /* extract wake reason field */ | |
111 | cmpwi r3,4 /* was it an external interrupt? */ | |
112 | bne 27f | |
113 | ||
114 | /* | |
115 | * External interrupt - for now assume it is an IPI, since we | |
116 | * should never get any other interrupts sent to offline threads. | |
117 | * Only do this for secondary threads. | |
118 | */ | |
119 | beq cr1,25f | |
120 | lwz r3,VCPU_PTID(r4) | |
121 | cmpwi r3,0 | |
122 | beq 27f | |
123 | 25: ld r5,HSTATE_XICS_PHYS(r13) | |
124 | li r0,0xff | |
125 | li r6,XICS_QIRR | |
126 | li r7,XICS_XIRR | |
127 | lwzcix r8,r5,r7 /* get and ack the interrupt */ | |
371fefd6 | 128 | sync |
f0888f70 PM |
129 | clrldi. r9,r8,40 /* get interrupt source ID. */ |
130 | beq 27f /* none there? */ | |
131 | cmpwi r9,XICS_IPI | |
132 | bne 26f | |
133 | stbcix r0,r5,r6 /* clear IPI */ | |
134 | 26: stwcix r8,r5,r7 /* EOI the interrupt */ | |
371fefd6 | 135 | |
f0888f70 PM |
136 | 27: /* XXX should handle hypervisor maintenance interrupts etc. here */ |
137 | ||
7b444c67 PM |
138 | /* reload vcpu pointer after clearing the IPI */ |
139 | ld r4,HSTATE_KVM_VCPU(r13) | |
140 | cmpdi r4,0 | |
f0888f70 | 141 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 142 | beq kvm_no_guest |
f0888f70 PM |
143 | |
144 | /* were we napping due to cede? */ | |
145 | lbz r0,HSTATE_NAPPING(r13) | |
146 | cmpwi r0,0 | |
147 | bne kvm_end_cede | |
2fde6d20 | 148 | |
de56a948 PM |
149 | .global kvmppc_hv_entry |
150 | kvmppc_hv_entry: | |
151 | ||
152 | /* Required state: | |
153 | * | |
154 | * R4 = vcpu pointer | |
155 | * MSR = ~IR|DR | |
156 | * R13 = PACA | |
157 | * R1 = host R1 | |
158 | * all other volatile GPRS = free | |
159 | */ | |
160 | mflr r0 | |
161 | std r0, HSTATE_VMHANDLER(r13) | |
162 | ||
8943633c PM |
163 | /* Set partition DABR */ |
164 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
165 | li r5,3 | |
166 | ld r6,VCPU_DABR(r4) | |
167 | mtspr SPRN_DABRX,r5 | |
168 | mtspr SPRN_DABR,r6 | |
169 | BEGIN_FTR_SECTION | |
170 | isync | |
171 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
172 | |
173 | /* Load guest PMU registers */ | |
174 | /* R4 is live here (vcpu pointer) */ | |
175 | li r3, 1 | |
176 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
177 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
178 | isync | |
179 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ | |
180 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
181 | lwz r6, VCPU_PMC + 8(r4) | |
182 | lwz r7, VCPU_PMC + 12(r4) | |
183 | lwz r8, VCPU_PMC + 16(r4) | |
184 | lwz r9, VCPU_PMC + 20(r4) | |
9e368f29 PM |
185 | BEGIN_FTR_SECTION |
186 | lwz r10, VCPU_PMC + 24(r4) | |
187 | lwz r11, VCPU_PMC + 28(r4) | |
188 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
189 | mtspr SPRN_PMC1, r3 |
190 | mtspr SPRN_PMC2, r5 | |
191 | mtspr SPRN_PMC3, r6 | |
192 | mtspr SPRN_PMC4, r7 | |
193 | mtspr SPRN_PMC5, r8 | |
194 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
195 | BEGIN_FTR_SECTION |
196 | mtspr SPRN_PMC7, r10 | |
197 | mtspr SPRN_PMC8, r11 | |
198 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
199 | ld r3, VCPU_MMCR(r4) |
200 | ld r5, VCPU_MMCR + 8(r4) | |
201 | ld r6, VCPU_MMCR + 16(r4) | |
202 | mtspr SPRN_MMCR1, r5 | |
203 | mtspr SPRN_MMCRA, r6 | |
204 | mtspr SPRN_MMCR0, r3 | |
205 | isync | |
206 | ||
207 | /* Load up FP, VMX and VSX registers */ | |
208 | bl kvmppc_load_fp | |
209 | ||
c75df6f9 MN |
210 | ld r14, VCPU_GPR(R14)(r4) |
211 | ld r15, VCPU_GPR(R15)(r4) | |
212 | ld r16, VCPU_GPR(R16)(r4) | |
213 | ld r17, VCPU_GPR(R17)(r4) | |
214 | ld r18, VCPU_GPR(R18)(r4) | |
215 | ld r19, VCPU_GPR(R19)(r4) | |
216 | ld r20, VCPU_GPR(R20)(r4) | |
217 | ld r21, VCPU_GPR(R21)(r4) | |
218 | ld r22, VCPU_GPR(R22)(r4) | |
219 | ld r23, VCPU_GPR(R23)(r4) | |
220 | ld r24, VCPU_GPR(R24)(r4) | |
221 | ld r25, VCPU_GPR(R25)(r4) | |
222 | ld r26, VCPU_GPR(R26)(r4) | |
223 | ld r27, VCPU_GPR(R27)(r4) | |
224 | ld r28, VCPU_GPR(R28)(r4) | |
225 | ld r29, VCPU_GPR(R29)(r4) | |
226 | ld r30, VCPU_GPR(R30)(r4) | |
227 | ld r31, VCPU_GPR(R31)(r4) | |
8943633c | 228 | |
9e368f29 | 229 | BEGIN_FTR_SECTION |
de56a948 PM |
230 | /* Switch DSCR to guest value */ |
231 | ld r5, VCPU_DSCR(r4) | |
232 | mtspr SPRN_DSCR, r5 | |
9e368f29 | 233 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
234 | |
235 | /* | |
236 | * Set the decrementer to the guest decrementer. | |
237 | */ | |
238 | ld r8,VCPU_DEC_EXPIRES(r4) | |
239 | mftb r7 | |
240 | subf r3,r7,r8 | |
241 | mtspr SPRN_DEC,r3 | |
242 | stw r3,VCPU_DEC(r4) | |
243 | ||
244 | ld r5, VCPU_SPRG0(r4) | |
245 | ld r6, VCPU_SPRG1(r4) | |
246 | ld r7, VCPU_SPRG2(r4) | |
247 | ld r8, VCPU_SPRG3(r4) | |
248 | mtspr SPRN_SPRG0, r5 | |
249 | mtspr SPRN_SPRG1, r6 | |
250 | mtspr SPRN_SPRG2, r7 | |
251 | mtspr SPRN_SPRG3, r8 | |
252 | ||
253 | /* Save R1 in the PACA */ | |
254 | std r1, HSTATE_HOST_R1(r13) | |
255 | ||
a8606e20 PM |
256 | /* Increment yield count if they have a VPA */ |
257 | ld r3, VCPU_VPA(r4) | |
258 | cmpdi r3, 0 | |
259 | beq 25f | |
260 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
261 | addi r5, r5, 1 | |
262 | stw r5, LPPACA_YIELDCOUNT(r3) | |
c35635ef PM |
263 | li r6, 1 |
264 | stb r6, VCPU_VPA_DIRTY(r4) | |
a8606e20 | 265 | 25: |
de56a948 PM |
266 | /* Load up DAR and DSISR */ |
267 | ld r5, VCPU_DAR(r4) | |
268 | lwz r6, VCPU_DSISR(r4) | |
269 | mtspr SPRN_DAR, r5 | |
270 | mtspr SPRN_DSISR, r6 | |
271 | ||
9e368f29 | 272 | BEGIN_FTR_SECTION |
de56a948 PM |
273 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
274 | ld r5,VCPU_AMR(r4) | |
275 | ld r6,VCPU_UAMOR(r4) | |
276 | li r7,-1 | |
277 | mtspr SPRN_AMR,r5 | |
278 | mtspr SPRN_UAMOR,r6 | |
279 | mtspr SPRN_AMOR,r7 | |
9e368f29 | 280 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
281 | |
282 | /* Clear out SLB */ | |
283 | li r6,0 | |
284 | slbmte r6,r6 | |
285 | slbia | |
286 | ptesync | |
287 | ||
9e368f29 PM |
288 | BEGIN_FTR_SECTION |
289 | b 30f | |
290 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
291 | /* | |
292 | * POWER7 host -> guest partition switch code. | |
293 | * We don't have to lock against concurrent tlbies, | |
294 | * but we do have to coordinate across hardware threads. | |
295 | */ | |
371fefd6 PM |
296 | /* Increment entry count iff exit count is zero. */ |
297 | ld r5,HSTATE_KVM_VCORE(r13) | |
298 | addi r9,r5,VCORE_ENTRY_EXIT | |
299 | 21: lwarx r3,0,r9 | |
300 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
301 | bge secondary_too_late /* if so we're too late to the party */ | |
302 | addi r3,r3,1 | |
303 | stwcx. r3,0,r9 | |
304 | bne 21b | |
305 | ||
306 | /* Primary thread switches to guest partition. */ | |
aa04b4cc | 307 | ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ |
371fefd6 PM |
308 | lwz r6,VCPU_PTID(r4) |
309 | cmpwi r6,0 | |
310 | bne 20f | |
de56a948 PM |
311 | ld r6,KVM_SDR1(r9) |
312 | lwz r7,KVM_LPID(r9) | |
313 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
314 | mtspr SPRN_LPID,r0 | |
315 | ptesync | |
316 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
317 | mtspr SPRN_LPID,r7 | |
318 | isync | |
1b400ba0 PM |
319 | |
320 | /* See if we need to flush the TLB */ | |
321 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
322 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
323 | srdi r6,r6,6 /* doubleword number */ | |
324 | sldi r6,r6,3 /* address offset */ | |
325 | add r6,r6,r9 | |
326 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 327 | li r0,1 |
1b400ba0 PM |
328 | sld r0,r0,r7 |
329 | ld r7,0(r6) | |
330 | and. r7,r7,r0 | |
331 | beq 22f | |
332 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
333 | andc r7,r7,r0 | |
334 | stdcx. r7,0,r6 | |
335 | bne 23b | |
336 | li r6,128 /* and flush the TLB */ | |
337 | mtctr r6 | |
338 | li r7,0x800 /* IS field = 0b10 */ | |
339 | ptesync | |
340 | 28: tlbiel r7 | |
341 | addi r7,r7,0x1000 | |
342 | bdnz 28b | |
343 | ptesync | |
344 | ||
345 | 22: li r0,1 | |
371fefd6 PM |
346 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
347 | b 10f | |
348 | ||
349 | /* Secondary threads wait for primary to have done partition switch */ | |
350 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
351 | cmpwi r0,0 | |
352 | beq 20b | |
aa04b4cc | 353 | |
19ccb76a | 354 | /* Set LPCR and RMOR. */ |
aa04b4cc | 355 | 10: ld r8,KVM_LPCR(r9) |
19ccb76a | 356 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
357 | ld r8,KVM_RMOR(r9) |
358 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
359 | isync |
360 | ||
361 | /* Check if HDEC expires soon */ | |
362 | mfspr r3,SPRN_HDEC | |
363 | cmpwi r3,10 | |
364 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
365 | mr r9,r4 | |
366 | blt hdec_soon | |
367 | ||
de56a948 PM |
368 | /* Save purr/spurr */ |
369 | mfspr r5,SPRN_PURR | |
370 | mfspr r6,SPRN_SPURR | |
371 | std r5,HSTATE_PURR(r13) | |
372 | std r6,HSTATE_SPURR(r13) | |
373 | ld r7,VCPU_PURR(r4) | |
374 | ld r8,VCPU_SPURR(r4) | |
375 | mtspr SPRN_PURR,r7 | |
376 | mtspr SPRN_SPURR,r8 | |
9e368f29 PM |
377 | b 31f |
378 | ||
379 | /* | |
380 | * PPC970 host -> guest partition switch code. | |
381 | * We have to lock against concurrent tlbies, | |
382 | * using native_tlbie_lock to lock against host tlbies | |
383 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
384 | * We also have to invalidate the TLB since its | |
385 | * entries aren't tagged with the LPID. | |
386 | */ | |
387 | 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ | |
388 | ||
389 | /* first take native_tlbie_lock */ | |
390 | .section ".toc","aw" | |
391 | toc_tlbie_lock: | |
392 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
393 | .previous | |
394 | ld r3,toc_tlbie_lock@toc(2) | |
395 | lwz r8,PACA_LOCK_TOKEN(r13) | |
396 | 24: lwarx r0,0,r3 | |
397 | cmpwi r0,0 | |
398 | bne 24b | |
399 | stwcx. r8,0,r3 | |
400 | bne 24b | |
401 | isync | |
402 | ||
403 | ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */ | |
404 | li r0,0x18f | |
405 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
406 | or r0,r7,r0 | |
407 | ptesync | |
408 | sync | |
409 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
410 | isync | |
411 | li r0,0 | |
412 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
413 | ||
414 | /* invalidate the whole TLB */ | |
415 | li r0,256 | |
416 | mtctr r0 | |
417 | li r6,0 | |
418 | 25: tlbiel r6 | |
419 | addi r6,r6,0x1000 | |
420 | bdnz 25b | |
421 | ptesync | |
422 | ||
423 | /* Take the guest's tlbie_lock */ | |
424 | addi r3,r9,KVM_TLBIE_LOCK | |
425 | 24: lwarx r0,0,r3 | |
426 | cmpwi r0,0 | |
427 | bne 24b | |
428 | stwcx. r8,0,r3 | |
429 | bne 24b | |
430 | isync | |
431 | ld r6,KVM_SDR1(r9) | |
432 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
433 | ||
434 | /* Set up HID4 with the guest's LPID etc. */ | |
435 | sync | |
436 | mtspr SPRN_HID4,r7 | |
437 | isync | |
438 | ||
439 | /* drop the guest's tlbie_lock */ | |
440 | li r0,0 | |
441 | stw r0,0(r3) | |
442 | ||
443 | /* Check if HDEC expires soon */ | |
444 | mfspr r3,SPRN_HDEC | |
445 | cmpwi r3,10 | |
446 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
447 | mr r9,r4 | |
448 | blt hdec_soon | |
449 | ||
450 | /* Enable HDEC interrupts */ | |
451 | mfspr r0,SPRN_HID0 | |
452 | li r3,1 | |
453 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
454 | sync | |
455 | mtspr SPRN_HID0,r0 | |
456 | mfspr r0,SPRN_HID0 | |
457 | mfspr r0,SPRN_HID0 | |
458 | mfspr r0,SPRN_HID0 | |
459 | mfspr r0,SPRN_HID0 | |
460 | mfspr r0,SPRN_HID0 | |
461 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
462 | |
463 | /* Load up guest SLB entries */ | |
9e368f29 | 464 | 31: lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
465 | cmpwi r5,0 |
466 | beq 9f | |
467 | mtctr r5 | |
468 | addi r6,r4,VCPU_SLB | |
469 | 1: ld r8,VCPU_SLB_E(r6) | |
470 | ld r9,VCPU_SLB_V(r6) | |
471 | slbmte r9,r8 | |
472 | addi r6,r6,VCPU_SLB_SIZE | |
473 | bdnz 1b | |
474 | 9: | |
475 | ||
476 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
477 | lwz r5,VCPU_CTRL(r4) | |
478 | andi. r5,r5,1 | |
479 | bne 4f | |
480 | mfspr r6,SPRN_CTRLF | |
481 | clrrdi r6,r6,1 | |
482 | mtspr SPRN_CTRLT,r6 | |
483 | 4: | |
484 | ld r6, VCPU_CTR(r4) | |
485 | lwz r7, VCPU_XER(r4) | |
486 | ||
487 | mtctr r6 | |
488 | mtxer r7 | |
489 | ||
19ccb76a | 490 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
de56a948 PM |
491 | ld r6, VCPU_SRR0(r4) |
492 | ld r7, VCPU_SRR1(r4) | |
de56a948 | 493 | ld r10, VCPU_PC(r4) |
19ccb76a | 494 | ld r11, VCPU_MSR(r4) /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 | 495 | |
de56a948 PM |
496 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
497 | rotldi r11, r11, 1 + MSR_HV_LG | |
498 | ori r11, r11, MSR_ME | |
499 | ||
19ccb76a PM |
500 | /* Check if we can deliver an external or decrementer interrupt now */ |
501 | ld r0,VCPU_PENDING_EXC(r4) | |
502 | li r8,(1 << BOOK3S_IRQPRIO_EXTERNAL) | |
503 | oris r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h | |
504 | and r0,r0,r8 | |
505 | cmpdi cr1,r0,0 | |
506 | andi. r0,r11,MSR_EE | |
507 | beq cr1,11f | |
508 | BEGIN_FTR_SECTION | |
509 | mfspr r8,SPRN_LPCR | |
510 | ori r8,r8,LPCR_MER | |
511 | mtspr SPRN_LPCR,r8 | |
512 | isync | |
513 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
514 | beq 5f | |
515 | li r0,BOOK3S_INTERRUPT_EXTERNAL | |
516 | 12: mr r6,r10 | |
517 | mr r10,r0 | |
518 | mr r7,r11 | |
519 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
520 | rotldi r11,r11,63 | |
521 | b 5f | |
522 | 11: beq 5f | |
523 | mfspr r0,SPRN_DEC | |
524 | cmpwi r0,0 | |
525 | li r0,BOOK3S_INTERRUPT_DECREMENTER | |
526 | blt 12b | |
527 | ||
528 | /* Move SRR0 and SRR1 into the respective regs */ | |
529 | 5: mtspr SPRN_SRR0, r6 | |
530 | mtspr SPRN_SRR1, r7 | |
531 | li r0,0 | |
532 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
533 | ||
de56a948 PM |
534 | fast_guest_return: |
535 | mtspr SPRN_HSRR0,r10 | |
536 | mtspr SPRN_HSRR1,r11 | |
537 | ||
538 | /* Activate guest mode, so faults get handled by KVM */ | |
539 | li r9, KVM_GUEST_MODE_GUEST | |
540 | stb r9, HSTATE_IN_GUEST(r13) | |
541 | ||
542 | /* Enter guest */ | |
543 | ||
0acb9111 PM |
544 | BEGIN_FTR_SECTION |
545 | ld r5, VCPU_CFAR(r4) | |
546 | mtspr SPRN_CFAR, r5 | |
547 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
548 | ||
de56a948 PM |
549 | ld r5, VCPU_LR(r4) |
550 | lwz r6, VCPU_CR(r4) | |
551 | mtlr r5 | |
552 | mtcr r6 | |
553 | ||
c75df6f9 MN |
554 | ld r0, VCPU_GPR(R0)(r4) |
555 | ld r1, VCPU_GPR(R1)(r4) | |
556 | ld r2, VCPU_GPR(R2)(r4) | |
557 | ld r3, VCPU_GPR(R3)(r4) | |
558 | ld r5, VCPU_GPR(R5)(r4) | |
559 | ld r6, VCPU_GPR(R6)(r4) | |
560 | ld r7, VCPU_GPR(R7)(r4) | |
561 | ld r8, VCPU_GPR(R8)(r4) | |
562 | ld r9, VCPU_GPR(R9)(r4) | |
563 | ld r10, VCPU_GPR(R10)(r4) | |
564 | ld r11, VCPU_GPR(R11)(r4) | |
565 | ld r12, VCPU_GPR(R12)(r4) | |
566 | ld r13, VCPU_GPR(R13)(r4) | |
567 | ||
568 | ld r4, VCPU_GPR(R4)(r4) | |
de56a948 PM |
569 | |
570 | hrfid | |
571 | b . | |
572 | ||
573 | /****************************************************************************** | |
574 | * * | |
575 | * Exit code * | |
576 | * * | |
577 | *****************************************************************************/ | |
578 | ||
579 | /* | |
580 | * We come here from the first-level interrupt handlers. | |
581 | */ | |
582 | .globl kvmppc_interrupt | |
583 | kvmppc_interrupt: | |
584 | /* | |
585 | * Register contents: | |
586 | * R12 = interrupt vector | |
587 | * R13 = PACA | |
588 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
589 | * guest R13 saved in SPRN_SCRATCH0 | |
590 | */ | |
591 | /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */ | |
592 | std r9, HSTATE_HOST_R2(r13) | |
593 | ld r9, HSTATE_KVM_VCPU(r13) | |
594 | ||
595 | /* Save registers */ | |
596 | ||
c75df6f9 MN |
597 | std r0, VCPU_GPR(R0)(r9) |
598 | std r1, VCPU_GPR(R1)(r9) | |
599 | std r2, VCPU_GPR(R2)(r9) | |
600 | std r3, VCPU_GPR(R3)(r9) | |
601 | std r4, VCPU_GPR(R4)(r9) | |
602 | std r5, VCPU_GPR(R5)(r9) | |
603 | std r6, VCPU_GPR(R6)(r9) | |
604 | std r7, VCPU_GPR(R7)(r9) | |
605 | std r8, VCPU_GPR(R8)(r9) | |
de56a948 | 606 | ld r0, HSTATE_HOST_R2(r13) |
c75df6f9 MN |
607 | std r0, VCPU_GPR(R9)(r9) |
608 | std r10, VCPU_GPR(R10)(r9) | |
609 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
610 | ld r3, HSTATE_SCRATCH0(r13) |
611 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 612 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 613 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
614 | BEGIN_FTR_SECTION |
615 | ld r3, HSTATE_CFAR(r13) | |
616 | std r3, VCPU_CFAR(r9) | |
617 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
de56a948 PM |
618 | |
619 | /* Restore R1/R2 so we can handle faults */ | |
620 | ld r1, HSTATE_HOST_R1(r13) | |
621 | ld r2, PACATOC(r13) | |
622 | ||
623 | mfspr r10, SPRN_SRR0 | |
624 | mfspr r11, SPRN_SRR1 | |
625 | std r10, VCPU_SRR0(r9) | |
626 | std r11, VCPU_SRR1(r9) | |
627 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
628 | beq 1f | |
629 | mfspr r10, SPRN_HSRR0 | |
630 | mfspr r11, SPRN_HSRR1 | |
631 | clrrdi r12, r12, 2 | |
632 | 1: std r10, VCPU_PC(r9) | |
633 | std r11, VCPU_MSR(r9) | |
634 | ||
635 | GET_SCRATCH0(r3) | |
636 | mflr r4 | |
c75df6f9 | 637 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
638 | std r4, VCPU_LR(r9) |
639 | ||
640 | /* Unset guest mode */ | |
641 | li r0, KVM_GUEST_MODE_NONE | |
642 | stb r0, HSTATE_IN_GUEST(r13) | |
643 | ||
644 | stw r12,VCPU_TRAP(r9) | |
645 | ||
697d3899 PM |
646 | /* Save HEIR (HV emulation assist reg) in last_inst |
647 | if this is an HEI (HV emulation interrupt, e40) */ | |
648 | li r3,KVM_INST_FETCH_FAILED | |
649 | BEGIN_FTR_SECTION | |
650 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
651 | bne 11f | |
652 | mfspr r3,SPRN_HEIR | |
653 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
654 | 11: stw r3,VCPU_LAST_INST(r9) | |
655 | ||
656 | /* these are volatile across C function calls */ | |
657 | mfctr r3 | |
658 | mfxer r4 | |
659 | std r3, VCPU_CTR(r9) | |
660 | stw r4, VCPU_XER(r9) | |
661 | ||
662 | BEGIN_FTR_SECTION | |
663 | /* If this is a page table miss then see if it's theirs or ours */ | |
664 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
665 | beq kvmppc_hdsi | |
342d3db7 PM |
666 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
667 | beq kvmppc_hisi | |
697d3899 PM |
668 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
669 | ||
de56a948 PM |
670 | /* See if this is a leftover HDEC interrupt */ |
671 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
672 | bne 2f | |
673 | mfspr r3,SPRN_HDEC | |
674 | cmpwi r3,0 | |
675 | bge ignore_hdec | |
676 | 2: | |
697d3899 | 677 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
678 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
679 | beq hcall_try_real_mode | |
de56a948 PM |
680 | |
681 | /* Check for mediated interrupts (could be done earlier really ...) */ | |
9e368f29 | 682 | BEGIN_FTR_SECTION |
de56a948 PM |
683 | cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL |
684 | bne+ 1f | |
de56a948 PM |
685 | andi. r0,r11,MSR_EE |
686 | beq 1f | |
19ccb76a | 687 | mfspr r5,SPRN_LPCR |
de56a948 PM |
688 | andi. r0,r5,LPCR_MER |
689 | bne bounce_ext_interrupt | |
690 | 1: | |
9e368f29 | 691 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 | 692 | |
b4072df4 | 693 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 PM |
694 | /* Save DEC */ |
695 | mfspr r5,SPRN_DEC | |
696 | mftb r6 | |
697 | extsw r5,r5 | |
698 | add r5,r5,r6 | |
699 | std r5,VCPU_DEC_EXPIRES(r9) | |
700 | ||
de56a948 | 701 | /* Save more register state */ |
de56a948 PM |
702 | mfdar r6 |
703 | mfdsisr r7 | |
de56a948 PM |
704 | std r6, VCPU_DAR(r9) |
705 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 706 | BEGIN_FTR_SECTION |
697d3899 | 707 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
708 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
709 | beq 6f | |
9e368f29 | 710 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 711 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
712 | stw r7, VCPU_FAULT_DSISR(r9) |
713 | ||
b4072df4 PM |
714 | /* See if it is a machine check */ |
715 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
716 | beq machine_check_realmode | |
717 | mc_cont: | |
718 | ||
de56a948 | 719 | /* Save guest CTRL register, set runlatch to 1 */ |
697d3899 | 720 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
721 | stw r6,VCPU_CTRL(r9) |
722 | andi. r0,r6,1 | |
723 | bne 4f | |
724 | ori r6,r6,1 | |
725 | mtspr SPRN_CTRLT,r6 | |
726 | 4: | |
727 | /* Read the guest SLB and save it away */ | |
728 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
729 | mtctr r0 | |
730 | li r6,0 | |
731 | addi r7,r9,VCPU_SLB | |
732 | li r5,0 | |
733 | 1: slbmfee r8,r6 | |
734 | andis. r0,r8,SLB_ESID_V@h | |
735 | beq 2f | |
736 | add r8,r8,r6 /* put index in */ | |
737 | slbmfev r3,r6 | |
738 | std r8,VCPU_SLB_E(r7) | |
739 | std r3,VCPU_SLB_V(r7) | |
740 | addi r7,r7,VCPU_SLB_SIZE | |
741 | addi r5,r5,1 | |
742 | 2: addi r6,r6,1 | |
743 | bdnz 1b | |
744 | stw r5,VCPU_SLB_MAX(r9) | |
745 | ||
746 | /* | |
747 | * Save the guest PURR/SPURR | |
748 | */ | |
9e368f29 | 749 | BEGIN_FTR_SECTION |
de56a948 PM |
750 | mfspr r5,SPRN_PURR |
751 | mfspr r6,SPRN_SPURR | |
752 | ld r7,VCPU_PURR(r9) | |
753 | ld r8,VCPU_SPURR(r9) | |
754 | std r5,VCPU_PURR(r9) | |
755 | std r6,VCPU_SPURR(r9) | |
756 | subf r5,r7,r5 | |
757 | subf r6,r8,r6 | |
758 | ||
759 | /* | |
760 | * Restore host PURR/SPURR and add guest times | |
761 | * so that the time in the guest gets accounted. | |
762 | */ | |
763 | ld r3,HSTATE_PURR(r13) | |
764 | ld r4,HSTATE_SPURR(r13) | |
765 | add r3,r3,r5 | |
766 | add r4,r4,r6 | |
767 | mtspr SPRN_PURR,r3 | |
768 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 769 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 PM |
770 | |
771 | /* Clear out SLB */ | |
772 | li r5,0 | |
773 | slbmte r5,r5 | |
774 | slbia | |
775 | ptesync | |
776 | ||
19ccb76a | 777 | hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */ |
9e368f29 PM |
778 | BEGIN_FTR_SECTION |
779 | b 32f | |
780 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
781 | /* | |
782 | * POWER7 guest -> host partition switch code. | |
783 | * We don't have to lock against tlbies but we do | |
784 | * have to coordinate the hardware threads. | |
785 | */ | |
371fefd6 PM |
786 | /* Increment the threads-exiting-guest count in the 0xff00 |
787 | bits of vcore->entry_exit_count */ | |
788 | lwsync | |
789 | ld r5,HSTATE_KVM_VCORE(r13) | |
790 | addi r6,r5,VCORE_ENTRY_EXIT | |
791 | 41: lwarx r3,0,r6 | |
792 | addi r0,r3,0x100 | |
793 | stwcx. r0,0,r6 | |
794 | bne 41b | |
19ccb76a | 795 | lwsync |
371fefd6 PM |
796 | |
797 | /* | |
798 | * At this point we have an interrupt that we have to pass | |
799 | * up to the kernel or qemu; we can't handle it in real mode. | |
800 | * Thus we have to do a partition switch, so we have to | |
801 | * collect the other threads, if we are the first thread | |
802 | * to take an interrupt. To do this, we set the HDEC to 0, | |
803 | * which causes an HDEC interrupt in all threads within 2ns | |
804 | * because the HDEC register is shared between all 4 threads. | |
805 | * However, we don't need to bother if this is an HDEC | |
806 | * interrupt, since the other threads will already be on their | |
807 | * way here in that case. | |
808 | */ | |
19ccb76a PM |
809 | cmpwi r3,0x100 /* Are we the first here? */ |
810 | bge 43f | |
811 | cmpwi r3,1 /* Are any other threads in the guest? */ | |
812 | ble 43f | |
371fefd6 PM |
813 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
814 | beq 40f | |
371fefd6 PM |
815 | li r0,0 |
816 | mtspr SPRN_HDEC,r0 | |
817 | 40: | |
19ccb76a PM |
818 | /* |
819 | * Send an IPI to any napping threads, since an HDEC interrupt | |
820 | * doesn't wake CPUs up from nap. | |
821 | */ | |
822 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
823 | lwz r4,VCPU_PTID(r9) | |
824 | li r0,1 | |
2f584a14 | 825 | sld r0,r0,r4 |
19ccb76a PM |
826 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
827 | beq 43f | |
828 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
829 | subf r6,r4,r13 | |
830 | 42: andi. r0,r3,1 | |
831 | beq 44f | |
832 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
833 | li r0,IPI_PRIORITY | |
834 | li r7,XICS_QIRR | |
835 | stbcix r0,r7,r8 /* trigger the IPI */ | |
836 | 44: srdi. r3,r3,1 | |
837 | addi r6,r6,PACA_SIZE | |
838 | bne 42b | |
371fefd6 PM |
839 | |
840 | /* Secondary threads wait for primary to do partition switch */ | |
19ccb76a | 841 | 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ |
371fefd6 PM |
842 | ld r5,HSTATE_KVM_VCORE(r13) |
843 | lwz r3,VCPU_PTID(r9) | |
844 | cmpwi r3,0 | |
845 | beq 15f | |
846 | HMT_LOW | |
847 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
848 | cmpwi r3,0 | |
849 | bne 13b | |
850 | HMT_MEDIUM | |
851 | b 16f | |
852 | ||
853 | /* Primary thread waits for all the secondaries to exit guest */ | |
854 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
855 | srwi r0,r3,8 | |
856 | clrldi r3,r3,56 | |
857 | cmpw r3,r0 | |
858 | bne 15b | |
859 | isync | |
860 | ||
861 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
862 | ld r6,KVM_HOST_SDR1(r4) |
863 | lwz r7,KVM_HOST_LPID(r4) | |
864 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
865 | mtspr SPRN_LPID,r8 | |
866 | ptesync | |
867 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
868 | mtspr SPRN_LPID,r7 | |
869 | isync | |
371fefd6 PM |
870 | li r0,0 |
871 | stb r0,VCORE_IN_GUEST(r5) | |
de56a948 PM |
872 | lis r8,0x7fff /* MAX_INT@h */ |
873 | mtspr SPRN_HDEC,r8 | |
874 | ||
371fefd6 | 875 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
876 | mtspr SPRN_LPCR,r8 |
877 | isync | |
9e368f29 PM |
878 | b 33f |
879 | ||
880 | /* | |
881 | * PPC970 guest -> host partition switch code. | |
882 | * We have to lock against concurrent tlbies, and | |
883 | * we have to flush the whole TLB. | |
884 | */ | |
885 | 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ | |
886 | ||
887 | /* Take the guest's tlbie_lock */ | |
888 | lwz r8,PACA_LOCK_TOKEN(r13) | |
889 | addi r3,r4,KVM_TLBIE_LOCK | |
890 | 24: lwarx r0,0,r3 | |
891 | cmpwi r0,0 | |
892 | bne 24b | |
893 | stwcx. r8,0,r3 | |
894 | bne 24b | |
895 | isync | |
896 | ||
897 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
898 | li r0,0x18f | |
899 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
900 | or r0,r7,r0 | |
901 | ptesync | |
902 | sync | |
903 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
904 | isync | |
905 | li r0,0 | |
906 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
907 | ||
908 | /* invalidate the whole TLB */ | |
909 | li r0,256 | |
910 | mtctr r0 | |
911 | li r6,0 | |
912 | 25: tlbiel r6 | |
913 | addi r6,r6,0x1000 | |
914 | bdnz 25b | |
915 | ptesync | |
916 | ||
917 | /* take native_tlbie_lock */ | |
918 | ld r3,toc_tlbie_lock@toc(2) | |
919 | 24: lwarx r0,0,r3 | |
920 | cmpwi r0,0 | |
921 | bne 24b | |
922 | stwcx. r8,0,r3 | |
923 | bne 24b | |
924 | isync | |
925 | ||
926 | ld r6,KVM_HOST_SDR1(r4) | |
927 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
928 | ||
929 | /* Set up host HID4 value */ | |
930 | sync | |
931 | mtspr SPRN_HID4,r7 | |
932 | isync | |
933 | li r0,0 | |
934 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
935 | ||
936 | lis r8,0x7fff /* MAX_INT@h */ | |
937 | mtspr SPRN_HDEC,r8 | |
938 | ||
939 | /* Disable HDEC interrupts */ | |
940 | mfspr r0,SPRN_HID0 | |
941 | li r3,0 | |
942 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
943 | sync | |
944 | mtspr SPRN_HID0,r0 | |
945 | mfspr r0,SPRN_HID0 | |
946 | mfspr r0,SPRN_HID0 | |
947 | mfspr r0,SPRN_HID0 | |
948 | mfspr r0,SPRN_HID0 | |
949 | mfspr r0,SPRN_HID0 | |
950 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
951 | |
952 | /* load host SLB entries */ | |
9e368f29 | 953 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
954 | |
955 | .rept SLB_NUM_BOLTED | |
956 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
957 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
958 | andis. r7,r5,SLB_ESID_V@h | |
959 | beq 1f | |
960 | slbmte r6,r5 | |
961 | 1: addi r8,r8,16 | |
962 | .endr | |
963 | ||
964 | /* Save and reset AMR and UAMOR before turning on the MMU */ | |
9e368f29 | 965 | BEGIN_FTR_SECTION |
de56a948 PM |
966 | mfspr r5,SPRN_AMR |
967 | mfspr r6,SPRN_UAMOR | |
968 | std r5,VCPU_AMR(r9) | |
969 | std r6,VCPU_UAMOR(r9) | |
970 | li r6,0 | |
971 | mtspr SPRN_AMR,r6 | |
9e368f29 | 972 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 | 973 | |
de56a948 | 974 | /* Switch DSCR back to host value */ |
9e368f29 | 975 | BEGIN_FTR_SECTION |
de56a948 PM |
976 | mfspr r8, SPRN_DSCR |
977 | ld r7, HSTATE_DSCR(r13) | |
978 | std r8, VCPU_DSCR(r7) | |
979 | mtspr SPRN_DSCR, r7 | |
9e368f29 | 980 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
981 | |
982 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
983 | std r14, VCPU_GPR(R14)(r9) |
984 | std r15, VCPU_GPR(R15)(r9) | |
985 | std r16, VCPU_GPR(R16)(r9) | |
986 | std r17, VCPU_GPR(R17)(r9) | |
987 | std r18, VCPU_GPR(R18)(r9) | |
988 | std r19, VCPU_GPR(R19)(r9) | |
989 | std r20, VCPU_GPR(R20)(r9) | |
990 | std r21, VCPU_GPR(R21)(r9) | |
991 | std r22, VCPU_GPR(R22)(r9) | |
992 | std r23, VCPU_GPR(R23)(r9) | |
993 | std r24, VCPU_GPR(R24)(r9) | |
994 | std r25, VCPU_GPR(R25)(r9) | |
995 | std r26, VCPU_GPR(R26)(r9) | |
996 | std r27, VCPU_GPR(R27)(r9) | |
997 | std r28, VCPU_GPR(R28)(r9) | |
998 | std r29, VCPU_GPR(R29)(r9) | |
999 | std r30, VCPU_GPR(R30)(r9) | |
1000 | std r31, VCPU_GPR(R31)(r9) | |
de56a948 PM |
1001 | |
1002 | /* Save SPRGs */ | |
1003 | mfspr r3, SPRN_SPRG0 | |
1004 | mfspr r4, SPRN_SPRG1 | |
1005 | mfspr r5, SPRN_SPRG2 | |
1006 | mfspr r6, SPRN_SPRG3 | |
1007 | std r3, VCPU_SPRG0(r9) | |
1008 | std r4, VCPU_SPRG1(r9) | |
1009 | std r5, VCPU_SPRG2(r9) | |
1010 | std r6, VCPU_SPRG3(r9) | |
1011 | ||
8943633c PM |
1012 | /* save FP state */ |
1013 | mr r3, r9 | |
1014 | bl .kvmppc_save_fp | |
1015 | ||
a8606e20 PM |
1016 | /* Increment yield count if they have a VPA */ |
1017 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1018 | cmpdi r8, 0 | |
1019 | beq 25f | |
1020 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
1021 | addi r3, r3, 1 | |
1022 | stw r3, LPPACA_YIELDCOUNT(r8) | |
c35635ef PM |
1023 | li r3, 1 |
1024 | stb r3, VCPU_VPA_DIRTY(r9) | |
a8606e20 PM |
1025 | 25: |
1026 | /* Save PMU registers if requested */ | |
1027 | /* r8 and cr0.eq are live here */ | |
de56a948 PM |
1028 | li r3, 1 |
1029 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1030 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1031 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
8943633c PM |
1032 | mfspr r6, SPRN_MMCRA |
1033 | BEGIN_FTR_SECTION | |
1034 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
1035 | li r7, 0 | |
1036 | mtspr SPRN_MMCRA, r7 | |
1037 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 | 1038 | isync |
a8606e20 PM |
1039 | beq 21f /* if no VPA, save PMU stuff anyway */ |
1040 | lbz r7, LPPACA_PMCINUSE(r8) | |
1041 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1042 | bne 21f | |
1043 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1044 | b 22f | |
1045 | 21: mfspr r5, SPRN_MMCR1 | |
de56a948 PM |
1046 | std r4, VCPU_MMCR(r9) |
1047 | std r5, VCPU_MMCR + 8(r9) | |
1048 | std r6, VCPU_MMCR + 16(r9) | |
1049 | mfspr r3, SPRN_PMC1 | |
1050 | mfspr r4, SPRN_PMC2 | |
1051 | mfspr r5, SPRN_PMC3 | |
1052 | mfspr r6, SPRN_PMC4 | |
1053 | mfspr r7, SPRN_PMC5 | |
1054 | mfspr r8, SPRN_PMC6 | |
9e368f29 PM |
1055 | BEGIN_FTR_SECTION |
1056 | mfspr r10, SPRN_PMC7 | |
1057 | mfspr r11, SPRN_PMC8 | |
1058 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1059 | stw r3, VCPU_PMC(r9) |
1060 | stw r4, VCPU_PMC + 4(r9) | |
1061 | stw r5, VCPU_PMC + 8(r9) | |
1062 | stw r6, VCPU_PMC + 12(r9) | |
1063 | stw r7, VCPU_PMC + 16(r9) | |
1064 | stw r8, VCPU_PMC + 20(r9) | |
9e368f29 PM |
1065 | BEGIN_FTR_SECTION |
1066 | stw r10, VCPU_PMC + 24(r9) | |
1067 | stw r11, VCPU_PMC + 28(r9) | |
1068 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 | 1069 | 22: |
de56a948 | 1070 | |
9e368f29 PM |
1071 | /* Secondary threads go off to take a nap on POWER7 */ |
1072 | BEGIN_FTR_SECTION | |
8943633c | 1073 | lwz r0,VCPU_PTID(r9) |
371fefd6 PM |
1074 | cmpwi r0,0 |
1075 | bne secondary_nap | |
9e368f29 | 1076 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
371fefd6 | 1077 | |
8943633c PM |
1078 | /* Restore host DABR and DABRX */ |
1079 | ld r5,HSTATE_DABR(r13) | |
1080 | li r6,7 | |
1081 | mtspr SPRN_DABR,r5 | |
1082 | mtspr SPRN_DABRX,r6 | |
1083 | ||
18ad51dd | 1084 | /* Restore SPRG3 */ |
0127262c | 1085 | ld r3,PACA_SPRG3(r13) |
18ad51dd AB |
1086 | mtspr SPRN_SPRG3,r3 |
1087 | ||
de56a948 PM |
1088 | /* |
1089 | * Reload DEC. HDEC interrupts were disabled when | |
1090 | * we reloaded the host's LPCR value. | |
1091 | */ | |
1092 | ld r3, HSTATE_DECEXP(r13) | |
1093 | mftb r4 | |
1094 | subf r4, r4, r3 | |
1095 | mtspr SPRN_DEC, r4 | |
1096 | ||
1097 | /* Reload the host's PMU registers */ | |
1098 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
1099 | lbz r4, LPPACA_PMCINUSE(r3) | |
1100 | cmpwi r4, 0 | |
1101 | beq 23f /* skip if not */ | |
1102 | lwz r3, HSTATE_PMC(r13) | |
1103 | lwz r4, HSTATE_PMC + 4(r13) | |
1104 | lwz r5, HSTATE_PMC + 8(r13) | |
1105 | lwz r6, HSTATE_PMC + 12(r13) | |
1106 | lwz r8, HSTATE_PMC + 16(r13) | |
1107 | lwz r9, HSTATE_PMC + 20(r13) | |
9e368f29 PM |
1108 | BEGIN_FTR_SECTION |
1109 | lwz r10, HSTATE_PMC + 24(r13) | |
1110 | lwz r11, HSTATE_PMC + 28(r13) | |
1111 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1112 | mtspr SPRN_PMC1, r3 |
1113 | mtspr SPRN_PMC2, r4 | |
1114 | mtspr SPRN_PMC3, r5 | |
1115 | mtspr SPRN_PMC4, r6 | |
1116 | mtspr SPRN_PMC5, r8 | |
1117 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
1118 | BEGIN_FTR_SECTION |
1119 | mtspr SPRN_PMC7, r10 | |
1120 | mtspr SPRN_PMC8, r11 | |
1121 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1122 | ld r3, HSTATE_MMCR(r13) |
1123 | ld r4, HSTATE_MMCR + 8(r13) | |
1124 | ld r5, HSTATE_MMCR + 16(r13) | |
1125 | mtspr SPRN_MMCR1, r4 | |
1126 | mtspr SPRN_MMCRA, r5 | |
1127 | mtspr SPRN_MMCR0, r3 | |
1128 | isync | |
1129 | 23: | |
1130 | /* | |
1131 | * For external and machine check interrupts, we need | |
1132 | * to call the Linux handler to process the interrupt. | |
b4072df4 PM |
1133 | * We do that by jumping to absolute address 0x500 for |
1134 | * external interrupts, or the machine_check_fwnmi label | |
1135 | * for machine checks (since firmware might have patched | |
1136 | * the vector area at 0x200). The [h]rfid at the end of the | |
de56a948 PM |
1137 | * handler will return to the book3s_hv_interrupts.S code. |
1138 | * For other interrupts we do the rfid to get back | |
b4072df4 | 1139 | * to the book3s_hv_interrupts.S code here. |
de56a948 PM |
1140 | */ |
1141 | ld r8, HSTATE_VMHANDLER(r13) | |
1142 | ld r7, HSTATE_HOST_MSR(r13) | |
1143 | ||
b4072df4 | 1144 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
de56a948 | 1145 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL |
b4072df4 | 1146 | BEGIN_FTR_SECTION |
de56a948 | 1147 | beq 11f |
b4072df4 | 1148 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
1149 | |
1150 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
b4072df4 | 1151 | mfmsr r6 |
de56a948 PM |
1152 | li r0, MSR_RI |
1153 | andc r6, r6, r0 | |
1154 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
1155 | mtsrr0 r8 | |
1156 | mtsrr1 r7 | |
b4072df4 PM |
1157 | beqa 0x500 /* external interrupt (PPC970) */ |
1158 | beq cr1, 13f /* machine check */ | |
de56a948 PM |
1159 | RFI |
1160 | ||
b4072df4 PM |
1161 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ |
1162 | 11: mtspr SPRN_HSRR0, r8 | |
de56a948 PM |
1163 | mtspr SPRN_HSRR1, r7 |
1164 | ba 0x500 | |
1165 | ||
b4072df4 PM |
1166 | 13: b machine_check_fwnmi |
1167 | ||
697d3899 PM |
1168 | /* |
1169 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1170 | * If it is an HPTE not found fault that is due to the guest accessing | |
1171 | * a page that they have mapped but which we have paged out, then | |
1172 | * we continue on with the guest exit path. In all other cases, | |
1173 | * reflect the HDSI to the guest as a DSI. | |
1174 | */ | |
1175 | kvmppc_hdsi: | |
1176 | mfspr r4, SPRN_HDAR | |
1177 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1178 | /* HPTE not found fault or protection fault? */ |
1179 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1180 | beq 1f /* if not, send it to the guest */ |
1181 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1182 | beq 3f | |
1183 | clrrdi r0, r4, 28 | |
c75df6f9 | 1184 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1185 | bne 1f /* if no SLB entry found */ |
1186 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1187 | stw r6, VCPU_FAULT_DSISR(r9) | |
1188 | ||
1189 | /* Search the hash table. */ | |
1190 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1191 | li r7, 1 /* data fault */ |
697d3899 PM |
1192 | bl .kvmppc_hpte_hv_fault |
1193 | ld r9, HSTATE_KVM_VCPU(r13) | |
1194 | ld r10, VCPU_PC(r9) | |
1195 | ld r11, VCPU_MSR(r9) | |
1196 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1197 | cmpdi r3, 0 /* retry the instruction */ | |
1198 | beq 6f | |
1199 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1200 | beq guest_exit_cont |
697d3899 PM |
1201 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1202 | beq 2f | |
1203 | ||
1204 | /* Synthesize a DSI for the guest */ | |
1205 | ld r4, VCPU_FAULT_DAR(r9) | |
1206 | mr r6, r3 | |
1207 | 1: mtspr SPRN_DAR, r4 | |
1208 | mtspr SPRN_DSISR, r6 | |
1209 | mtspr SPRN_SRR0, r10 | |
1210 | mtspr SPRN_SRR1, r11 | |
1211 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
1212 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1213 | rotldi r11, r11, 63 | |
b4072df4 | 1214 | fast_interrupt_c_return: |
697d3899 PM |
1215 | 6: ld r7, VCPU_CTR(r9) |
1216 | lwz r8, VCPU_XER(r9) | |
1217 | mtctr r7 | |
1218 | mtxer r8 | |
1219 | mr r4, r9 | |
1220 | b fast_guest_return | |
1221 | ||
1222 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1223 | ld r5, KVM_VRMA_SLB_V(r5) | |
1224 | b 4b | |
1225 | ||
1226 | /* If this is for emulated MMIO, load the instruction word */ | |
1227 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1228 | ||
1229 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1230 | * we'll just continue at the next IP. */ | |
1231 | li r0, KVM_GUEST_MODE_SKIP | |
1232 | stb r0, HSTATE_IN_GUEST(r13) | |
1233 | ||
1234 | /* Do the access with MSR:DR enabled */ | |
1235 | mfmsr r3 | |
1236 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1237 | mtmsrd r4 | |
1238 | lwz r8, 0(r10) | |
1239 | mtmsrd r3 | |
1240 | ||
1241 | /* Store the result */ | |
1242 | stw r8, VCPU_LAST_INST(r9) | |
1243 | ||
1244 | /* Unset guest mode. */ | |
1245 | li r0, KVM_GUEST_MODE_NONE | |
1246 | stb r0, HSTATE_IN_GUEST(r13) | |
b4072df4 | 1247 | b guest_exit_cont |
de56a948 | 1248 | |
342d3db7 PM |
1249 | /* |
1250 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1251 | * it is an HPTE not found fault for a page that we have paged out. | |
1252 | */ | |
1253 | kvmppc_hisi: | |
1254 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1255 | beq 1f | |
1256 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1257 | beq 3f | |
1258 | clrrdi r0, r10, 28 | |
c75df6f9 | 1259 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1260 | bne 1f /* if no SLB entry found */ |
1261 | 4: | |
1262 | /* Search the hash table. */ | |
1263 | mr r3, r9 /* vcpu pointer */ | |
1264 | mr r4, r10 | |
1265 | mr r6, r11 | |
1266 | li r7, 0 /* instruction fault */ | |
1267 | bl .kvmppc_hpte_hv_fault | |
1268 | ld r9, HSTATE_KVM_VCPU(r13) | |
1269 | ld r10, VCPU_PC(r9) | |
1270 | ld r11, VCPU_MSR(r9) | |
1271 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1272 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1273 | beq fast_interrupt_c_return |
342d3db7 | 1274 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1275 | beq guest_exit_cont |
342d3db7 PM |
1276 | |
1277 | /* Synthesize an ISI for the guest */ | |
1278 | mr r11, r3 | |
1279 | 1: mtspr SPRN_SRR0, r10 | |
1280 | mtspr SPRN_SRR1, r11 | |
1281 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
1282 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1283 | rotldi r11, r11, 63 | |
b4072df4 | 1284 | b fast_interrupt_c_return |
342d3db7 PM |
1285 | |
1286 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1287 | ld r5, KVM_VRMA_SLB_V(r6) | |
1288 | b 4b | |
1289 | ||
a8606e20 PM |
1290 | /* |
1291 | * Try to handle an hcall in real mode. | |
1292 | * Returns to the guest if we handle it, or continues on up to | |
1293 | * the kernel if we can't (i.e. if we don't have a handler for | |
1294 | * it, or if the handler returns H_TOO_HARD). | |
1295 | */ | |
1296 | .globl hcall_try_real_mode | |
1297 | hcall_try_real_mode: | |
c75df6f9 | 1298 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1299 | andi. r0,r11,MSR_PR |
b4072df4 | 1300 | bne guest_exit_cont |
a8606e20 PM |
1301 | clrrdi r3,r3,2 |
1302 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1303 | bge guest_exit_cont |
a8606e20 PM |
1304 | LOAD_REG_ADDR(r4, hcall_real_table) |
1305 | lwzx r3,r3,r4 | |
1306 | cmpwi r3,0 | |
b4072df4 | 1307 | beq guest_exit_cont |
a8606e20 PM |
1308 | add r3,r3,r4 |
1309 | mtctr r3 | |
1310 | mr r3,r9 /* get vcpu pointer */ | |
c75df6f9 | 1311 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1312 | bctrl |
1313 | cmpdi r3,H_TOO_HARD | |
1314 | beq hcall_real_fallback | |
1315 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1316 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1317 | ld r10,VCPU_PC(r4) |
1318 | ld r11,VCPU_MSR(r4) | |
1319 | b fast_guest_return | |
1320 | ||
1321 | /* We've attempted a real mode hcall, but it's punted it back | |
1322 | * to userspace. We need to restore some clobbered volatiles | |
1323 | * before resuming the pass-it-to-qemu path */ | |
1324 | hcall_real_fallback: | |
1325 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1326 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1327 | |
b4072df4 | 1328 | b guest_exit_cont |
a8606e20 PM |
1329 | |
1330 | .globl hcall_real_table | |
1331 | hcall_real_table: | |
1332 | .long 0 /* 0 - unused */ | |
1333 | .long .kvmppc_h_remove - hcall_real_table | |
1334 | .long .kvmppc_h_enter - hcall_real_table | |
1335 | .long .kvmppc_h_read - hcall_real_table | |
1336 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1337 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1338 | .long .kvmppc_h_protect - hcall_real_table | |
1339 | .long 0 /* 0x1c - H_GET_TCE */ | |
54738c09 | 1340 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1341 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1342 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1343 | .long 0 /* 0x2c */ | |
1344 | .long 0 /* 0x30 */ | |
1345 | .long 0 /* 0x34 */ | |
1346 | .long 0 /* 0x38 */ | |
1347 | .long 0 /* 0x3c */ | |
1348 | .long 0 /* 0x40 */ | |
1349 | .long 0 /* 0x44 */ | |
1350 | .long 0 /* 0x48 */ | |
1351 | .long 0 /* 0x4c */ | |
1352 | .long 0 /* 0x50 */ | |
1353 | .long 0 /* 0x54 */ | |
1354 | .long 0 /* 0x58 */ | |
1355 | .long 0 /* 0x5c */ | |
1356 | .long 0 /* 0x60 */ | |
1357 | .long 0 /* 0x64 */ | |
1358 | .long 0 /* 0x68 */ | |
1359 | .long 0 /* 0x6c */ | |
1360 | .long 0 /* 0x70 */ | |
1361 | .long 0 /* 0x74 */ | |
1362 | .long 0 /* 0x78 */ | |
1363 | .long 0 /* 0x7c */ | |
1364 | .long 0 /* 0x80 */ | |
1365 | .long 0 /* 0x84 */ | |
1366 | .long 0 /* 0x88 */ | |
1367 | .long 0 /* 0x8c */ | |
1368 | .long 0 /* 0x90 */ | |
1369 | .long 0 /* 0x94 */ | |
1370 | .long 0 /* 0x98 */ | |
1371 | .long 0 /* 0x9c */ | |
1372 | .long 0 /* 0xa0 */ | |
1373 | .long 0 /* 0xa4 */ | |
1374 | .long 0 /* 0xa8 */ | |
1375 | .long 0 /* 0xac */ | |
1376 | .long 0 /* 0xb0 */ | |
1377 | .long 0 /* 0xb4 */ | |
1378 | .long 0 /* 0xb8 */ | |
1379 | .long 0 /* 0xbc */ | |
1380 | .long 0 /* 0xc0 */ | |
1381 | .long 0 /* 0xc4 */ | |
1382 | .long 0 /* 0xc8 */ | |
1383 | .long 0 /* 0xcc */ | |
1384 | .long 0 /* 0xd0 */ | |
1385 | .long 0 /* 0xd4 */ | |
1386 | .long 0 /* 0xd8 */ | |
1387 | .long 0 /* 0xdc */ | |
19ccb76a | 1388 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
1389 | .long 0 /* 0xe4 */ |
1390 | .long 0 /* 0xe8 */ | |
1391 | .long 0 /* 0xec */ | |
1392 | .long 0 /* 0xf0 */ | |
1393 | .long 0 /* 0xf4 */ | |
1394 | .long 0 /* 0xf8 */ | |
1395 | .long 0 /* 0xfc */ | |
1396 | .long 0 /* 0x100 */ | |
1397 | .long 0 /* 0x104 */ | |
1398 | .long 0 /* 0x108 */ | |
1399 | .long 0 /* 0x10c */ | |
1400 | .long 0 /* 0x110 */ | |
1401 | .long 0 /* 0x114 */ | |
1402 | .long 0 /* 0x118 */ | |
1403 | .long 0 /* 0x11c */ | |
1404 | .long 0 /* 0x120 */ | |
1405 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
1406 | hcall_real_table_end: | |
1407 | ||
de56a948 PM |
1408 | ignore_hdec: |
1409 | mr r4,r9 | |
1410 | b fast_guest_return | |
1411 | ||
1412 | bounce_ext_interrupt: | |
1413 | mr r4,r9 | |
1414 | mtspr SPRN_SRR0,r10 | |
1415 | mtspr SPRN_SRR1,r11 | |
1416 | li r10,BOOK3S_INTERRUPT_EXTERNAL | |
19ccb76a PM |
1417 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ |
1418 | rotldi r11,r11,63 | |
de56a948 PM |
1419 | b fast_guest_return |
1420 | ||
a8606e20 PM |
1421 | _GLOBAL(kvmppc_h_set_dabr) |
1422 | std r4,VCPU_DABR(r3) | |
8943633c PM |
1423 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
1424 | 1: mtspr SPRN_DABR,r4 | |
1425 | mfspr r5, SPRN_DABR | |
1426 | cmpd r4, r5 | |
1427 | bne 1b | |
1428 | isync | |
a8606e20 PM |
1429 | li r3,0 |
1430 | blr | |
1431 | ||
19ccb76a PM |
1432 | _GLOBAL(kvmppc_h_cede) |
1433 | ori r11,r11,MSR_EE | |
1434 | std r11,VCPU_MSR(r3) | |
1435 | li r0,1 | |
1436 | stb r0,VCPU_CEDED(r3) | |
1437 | sync /* order setting ceded vs. testing prodded */ | |
1438 | lbz r5,VCPU_PRODDED(r3) | |
1439 | cmpwi r5,0 | |
04f995a5 | 1440 | bne kvm_cede_prodded |
19ccb76a PM |
1441 | li r0,0 /* set trap to 0 to say hcall is handled */ |
1442 | stw r0,VCPU_TRAP(r3) | |
1443 | li r0,H_SUCCESS | |
c75df6f9 | 1444 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a | 1445 | BEGIN_FTR_SECTION |
04f995a5 | 1446 | b kvm_cede_exit /* just send it up to host on 970 */ |
19ccb76a PM |
1447 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
1448 | ||
1449 | /* | |
1450 | * Set our bit in the bitmask of napping threads unless all the | |
1451 | * other threads are already napping, in which case we send this | |
1452 | * up to the host. | |
1453 | */ | |
1454 | ld r5,HSTATE_KVM_VCORE(r13) | |
1455 | lwz r6,VCPU_PTID(r3) | |
1456 | lwz r8,VCORE_ENTRY_EXIT(r5) | |
1457 | clrldi r8,r8,56 | |
1458 | li r0,1 | |
1459 | sld r0,r0,r6 | |
1460 | addi r6,r5,VCORE_NAPPING_THREADS | |
1461 | 31: lwarx r4,0,r6 | |
1462 | or r4,r4,r0 | |
c75df6f9 | 1463 | PPC_POPCNTW(R7,R4) |
19ccb76a | 1464 | cmpw r7,r8 |
04f995a5 | 1465 | bge kvm_cede_exit |
19ccb76a PM |
1466 | stwcx. r4,0,r6 |
1467 | bne 31b | |
1468 | li r0,1 | |
1469 | stb r0,HSTATE_NAPPING(r13) | |
1470 | /* order napping_threads update vs testing entry_exit_count */ | |
1471 | lwsync | |
1472 | mr r4,r3 | |
1473 | lwz r7,VCORE_ENTRY_EXIT(r5) | |
1474 | cmpwi r7,0x100 | |
1475 | bge 33f /* another thread already exiting */ | |
1476 | ||
1477 | /* | |
1478 | * Although not specifically required by the architecture, POWER7 | |
1479 | * preserves the following registers in nap mode, even if an SMT mode | |
1480 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
1481 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
1482 | */ | |
1483 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1484 | std r14, VCPU_GPR(R14)(r3) |
1485 | std r15, VCPU_GPR(R15)(r3) | |
1486 | std r16, VCPU_GPR(R16)(r3) | |
1487 | std r17, VCPU_GPR(R17)(r3) | |
1488 | std r18, VCPU_GPR(R18)(r3) | |
1489 | std r19, VCPU_GPR(R19)(r3) | |
1490 | std r20, VCPU_GPR(R20)(r3) | |
1491 | std r21, VCPU_GPR(R21)(r3) | |
1492 | std r22, VCPU_GPR(R22)(r3) | |
1493 | std r23, VCPU_GPR(R23)(r3) | |
1494 | std r24, VCPU_GPR(R24)(r3) | |
1495 | std r25, VCPU_GPR(R25)(r3) | |
1496 | std r26, VCPU_GPR(R26)(r3) | |
1497 | std r27, VCPU_GPR(R27)(r3) | |
1498 | std r28, VCPU_GPR(R28)(r3) | |
1499 | std r29, VCPU_GPR(R29)(r3) | |
1500 | std r30, VCPU_GPR(R30)(r3) | |
1501 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
1502 | |
1503 | /* save FP state */ | |
1504 | bl .kvmppc_save_fp | |
1505 | ||
1506 | /* | |
1507 | * Take a nap until a decrementer or external interrupt occurs, | |
1508 | * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR | |
1509 | */ | |
f0888f70 PM |
1510 | li r0,1 |
1511 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
1512 | mfspr r5,SPRN_LPCR |
1513 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
1514 | mtspr SPRN_LPCR,r5 | |
1515 | isync | |
1516 | li r0, 0 | |
1517 | std r0, HSTATE_SCRATCH0(r13) | |
1518 | ptesync | |
1519 | ld r0, HSTATE_SCRATCH0(r13) | |
1520 | 1: cmpd r0, r0 | |
1521 | bne 1b | |
1522 | nap | |
1523 | b . | |
1524 | ||
1525 | kvm_end_cede: | |
1526 | /* Woken by external or decrementer interrupt */ | |
1527 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 1528 | |
19ccb76a PM |
1529 | /* load up FP state */ |
1530 | bl kvmppc_load_fp | |
1531 | ||
1532 | /* Load NV GPRS */ | |
c75df6f9 MN |
1533 | ld r14, VCPU_GPR(R14)(r4) |
1534 | ld r15, VCPU_GPR(R15)(r4) | |
1535 | ld r16, VCPU_GPR(R16)(r4) | |
1536 | ld r17, VCPU_GPR(R17)(r4) | |
1537 | ld r18, VCPU_GPR(R18)(r4) | |
1538 | ld r19, VCPU_GPR(R19)(r4) | |
1539 | ld r20, VCPU_GPR(R20)(r4) | |
1540 | ld r21, VCPU_GPR(R21)(r4) | |
1541 | ld r22, VCPU_GPR(R22)(r4) | |
1542 | ld r23, VCPU_GPR(R23)(r4) | |
1543 | ld r24, VCPU_GPR(R24)(r4) | |
1544 | ld r25, VCPU_GPR(R25)(r4) | |
1545 | ld r26, VCPU_GPR(R26)(r4) | |
1546 | ld r27, VCPU_GPR(R27)(r4) | |
1547 | ld r28, VCPU_GPR(R28)(r4) | |
1548 | ld r29, VCPU_GPR(R29)(r4) | |
1549 | ld r30, VCPU_GPR(R30)(r4) | |
1550 | ld r31, VCPU_GPR(R31)(r4) | |
19ccb76a PM |
1551 | |
1552 | /* clear our bit in vcore->napping_threads */ | |
1553 | 33: ld r5,HSTATE_KVM_VCORE(r13) | |
1554 | lwz r3,VCPU_PTID(r4) | |
1555 | li r0,1 | |
1556 | sld r0,r0,r3 | |
1557 | addi r6,r5,VCORE_NAPPING_THREADS | |
1558 | 32: lwarx r7,0,r6 | |
1559 | andc r7,r7,r0 | |
1560 | stwcx. r7,0,r6 | |
1561 | bne 32b | |
1562 | li r0,0 | |
1563 | stb r0,HSTATE_NAPPING(r13) | |
1564 | ||
1565 | /* see if any other thread is already exiting */ | |
1566 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
1567 | cmpwi r0,0x100 | |
1568 | blt kvmppc_cede_reentry /* if not go back to guest */ | |
1569 | ||
1570 | /* some threads are exiting, so go to the guest exit path */ | |
1571 | b hcall_real_fallback | |
1572 | ||
1573 | /* cede when already previously prodded case */ | |
04f995a5 PM |
1574 | kvm_cede_prodded: |
1575 | li r0,0 | |
19ccb76a PM |
1576 | stb r0,VCPU_PRODDED(r3) |
1577 | sync /* order testing prodded vs. clearing ceded */ | |
1578 | stb r0,VCPU_CEDED(r3) | |
1579 | li r3,H_SUCCESS | |
1580 | blr | |
1581 | ||
1582 | /* we've ceded but we want to give control to the host */ | |
04f995a5 PM |
1583 | kvm_cede_exit: |
1584 | li r3,H_TOO_HARD | |
19ccb76a PM |
1585 | blr |
1586 | ||
b4072df4 PM |
1587 | /* Try to handle a machine check in real mode */ |
1588 | machine_check_realmode: | |
1589 | mr r3, r9 /* get vcpu pointer */ | |
1590 | bl .kvmppc_realmode_machine_check | |
1591 | nop | |
1592 | cmpdi r3, 0 /* continue exiting from guest? */ | |
1593 | ld r9, HSTATE_KVM_VCPU(r13) | |
1594 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1595 | beq mc_cont | |
1596 | /* If not, deliver a machine check. SRR0/1 are already set */ | |
1597 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1598 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1599 | rotldi r11, r11, 63 | |
1600 | b fast_interrupt_c_return | |
1601 | ||
371fefd6 PM |
1602 | secondary_too_late: |
1603 | ld r5,HSTATE_KVM_VCORE(r13) | |
1604 | HMT_LOW | |
1605 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1606 | cmpwi r3,0 | |
1607 | bne 13b | |
1608 | HMT_MEDIUM | |
1609 | ld r11,PACA_SLBSHADOWPTR(r13) | |
1610 | ||
1611 | .rept SLB_NUM_BOLTED | |
1612 | ld r5,SLBSHADOW_SAVEAREA(r11) | |
1613 | ld r6,SLBSHADOW_SAVEAREA+8(r11) | |
1614 | andis. r7,r5,SLB_ESID_V@h | |
1615 | beq 1f | |
1616 | slbmte r6,r5 | |
1617 | 1: addi r11,r11,16 | |
1618 | .endr | |
371fefd6 PM |
1619 | |
1620 | secondary_nap: | |
7b444c67 PM |
1621 | /* Clear our vcpu pointer so we don't come back in early */ |
1622 | li r0, 0 | |
1623 | std r0, HSTATE_KVM_VCPU(r13) | |
1624 | lwsync | |
19ccb76a PM |
1625 | /* Clear any pending IPI - assume we're a secondary thread */ |
1626 | ld r5, HSTATE_XICS_PHYS(r13) | |
1627 | li r7, XICS_XIRR | |
1628 | lwzcix r3, r5, r7 /* ack any pending interrupt */ | |
1629 | rlwinm. r0, r3, 0, 0xffffff /* any pending? */ | |
1630 | beq 37f | |
1631 | sync | |
371fefd6 PM |
1632 | li r0, 0xff |
1633 | li r6, XICS_QIRR | |
19ccb76a PM |
1634 | stbcix r0, r5, r6 /* clear the IPI */ |
1635 | stwcix r3, r5, r7 /* EOI it */ | |
1636 | 37: sync | |
371fefd6 PM |
1637 | |
1638 | /* increment the nap count and then go to nap mode */ | |
1639 | ld r4, HSTATE_KVM_VCORE(r13) | |
1640 | addi r4, r4, VCORE_NAP_COUNT | |
1641 | lwsync /* make previous updates visible */ | |
1642 | 51: lwarx r3, 0, r4 | |
1643 | addi r3, r3, 1 | |
1644 | stwcx. r3, 0, r4 | |
1645 | bne 51b | |
371fefd6 | 1646 | |
f0888f70 PM |
1647 | kvm_no_guest: |
1648 | li r0, KVM_HWTHREAD_IN_NAP | |
1649 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
f0888f70 | 1650 | |
19ccb76a | 1651 | li r3, LPCR_PECE0 |
371fefd6 | 1652 | mfspr r4, SPRN_LPCR |
19ccb76a | 1653 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 |
371fefd6 | 1654 | mtspr SPRN_LPCR, r4 |
19ccb76a | 1655 | isync |
371fefd6 PM |
1656 | std r0, HSTATE_SCRATCH0(r13) |
1657 | ptesync | |
1658 | ld r0, HSTATE_SCRATCH0(r13) | |
1659 | 1: cmpd r0, r0 | |
1660 | bne 1b | |
1661 | nap | |
1662 | b . | |
1663 | ||
de56a948 PM |
1664 | /* |
1665 | * Save away FP, VMX and VSX registers. | |
1666 | * r3 = vcpu pointer | |
a8606e20 | 1667 | */ |
de56a948 | 1668 | _GLOBAL(kvmppc_save_fp) |
8943633c PM |
1669 | mfmsr r5 |
1670 | ori r8,r5,MSR_FP | |
de56a948 PM |
1671 | #ifdef CONFIG_ALTIVEC |
1672 | BEGIN_FTR_SECTION | |
1673 | oris r8,r8,MSR_VEC@h | |
1674 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1675 | #endif | |
1676 | #ifdef CONFIG_VSX | |
1677 | BEGIN_FTR_SECTION | |
1678 | oris r8,r8,MSR_VSX@h | |
1679 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1680 | #endif | |
1681 | mtmsrd r8 | |
1682 | isync | |
1683 | #ifdef CONFIG_VSX | |
1684 | BEGIN_FTR_SECTION | |
1685 | reg = 0 | |
1686 | .rept 32 | |
1687 | li r6,reg*16+VCPU_VSRS | |
c75df6f9 | 1688 | STXVD2X(reg,R6,R3) |
de56a948 PM |
1689 | reg = reg + 1 |
1690 | .endr | |
1691 | FTR_SECTION_ELSE | |
1692 | #endif | |
1693 | reg = 0 | |
1694 | .rept 32 | |
1695 | stfd reg,reg*8+VCPU_FPRS(r3) | |
1696 | reg = reg + 1 | |
1697 | .endr | |
1698 | #ifdef CONFIG_VSX | |
1699 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1700 | #endif | |
1701 | mffs fr0 | |
1702 | stfd fr0,VCPU_FPSCR(r3) | |
1703 | ||
1704 | #ifdef CONFIG_ALTIVEC | |
1705 | BEGIN_FTR_SECTION | |
1706 | reg = 0 | |
1707 | .rept 32 | |
1708 | li r6,reg*16+VCPU_VRS | |
1709 | stvx reg,r6,r3 | |
1710 | reg = reg + 1 | |
1711 | .endr | |
1712 | mfvscr vr0 | |
1713 | li r6,VCPU_VSCR | |
1714 | stvx vr0,r6,r3 | |
1715 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1716 | #endif | |
1717 | mfspr r6,SPRN_VRSAVE | |
1718 | stw r6,VCPU_VRSAVE(r3) | |
8943633c | 1719 | mtmsrd r5 |
de56a948 PM |
1720 | isync |
1721 | blr | |
1722 | ||
1723 | /* | |
1724 | * Load up FP, VMX and VSX registers | |
1725 | * r4 = vcpu pointer | |
1726 | */ | |
1727 | .globl kvmppc_load_fp | |
1728 | kvmppc_load_fp: | |
1729 | mfmsr r9 | |
1730 | ori r8,r9,MSR_FP | |
1731 | #ifdef CONFIG_ALTIVEC | |
1732 | BEGIN_FTR_SECTION | |
1733 | oris r8,r8,MSR_VEC@h | |
1734 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1735 | #endif | |
1736 | #ifdef CONFIG_VSX | |
1737 | BEGIN_FTR_SECTION | |
1738 | oris r8,r8,MSR_VSX@h | |
1739 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1740 | #endif | |
1741 | mtmsrd r8 | |
1742 | isync | |
1743 | lfd fr0,VCPU_FPSCR(r4) | |
1744 | MTFSF_L(fr0) | |
1745 | #ifdef CONFIG_VSX | |
1746 | BEGIN_FTR_SECTION | |
1747 | reg = 0 | |
1748 | .rept 32 | |
1749 | li r7,reg*16+VCPU_VSRS | |
c75df6f9 | 1750 | LXVD2X(reg,R7,R4) |
de56a948 PM |
1751 | reg = reg + 1 |
1752 | .endr | |
1753 | FTR_SECTION_ELSE | |
1754 | #endif | |
1755 | reg = 0 | |
1756 | .rept 32 | |
1757 | lfd reg,reg*8+VCPU_FPRS(r4) | |
1758 | reg = reg + 1 | |
1759 | .endr | |
1760 | #ifdef CONFIG_VSX | |
1761 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1762 | #endif | |
1763 | ||
1764 | #ifdef CONFIG_ALTIVEC | |
1765 | BEGIN_FTR_SECTION | |
1766 | li r7,VCPU_VSCR | |
1767 | lvx vr0,r7,r4 | |
1768 | mtvscr vr0 | |
1769 | reg = 0 | |
1770 | .rept 32 | |
1771 | li r7,reg*16+VCPU_VRS | |
1772 | lvx reg,r7,r4 | |
1773 | reg = reg + 1 | |
1774 | .endr | |
1775 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1776 | #endif | |
1777 | lwz r7,VCPU_VRSAVE(r4) | |
1778 | mtspr SPRN_VRSAVE,r7 | |
1779 | blr |