[deliverable/linux.git] / arch / powerpc / kvm / bookehv_interrupts.S

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * Author: Varun Sethi <varun.sethi@freescale.com>
 * Author: Scott Wood <scotwood@freescale.com>
 *
 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
 */

#include <asm/ppc_asm.h>
#include <asm/kvm_asm.h>
#include <asm/reg.h>
#include <asm/mmu-44x.h>
#include <asm/page.h>
#include <asm/asm-compat.h>
#include <asm/asm-offsets.h>
#include <asm/bitsperlong.h>
#include <asm/thread_info.h>

#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */

#define GET_VCPU(vcpu, thread)	\
	PPC_LL	vcpu, THREAD_KVM_VCPU(thread)

#define LONGBYTES		(BITS_PER_LONG / 8)

#define VCPU_GPR(n)     	(VCPU_GPRS + (n * LONGBYTES))
#define VCPU_GUEST_SPRG(n)	(VCPU_GUEST_SPRGS + (n * LONGBYTES))

/* The host stack layout: */
#define HOST_R1         (0 * LONGBYTES) /* Implied by stwu. */
#define HOST_CALLEE_LR  (1 * LONGBYTES)
#define HOST_RUN        (2 * LONGBYTES) /* struct kvm_run */
/*
 * r2 is special: it holds 'current', and it made nonvolatile in the
 * kernel with the -ffixed-r2 gcc option.
 */
#define HOST_R2         (3 * LONGBYTES)
#define HOST_NV_GPRS    (4 * LONGBYTES)
#define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
#define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */

#define NEED_EMU		0x00000001 /* emulation -- save nv regs */
#define NEED_DEAR		0x00000002 /* save faulting DEAR */
#define NEED_ESR		0x00000004 /* save faulting ESR */

/*
 * On entry:
 * r4 = vcpu, r5 = srr0, r6 = srr1
 * saved in vcpu: cr, ctr, r3-r13
 */
.macro kvm_handler_common intno, srr0, flags
	/* Restore host stack pointer */
	PPC_STL	r1, VCPU_GPR(r1)(r4)
	PPC_STL	r2, VCPU_GPR(r2)(r4)
	PPC_LL	r1, VCPU_HOST_STACK(r4)
	PPC_LL	r2, HOST_R2(r1)

	mfspr	r10, SPRN_PID
	lwz	r8, VCPU_HOST_PID(r4)
	PPC_LL	r11, VCPU_SHARED(r4)
	PPC_STL	r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
	li	r14, \intno

	stw	r10, VCPU_GUEST_PID(r4)
	mtspr	SPRN_PID, r8

#ifdef CONFIG_KVM_EXIT_TIMING
	/* save exit time */
1:	mfspr	r7, SPRN_TBRU
	mfspr	r8, SPRN_TBRL
	mfspr	r9, SPRN_TBRU
	cmpw	r9, r7
	PPC_STL	r8, VCPU_TIMING_EXIT_TBL(r4)
	bne-	1b
	PPC_STL	r9, VCPU_TIMING_EXIT_TBU(r4)
#endif

	oris	r8, r6, MSR_CE@h
#ifdef CONFIG_64BIT
	std	r6, (VCPU_SHARED_MSR)(r11)
#else
	stw	r6, (VCPU_SHARED_MSR + 4)(r11)
#endif
	ori	r8, r8, MSR_ME | MSR_RI
	PPC_STL	r5, VCPU_PC(r4)

	/*
	 * Make sure CE/ME/RI are set (if appropriate for exception type)
	 * whether or not the guest had it set.  Since mfmsr/mtmsr are
	 * somewhat expensive, skip in the common case where the guest
	 * had all these bits set (and thus they're still set if
	 * appropriate for the exception type).
	 */
	cmpw	r6, r8
	beq	1f
	mfmsr	r7
	.if	\srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
	oris	r7, r7, MSR_CE@h
	.endif
	.if	\srr0 != SPRN_MCSRR0
	ori	r7, r7, MSR_ME | MSR_RI
	.endif
	mtmsr	r7
1:

	.if	\flags & NEED_EMU
	/*
	 * This assumes you have external PID support.
	 * To support a bookehv CPU without external PID, you'll
	 * need to look up the TLB entry and create a temporary mapping.
	 *
	 * FIXME: we don't currently handle if the lwepx faults.  PR-mode
	 * booke doesn't handle it either.  Since Linux doesn't use
	 * broadcast tlbivax anymore, the only way this should happen is
	 * if the guest maps its memory execute-but-not-read, or if we
	 * somehow take a TLB miss in the middle of this entry code and
	 * evict the relevant entry.  On e500mc, all kernel lowmem is
	 * bolted into TLB1 large page mappings, and we don't use
	 * broadcast invalidates, so we should not take a TLB miss here.
	 *
	 * Later we'll need to deal with faults here.  Disallowing guest
	 * mappings that are execute-but-not-read could be an option on
	 * e500mc, but not on chips with an LRAT if it is used.
	 */

	mfspr	r3, SPRN_EPLC	/* will already have correct ELPID and EGS */
	PPC_STL	r15, VCPU_GPR(r15)(r4)
	PPC_STL	r16, VCPU_GPR(r16)(r4)
	PPC_STL	r17, VCPU_GPR(r17)(r4)
	PPC_STL	r18, VCPU_GPR(r18)(r4)
	PPC_STL	r19, VCPU_GPR(r19)(r4)
	mr	r8, r3
	PPC_STL	r20, VCPU_GPR(r20)(r4)
	rlwimi	r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
	PPC_STL	r21, VCPU_GPR(r21)(r4)
	rlwimi	r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
	PPC_STL	r22, VCPU_GPR(r22)(r4)
	rlwimi	r8, r10, EPC_EPID_SHIFT, EPC_EPID
	PPC_STL	r23, VCPU_GPR(r23)(r4)
	PPC_STL	r24, VCPU_GPR(r24)(r4)
	PPC_STL	r25, VCPU_GPR(r25)(r4)
	PPC_STL	r26, VCPU_GPR(r26)(r4)
	PPC_STL	r27, VCPU_GPR(r27)(r4)
	PPC_STL	r28, VCPU_GPR(r28)(r4)
	PPC_STL	r29, VCPU_GPR(r29)(r4)
	PPC_STL	r30, VCPU_GPR(r30)(r4)
	PPC_STL	r31, VCPU_GPR(r31)(r4)
	mtspr	SPRN_EPLC, r8

	/* disable preemption, so we are sure we hit the fixup handler */
#ifdef CONFIG_PPC64
	clrrdi	r8,r1,THREAD_SHIFT
#else
	rlwinm	r8,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
#endif
	li	r7, 1
	stw	r7, TI_PREEMPT(r8)

	isync

	/*
	 * In case the read goes wrong, we catch it and write an invalid value
	 * in LAST_INST instead.
	 */
1:	lwepx	r9, 0, r5
2:
.section .fixup, "ax"
3:	li	r9, KVM_INST_FETCH_FAILED
	b	2b
.previous
.section __ex_table,"a"
	PPC_LONG_ALIGN
	PPC_LONG 1b,3b
.previous

	mtspr	SPRN_EPLC, r3
	li	r7, 0
	stw	r7, TI_PREEMPT(r8)
	stw	r9, VCPU_LAST_INST(r4)
	.endif

	.if	\flags & NEED_ESR
	mfspr	r8, SPRN_ESR
	PPC_STL	r8, VCPU_FAULT_ESR(r4)
	.endif

	.if	\flags & NEED_DEAR
	mfspr	r9, SPRN_DEAR
	PPC_STL	r9, VCPU_FAULT_DEAR(r4)
	.endif

	b	kvmppc_resume_host
.endm

/*
 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
 */
.macro kvm_handler intno srr0, srr1, flags
_GLOBAL(kvmppc_handler_\intno\()_\srr1)
	GET_VCPU(r11, r10)
	PPC_STL r3, VCPU_GPR(r3)(r11)
	mfspr	r3, SPRN_SPRG_RSCRATCH0
	PPC_STL	r4, VCPU_GPR(r4)(r11)
	PPC_LL	r4, THREAD_NORMSAVE(0)(r10)
	PPC_STL	r5, VCPU_GPR(r5)(r11)
	PPC_STL	r13, VCPU_CR(r11)
	mfspr	r5, \srr0
	PPC_STL	r3, VCPU_GPR(r10)(r11)
	PPC_LL	r3, THREAD_NORMSAVE(2)(r10)
	PPC_STL	r6, VCPU_GPR(r6)(r11)
	PPC_STL	r4, VCPU_GPR(r11)(r11)
	mfspr	r6, \srr1
	PPC_STL	r7, VCPU_GPR(r7)(r11)
	PPC_STL	r8, VCPU_GPR(r8)(r11)
	PPC_STL	r9, VCPU_GPR(r9)(r11)
	PPC_STL r3, VCPU_GPR(r13)(r11)
	mfctr	r7
	PPC_STL	r12, VCPU_GPR(r12)(r11)
	PPC_STL	r7, VCPU_CTR(r11)
	mr	r4, r11
	kvm_handler_common \intno, \srr0, \flags
.endm

.macro kvm_lvl_handler intno scratch srr0, srr1, flags
_GLOBAL(kvmppc_handler_\intno\()_\srr1)
	mfspr	r10, SPRN_SPRG_THREAD
	GET_VCPU(r11, r10)
	PPC_STL r3, VCPU_GPR(r3)(r11)
	mfspr	r3, \scratch
	PPC_STL	r4, VCPU_GPR(r4)(r11)
	PPC_LL	r4, GPR9(r8)
	PPC_STL	r5, VCPU_GPR(r5)(r11)
	PPC_STL	r9, VCPU_CR(r11)
	mfspr	r5, \srr0
	PPC_STL	r3, VCPU_GPR(r8)(r11)
	PPC_LL	r3, GPR10(r8)
	PPC_STL	r6, VCPU_GPR(r6)(r11)
	PPC_STL	r4, VCPU_GPR(r9)(r11)
	mfspr	r6, \srr1
	PPC_LL	r4, GPR11(r8)
	PPC_STL	r7, VCPU_GPR(r7)(r11)
	PPC_STL	r8, VCPU_GPR(r8)(r11)
	PPC_STL r3, VCPU_GPR(r10)(r11)
	mfctr	r7
	PPC_STL	r12, VCPU_GPR(r12)(r11)
	PPC_STL	r4, VCPU_GPR(r11)(r11)
	PPC_STL	r7, VCPU_CTR(r11)
	mr	r4, r11
	kvm_handler_common \intno, \srr0, \flags
.endm

kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
	SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
	SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
	SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
	SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
	SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0


/* Registers:
 *  SPRG_SCRATCH0: guest r10
 *  r4: vcpu pointer
 *  r11: vcpu->arch.shared
 *  r14: KVM exit number
 */
_GLOBAL(kvmppc_resume_host)
	/* Save remaining volatile guest register state to vcpu. */
	mfspr	r3, SPRN_VRSAVE
	PPC_STL	r0, VCPU_GPR(r0)(r4)
	mflr	r5
	mfspr	r6, SPRN_SPRG4
	PPC_STL	r5, VCPU_LR(r4)
	mfspr	r7, SPRN_SPRG5
	PPC_STL	r3, VCPU_VRSAVE(r4)
	PPC_STL	r6, VCPU_SHARED_SPRG4(r11)
	mfspr	r8, SPRN_SPRG6
	PPC_STL	r7, VCPU_SHARED_SPRG5(r11)
	mfspr	r9, SPRN_SPRG7
	PPC_STL	r8, VCPU_SHARED_SPRG6(r11)
	mfxer	r3
	PPC_STL	r9, VCPU_SHARED_SPRG7(r11)

	/* save guest MAS registers and restore host mas4 & mas6 */
	mfspr	r5, SPRN_MAS0
	PPC_STL	r3, VCPU_XER(r4)
	mfspr	r6, SPRN_MAS1
	stw	r5, VCPU_SHARED_MAS0(r11)
	mfspr	r7, SPRN_MAS2
	stw	r6, VCPU_SHARED_MAS1(r11)
#ifdef CONFIG_64BIT
	std	r7, (VCPU_SHARED_MAS2)(r11)
#else
	stw	r7, (VCPU_SHARED_MAS2 + 4)(r11)
#endif
	mfspr	r5, SPRN_MAS3
	mfspr	r6, SPRN_MAS4
	stw	r5, VCPU_SHARED_MAS7_3+4(r11)
	mfspr	r7, SPRN_MAS6
	stw	r6, VCPU_SHARED_MAS4(r11)
	mfspr	r5, SPRN_MAS7
	lwz	r6, VCPU_HOST_MAS4(r4)
	stw	r7, VCPU_SHARED_MAS6(r11)
	lwz	r8, VCPU_HOST_MAS6(r4)
	mtspr	SPRN_MAS4, r6
	stw	r5, VCPU_SHARED_MAS7_3+0(r11)
	mtspr	SPRN_MAS6, r8
	/* Enable MAS register updates via exception */
	mfspr	r3, SPRN_EPCR
	rlwinm	r3, r3, 0, ~SPRN_EPCR_DMIUH
	mtspr	SPRN_EPCR, r3
	isync

	/* Switch to kernel stack and jump to handler. */
	PPC_LL	r3, HOST_RUN(r1)
	mr	r5, r14 /* intno */
	mr	r14, r4 /* Save vcpu pointer. */
	bl	kvmppc_handle_exit

	/* Restore vcpu pointer and the nonvolatiles we used. */
	mr	r4, r14
	PPC_LL	r14, VCPU_GPR(r14)(r4)

	andi.	r5, r3, RESUME_FLAG_NV
	beq	skip_nv_load
	PPC_LL	r15, VCPU_GPR(r15)(r4)
	PPC_LL	r16, VCPU_GPR(r16)(r4)
	PPC_LL	r17, VCPU_GPR(r17)(r4)
	PPC_LL	r18, VCPU_GPR(r18)(r4)
	PPC_LL	r19, VCPU_GPR(r19)(r4)
	PPC_LL	r20, VCPU_GPR(r20)(r4)
	PPC_LL	r21, VCPU_GPR(r21)(r4)
	PPC_LL	r22, VCPU_GPR(r22)(r4)
	PPC_LL	r23, VCPU_GPR(r23)(r4)
	PPC_LL	r24, VCPU_GPR(r24)(r4)
	PPC_LL	r25, VCPU_GPR(r25)(r4)
	PPC_LL	r26, VCPU_GPR(r26)(r4)
	PPC_LL	r27, VCPU_GPR(r27)(r4)
	PPC_LL	r28, VCPU_GPR(r28)(r4)
	PPC_LL	r29, VCPU_GPR(r29)(r4)
	PPC_LL	r30, VCPU_GPR(r30)(r4)
	PPC_LL	r31, VCPU_GPR(r31)(r4)
skip_nv_load:
	/* Should we return to the guest? */
	andi.	r5, r3, RESUME_FLAG_HOST
	beq	lightweight_exit

	srawi	r3, r3, 2 /* Shift -ERR back down. */

heavyweight_exit:
	/* Not returning to guest. */
	PPC_LL	r5, HOST_STACK_LR(r1)

	/*
	 * We already saved guest volatile register state; now save the
	 * non-volatiles.
	 */

	PPC_STL	r15, VCPU_GPR(r15)(r4)
	PPC_STL	r16, VCPU_GPR(r16)(r4)
	PPC_STL	r17, VCPU_GPR(r17)(r4)
	PPC_STL	r18, VCPU_GPR(r18)(r4)
	PPC_STL	r19, VCPU_GPR(r19)(r4)
	PPC_STL	r20, VCPU_GPR(r20)(r4)
	PPC_STL	r21, VCPU_GPR(r21)(r4)
	PPC_STL	r22, VCPU_GPR(r22)(r4)
	PPC_STL	r23, VCPU_GPR(r23)(r4)
	PPC_STL	r24, VCPU_GPR(r24)(r4)
	PPC_STL	r25, VCPU_GPR(r25)(r4)
	PPC_STL	r26, VCPU_GPR(r26)(r4)
	PPC_STL	r27, VCPU_GPR(r27)(r4)
	PPC_STL	r28, VCPU_GPR(r28)(r4)
	PPC_STL	r29, VCPU_GPR(r29)(r4)
	PPC_STL	r30, VCPU_GPR(r30)(r4)
	PPC_STL	r31, VCPU_GPR(r31)(r4)

	/* Load host non-volatile register state from host stack. */
	PPC_LL	r14, HOST_NV_GPR(r14)(r1)
	PPC_LL	r15, HOST_NV_GPR(r15)(r1)
	PPC_LL	r16, HOST_NV_GPR(r16)(r1)
	PPC_LL	r17, HOST_NV_GPR(r17)(r1)
	PPC_LL	r18, HOST_NV_GPR(r18)(r1)
	PPC_LL	r19, HOST_NV_GPR(r19)(r1)
	PPC_LL	r20, HOST_NV_GPR(r20)(r1)
	PPC_LL	r21, HOST_NV_GPR(r21)(r1)
	PPC_LL	r22, HOST_NV_GPR(r22)(r1)
	PPC_LL	r23, HOST_NV_GPR(r23)(r1)
	PPC_LL	r24, HOST_NV_GPR(r24)(r1)
	PPC_LL	r25, HOST_NV_GPR(r25)(r1)
	PPC_LL	r26, HOST_NV_GPR(r26)(r1)
	PPC_LL	r27, HOST_NV_GPR(r27)(r1)
	PPC_LL	r28, HOST_NV_GPR(r28)(r1)
	PPC_LL	r29, HOST_NV_GPR(r29)(r1)
	PPC_LL	r30, HOST_NV_GPR(r30)(r1)
	PPC_LL	r31, HOST_NV_GPR(r31)(r1)

	/* Return to kvm_vcpu_run(). */
	mtlr	r5
	addi	r1, r1, HOST_STACK_SIZE
	/* r3 still contains the return code from kvmppc_handle_exit(). */
	blr

/* Registers:
 *  r3: kvm_run pointer
 *  r4: vcpu pointer
 */
_GLOBAL(__kvmppc_vcpu_run)
	stwu	r1, -HOST_STACK_SIZE(r1)
	PPC_STL	r1, VCPU_HOST_STACK(r4)	/* Save stack pointer to vcpu. */

	/* Save host state to stack. */
	PPC_STL	r3, HOST_RUN(r1)
	mflr	r3
	PPC_STL	r3, HOST_STACK_LR(r1)

	/* Save host non-volatile register state to stack. */
	PPC_STL	r14, HOST_NV_GPR(r14)(r1)
	PPC_STL	r15, HOST_NV_GPR(r15)(r1)
	PPC_STL	r16, HOST_NV_GPR(r16)(r1)
	PPC_STL	r17, HOST_NV_GPR(r17)(r1)
	PPC_STL	r18, HOST_NV_GPR(r18)(r1)
	PPC_STL	r19, HOST_NV_GPR(r19)(r1)
	PPC_STL	r20, HOST_NV_GPR(r20)(r1)
	PPC_STL	r21, HOST_NV_GPR(r21)(r1)
	PPC_STL	r22, HOST_NV_GPR(r22)(r1)
	PPC_STL	r23, HOST_NV_GPR(r23)(r1)
	PPC_STL	r24, HOST_NV_GPR(r24)(r1)
	PPC_STL	r25, HOST_NV_GPR(r25)(r1)
	PPC_STL	r26, HOST_NV_GPR(r26)(r1)
	PPC_STL	r27, HOST_NV_GPR(r27)(r1)
	PPC_STL	r28, HOST_NV_GPR(r28)(r1)
	PPC_STL	r29, HOST_NV_GPR(r29)(r1)
	PPC_STL	r30, HOST_NV_GPR(r30)(r1)
	PPC_STL	r31, HOST_NV_GPR(r31)(r1)

	/* Load guest non-volatiles. */
	PPC_LL	r14, VCPU_GPR(r14)(r4)
	PPC_LL	r15, VCPU_GPR(r15)(r4)
	PPC_LL	r16, VCPU_GPR(r16)(r4)
	PPC_LL	r17, VCPU_GPR(r17)(r4)
	PPC_LL	r18, VCPU_GPR(r18)(r4)
	PPC_LL	r19, VCPU_GPR(r19)(r4)
	PPC_LL	r20, VCPU_GPR(r20)(r4)
	PPC_LL	r21, VCPU_GPR(r21)(r4)
	PPC_LL	r22, VCPU_GPR(r22)(r4)
	PPC_LL	r23, VCPU_GPR(r23)(r4)
	PPC_LL	r24, VCPU_GPR(r24)(r4)
	PPC_LL	r25, VCPU_GPR(r25)(r4)
	PPC_LL	r26, VCPU_GPR(r26)(r4)
	PPC_LL	r27, VCPU_GPR(r27)(r4)
	PPC_LL	r28, VCPU_GPR(r28)(r4)
	PPC_LL	r29, VCPU_GPR(r29)(r4)
	PPC_LL	r30, VCPU_GPR(r30)(r4)
	PPC_LL	r31, VCPU_GPR(r31)(r4)


lightweight_exit:
	PPC_STL	r2, HOST_R2(r1)

	mfspr	r3, SPRN_PID
	stw	r3, VCPU_HOST_PID(r4)
	lwz	r3, VCPU_GUEST_PID(r4)
	mtspr	SPRN_PID, r3

	PPC_LL	r11, VCPU_SHARED(r4)
	/* Disable MAS register updates via exception */
	mfspr	r3, SPRN_EPCR
	oris	r3, r3, SPRN_EPCR_DMIUH@h
	mtspr	SPRN_EPCR, r3
	isync
	/* Save host mas4 and mas6 and load guest MAS registers */
	mfspr	r3, SPRN_MAS4
	stw	r3, VCPU_HOST_MAS4(r4)
	mfspr	r3, SPRN_MAS6
	stw	r3, VCPU_HOST_MAS6(r4)
	lwz	r3, VCPU_SHARED_MAS0(r11)
	lwz	r5, VCPU_SHARED_MAS1(r11)
#ifdef CONFIG_64BIT
	ld	r6, (VCPU_SHARED_MAS2)(r11)
#else
	lwz	r6, (VCPU_SHARED_MAS2 + 4)(r11)
#endif
	lwz	r7, VCPU_SHARED_MAS7_3+4(r11)
	lwz	r8, VCPU_SHARED_MAS4(r11)
	mtspr	SPRN_MAS0, r3
	mtspr	SPRN_MAS1, r5
	mtspr	SPRN_MAS2, r6
	mtspr	SPRN_MAS3, r7
	mtspr	SPRN_MAS4, r8
	lwz	r3, VCPU_SHARED_MAS6(r11)
	lwz	r5, VCPU_SHARED_MAS7_3+0(r11)
	mtspr	SPRN_MAS6, r3
	mtspr	SPRN_MAS7, r5

	/*
	 * Host interrupt handlers may have clobbered these guest-readable
	 * SPRGs, so we need to reload them here with the guest's values.
	 */
	lwz	r3, VCPU_VRSAVE(r4)
	lwz	r5, VCPU_SHARED_SPRG4(r11)
	mtspr	SPRN_VRSAVE, r3
	lwz	r6, VCPU_SHARED_SPRG5(r11)
	mtspr	SPRN_SPRG4W, r5
	lwz	r7, VCPU_SHARED_SPRG6(r11)
	mtspr	SPRN_SPRG5W, r6
	lwz	r8, VCPU_SHARED_SPRG7(r11)
	mtspr	SPRN_SPRG6W, r7
	mtspr	SPRN_SPRG7W, r8

	/* Load some guest volatiles. */
	PPC_LL	r3, VCPU_LR(r4)
	PPC_LL	r5, VCPU_XER(r4)
	PPC_LL	r6, VCPU_CTR(r4)
	PPC_LL	r7, VCPU_CR(r4)
	PPC_LL	r8, VCPU_PC(r4)
#ifdef CONFIG_64BIT
	ld	r9, (VCPU_SHARED_MSR)(r11)
#else
	lwz	r9, (VCPU_SHARED_MSR + 4)(r11)
#endif
	PPC_LL	r0, VCPU_GPR(r0)(r4)
	PPC_LL	r1, VCPU_GPR(r1)(r4)
	PPC_LL	r2, VCPU_GPR(r2)(r4)
	PPC_LL	r10, VCPU_GPR(r10)(r4)
	PPC_LL	r11, VCPU_GPR(r11)(r4)
	PPC_LL	r12, VCPU_GPR(r12)(r4)
	PPC_LL	r13, VCPU_GPR(r13)(r4)
	mtlr	r3
	mtxer	r5
	mtctr	r6
	mtcr	r7
	mtsrr0	r8
	mtsrr1	r9

#ifdef CONFIG_KVM_EXIT_TIMING
	/* save enter time */
1:
	mfspr	r6, SPRN_TBRU
	mfspr	r7, SPRN_TBRL
	mfspr	r8, SPRN_TBRU
	cmpw	r8, r6
	PPC_STL	r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
	bne	1b
	PPC_STL	r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
#endif

	/* Finish loading guest volatiles and jump to guest. */
	PPC_LL	r5, VCPU_GPR(r5)(r4)
	PPC_LL	r6, VCPU_GPR(r6)(r4)
	PPC_LL	r7, VCPU_GPR(r7)(r4)
	PPC_LL	r8, VCPU_GPR(r8)(r4)
	PPC_LL	r9, VCPU_GPR(r9)(r4)

	PPC_LL	r3, VCPU_GPR(r3)(r4)
	PPC_LL	r4, VCPU_GPR(r4)(r4)
	rfi
Commit	Line	Data
d30f6e48 SW	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	16	*
	17	* Author: Varun Sethi <varun.sethi@freescale.com>
	18	* Author: Scott Wood <scotwood@freescale.com>
	19	*
	20	* This file is derived from arch/powerpc/kvm/booke_interrupts.S
	21	*/
	22
	23	#include <asm/ppc_asm.h>
	24	#include <asm/kvm_asm.h>
	25	#include <asm/reg.h>
	26	#include <asm/mmu-44x.h>
	27	#include <asm/page.h>
	28	#include <asm/asm-compat.h>
	29	#include <asm/asm-offsets.h>
	30	#include <asm/bitsperlong.h>
1d628af7	31	#include <asm/thread_info.h>
d30f6e48 SW	32
	33	#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
	34
	35	#define GET_VCPU(vcpu, thread) \
	36	PPC_LL vcpu, THREAD_KVM_VCPU(thread)
	37
d30f6e48 SW	38	#define LONGBYTES (BITS_PER_LONG / 8)
	39
	40	#define VCPU_GPR(n) (VCPU_GPRS + (n * LONGBYTES))
	41	#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
	42
	43	/* The host stack layout: */
	44	#define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */
	45	#define HOST_CALLEE_LR (1 * LONGBYTES)
	46	#define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */
	47	/*
	48	* r2 is special: it holds 'current', and it made nonvolatile in the
	49	* kernel with the -ffixed-r2 gcc option.
	50	*/
	51	#define HOST_R2 (3 * LONGBYTES)
	52	#define HOST_NV_GPRS (4 * LONGBYTES)
	53	#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
	54	#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
	55	#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
	56	#define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
	57
	58	#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
	59	#define NEED_DEAR 0x00000002 /* save faulting DEAR */
	60	#define NEED_ESR 0x00000004 /* save faulting ESR */
	61
	62	/*
	63	* On entry:
	64	* r4 = vcpu, r5 = srr0, r6 = srr1
	65	* saved in vcpu: cr, ctr, r3-r13
	66	*/
	67	.macro kvm_handler_common intno, srr0, flags
a2723ce7 AG	68	/* Restore host stack pointer */
	69	PPC_STL r1, VCPU_GPR(r1)(r4)
	70	PPC_STL r2, VCPU_GPR(r2)(r4)
	71	PPC_LL r1, VCPU_HOST_STACK(r4)
	72	PPC_LL r2, HOST_R2(r1)
	73
d30f6e48 SW	74	mfspr r10, SPRN_PID
	75	lwz r8, VCPU_HOST_PID(r4)
	76	PPC_LL r11, VCPU_SHARED(r4)
	77	PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
	78	li r14, \intno
	79
	80	stw r10, VCPU_GUEST_PID(r4)
	81	mtspr SPRN_PID, r8
	82
d30f6e48 SW	83	#ifdef CONFIG_KVM_EXIT_TIMING
	84	/* save exit time */
	85	1: mfspr r7, SPRN_TBRU
	86	mfspr r8, SPRN_TBRL
	87	mfspr r9, SPRN_TBRU
	88	cmpw r9, r7
	89	PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4)
	90	bne- 1b
	91	PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4)
	92	#endif
	93
	94	oris r8, r6, MSR_CE@h
8764b46e	95	#ifdef CONFIG_64BIT
d30f6e48	96	std r6, (VCPU_SHARED_MSR)(r11)
8764b46e AG	97	#else
8764b46e AG	98	stw r6, (VCPU_SHARED_MSR + 4)(r11)
d30f6e48 SW	99	#endif
	100	ori r8, r8, MSR_ME \| MSR_RI
	101	PPC_STL r5, VCPU_PC(r4)
	102
	103	/*
	104	* Make sure CE/ME/RI are set (if appropriate for exception type)
	105	* whether or not the guest had it set. Since mfmsr/mtmsr are
	106	* somewhat expensive, skip in the common case where the guest
	107	* had all these bits set (and thus they're still set if
	108	* appropriate for the exception type).
	109	*/
	110	cmpw r6, r8
d30f6e48 SW	111	beq 1f
	112	mfmsr r7
	113	.if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
	114	oris r7, r7, MSR_CE@h
	115	.endif
	116	.if \srr0 != SPRN_MCSRR0
	117	ori r7, r7, MSR_ME \| MSR_RI
	118	.endif
	119	mtmsr r7
	120	1:
	121
	122	.if \flags & NEED_EMU
	123	/*
	124	* This assumes you have external PID support.
	125	* To support a bookehv CPU without external PID, you'll
	126	* need to look up the TLB entry and create a temporary mapping.
	127	*
	128	* FIXME: we don't currently handle if the lwepx faults. PR-mode
	129	* booke doesn't handle it either. Since Linux doesn't use
	130	* broadcast tlbivax anymore, the only way this should happen is
	131	* if the guest maps its memory execute-but-not-read, or if we
	132	* somehow take a TLB miss in the middle of this entry code and
	133	* evict the relevant entry. On e500mc, all kernel lowmem is
	134	* bolted into TLB1 large page mappings, and we don't use
	135	* broadcast invalidates, so we should not take a TLB miss here.
	136	*
	137	* Later we'll need to deal with faults here. Disallowing guest
	138	* mappings that are execute-but-not-read could be an option on
	139	* e500mc, but not on chips with an LRAT if it is used.
	140	*/
	141
	142	mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */
	143	PPC_STL r15, VCPU_GPR(r15)(r4)
	144	PPC_STL r16, VCPU_GPR(r16)(r4)
	145	PPC_STL r17, VCPU_GPR(r17)(r4)
	146	PPC_STL r18, VCPU_GPR(r18)(r4)
	147	PPC_STL r19, VCPU_GPR(r19)(r4)
	148	mr r8, r3
	149	PPC_STL r20, VCPU_GPR(r20)(r4)
	150	rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
	151	PPC_STL r21, VCPU_GPR(r21)(r4)
	152	rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
	153	PPC_STL r22, VCPU_GPR(r22)(r4)
	154	rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID
	155	PPC_STL r23, VCPU_GPR(r23)(r4)
	156	PPC_STL r24, VCPU_GPR(r24)(r4)
	157	PPC_STL r25, VCPU_GPR(r25)(r4)
	158	PPC_STL r26, VCPU_GPR(r26)(r4)
	159	PPC_STL r27, VCPU_GPR(r27)(r4)
	160	PPC_STL r28, VCPU_GPR(r28)(r4)
	161	PPC_STL r29, VCPU_GPR(r29)(r4)
	162	PPC_STL r30, VCPU_GPR(r30)(r4)
	163	PPC_STL r31, VCPU_GPR(r31)(r4)
	164	mtspr SPRN_EPLC, r8
1d628af7 AG	165
	166	/* disable preemption, so we are sure we hit the fixup handler */
	167	#ifdef CONFIG_PPC64
	168	clrrdi r8,r1,THREAD_SHIFT
	169	#else
	170	rlwinm r8,r1,0,0,31-THREAD_SHIFT /* current thread_info */
	171	#endif
	172	li r7, 1
	173	stw r7, TI_PREEMPT(r8)
	174
d30f6e48	175	isync
1d628af7 AG	176
	177	/*
	178	* In case the read goes wrong, we catch it and write an invalid value
	179	* in LAST_INST instead.
	180	*/
	181	1: lwepx r9, 0, r5
	182	2:
	183	.section .fixup, "ax"
	184	3: li r9, KVM_INST_FETCH_FAILED
	185	b 2b
	186	.previous
	187	.section __ex_table,"a"
	188	PPC_LONG_ALIGN
	189	PPC_LONG 1b,3b
	190	.previous
	191
d30f6e48	192	mtspr SPRN_EPLC, r3
1d628af7 AG	193	li r7, 0
1d628af7 AG	194	stw r7, TI_PREEMPT(r8)
d30f6e48 SW	195	stw r9, VCPU_LAST_INST(r4)
	196	.endif
	197
	198	.if \flags & NEED_ESR
	199	mfspr r8, SPRN_ESR
	200	PPC_STL r8, VCPU_FAULT_ESR(r4)
	201	.endif
	202
	203	.if \flags & NEED_DEAR
	204	mfspr r9, SPRN_DEAR
	205	PPC_STL r9, VCPU_FAULT_DEAR(r4)
	206	.endif
	207
	208	b kvmppc_resume_host
	209	.endm
	210
	211	/*
	212	* For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
	213	*/
	214	.macro kvm_handler intno srr0, srr1, flags
	215	_GLOBAL(kvmppc_handler_\intno\()_\srr1)
	216	GET_VCPU(r11, r10)
	217	PPC_STL r3, VCPU_GPR(r3)(r11)
	218	mfspr r3, SPRN_SPRG_RSCRATCH0
	219	PPC_STL r4, VCPU_GPR(r4)(r11)
	220	PPC_LL r4, THREAD_NORMSAVE(0)(r10)
	221	PPC_STL r5, VCPU_GPR(r5)(r11)
	222	PPC_STL r13, VCPU_CR(r11)
	223	mfspr r5, \srr0
	224	PPC_STL r3, VCPU_GPR(r10)(r11)
	225	PPC_LL r3, THREAD_NORMSAVE(2)(r10)
	226	PPC_STL r6, VCPU_GPR(r6)(r11)
	227	PPC_STL r4, VCPU_GPR(r11)(r11)
	228	mfspr r6, \srr1
	229	PPC_STL r7, VCPU_GPR(r7)(r11)
	230	PPC_STL r8, VCPU_GPR(r8)(r11)
	231	PPC_STL r9, VCPU_GPR(r9)(r11)
	232	PPC_STL r3, VCPU_GPR(r13)(r11)
	233	mfctr r7
	234	PPC_STL r12, VCPU_GPR(r12)(r11)
	235	PPC_STL r7, VCPU_CTR(r11)
	236	mr r4, r11
	237	kvm_handler_common \intno, \srr0, \flags
	238	.endm
	239
	240	.macro kvm_lvl_handler intno scratch srr0, srr1, flags
	241	_GLOBAL(kvmppc_handler_\intno\()_\srr1)
	242	mfspr r10, SPRN_SPRG_THREAD
	243	GET_VCPU(r11, r10)
	244	PPC_STL r3, VCPU_GPR(r3)(r11)
	245	mfspr r3, \scratch
	246	PPC_STL r4, VCPU_GPR(r4)(r11)
	247	PPC_LL r4, GPR9(r8)
	248	PPC_STL r5, VCPU_GPR(r5)(r11)
	249	PPC_STL r9, VCPU_CR(r11)
	250	mfspr r5, \srr0
	251	PPC_STL r3, VCPU_GPR(r8)(r11)
	252	PPC_LL r3, GPR10(r8)
	253	PPC_STL r6, VCPU_GPR(r6)(r11)
	254	PPC_STL r4, VCPU_GPR(r9)(r11)
	255	mfspr r6, \srr1
	256	PPC_LL r4, GPR11(r8)
	257	PPC_STL r7, VCPU_GPR(r7)(r11)
	258	PPC_STL r8, VCPU_GPR(r8)(r11)
259	PPC_STL r3, VCPU_GPR(r10)(r11)
260	mfctr r7
261	PPC_STL r12, VCPU_GPR(r12)(r11)
262	PPC_STL r4, VCPU_GPR(r11)(r11)
263	PPC_STL r7, VCPU_CTR(r11)
264	mr r4, r11
265	kvm_handler_common \intno, \srr0, \flags
266	.endm
267
268	kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
269	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
270	kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
271	SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
272	kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
273	SPRN_SRR0, SPRN_SRR1, (NEED_EMU \| NEED_DEAR)
274	kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
275	kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
276	kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
277	SPRN_SRR0, SPRN_SRR1, (NEED_DEAR \| NEED_ESR)
278	kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
279	kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
280	kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
281	kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
282	kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
283	kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
284	kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
285	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
286	kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
287	SPRN_SRR0, SPRN_SRR1, (NEED_EMU \| NEED_DEAR \| NEED_ESR)
288	kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
289	kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
290	kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
291	kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
292	kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
293	kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
294	kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
295	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
296	kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
297	kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
298	kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
299	kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
300	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
301	kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
302	SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
303	kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
304	SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
305
306
307	/* Registers:
308	* SPRG_SCRATCH0: guest r10
309	* r4: vcpu pointer
310	* r11: vcpu->arch.shared
311	* r14: KVM exit number
312	*/
313	_GLOBAL(kvmppc_resume_host)
314	/* Save remaining volatile guest register state to vcpu. */
315	mfspr r3, SPRN_VRSAVE
316	PPC_STL r0, VCPU_GPR(r0)(r4)
d30f6e48 SW	317	mflr r5
d30f6e48 SW	318	mfspr r6, SPRN_SPRG4
d30f6e48 SW	319	PPC_STL r5, VCPU_LR(r4)
	320	mfspr r7, SPRN_SPRG5
	321	PPC_STL r3, VCPU_VRSAVE(r4)
	322	PPC_STL r6, VCPU_SHARED_SPRG4(r11)
	323	mfspr r8, SPRN_SPRG6
	324	PPC_STL r7, VCPU_SHARED_SPRG5(r11)
	325	mfspr r9, SPRN_SPRG7
	326	PPC_STL r8, VCPU_SHARED_SPRG6(r11)
	327	mfxer r3
	328	PPC_STL r9, VCPU_SHARED_SPRG7(r11)
	329
	330	/* save guest MAS registers and restore host mas4 & mas6 */
	331	mfspr r5, SPRN_MAS0
	332	PPC_STL r3, VCPU_XER(r4)
	333	mfspr r6, SPRN_MAS1
	334	stw r5, VCPU_SHARED_MAS0(r11)
	335	mfspr r7, SPRN_MAS2
	336	stw r6, VCPU_SHARED_MAS1(r11)
8764b46e	337	#ifdef CONFIG_64BIT
d30f6e48	338	std r7, (VCPU_SHARED_MAS2)(r11)
8764b46e AG	339	#else
8764b46e AG	340	stw r7, (VCPU_SHARED_MAS2 + 4)(r11)
d30f6e48 SW	341	#endif
	342	mfspr r5, SPRN_MAS3
	343	mfspr r6, SPRN_MAS4
	344	stw r5, VCPU_SHARED_MAS7_3+4(r11)
	345	mfspr r7, SPRN_MAS6
	346	stw r6, VCPU_SHARED_MAS4(r11)
	347	mfspr r5, SPRN_MAS7
	348	lwz r6, VCPU_HOST_MAS4(r4)
	349	stw r7, VCPU_SHARED_MAS6(r11)
	350	lwz r8, VCPU_HOST_MAS6(r4)
	351	mtspr SPRN_MAS4, r6
	352	stw r5, VCPU_SHARED_MAS7_3+0(r11)
	353	mtspr SPRN_MAS6, r8
e9ba39c1	354	/* Enable MAS register updates via exception */
d30f6e48 SW	355	mfspr r3, SPRN_EPCR
	356	rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
	357	mtspr SPRN_EPCR, r3
	358	isync
	359
d30f6e48 SW	360	/* Switch to kernel stack and jump to handler. */
	361	PPC_LL r3, HOST_RUN(r1)
	362	mr r5, r14 /* intno */
	363	mr r14, r4 /* Save vcpu pointer. */
	364	bl kvmppc_handle_exit
	365
	366	/* Restore vcpu pointer and the nonvolatiles we used. */
	367	mr r4, r14
	368	PPC_LL r14, VCPU_GPR(r14)(r4)
	369
	370	andi. r5, r3, RESUME_FLAG_NV
	371	beq skip_nv_load
	372	PPC_LL r15, VCPU_GPR(r15)(r4)
	373	PPC_LL r16, VCPU_GPR(r16)(r4)
	374	PPC_LL r17, VCPU_GPR(r17)(r4)
	375	PPC_LL r18, VCPU_GPR(r18)(r4)
	376	PPC_LL r19, VCPU_GPR(r19)(r4)
	377	PPC_LL r20, VCPU_GPR(r20)(r4)
	378	PPC_LL r21, VCPU_GPR(r21)(r4)
	379	PPC_LL r22, VCPU_GPR(r22)(r4)
	380	PPC_LL r23, VCPU_GPR(r23)(r4)
	381	PPC_LL r24, VCPU_GPR(r24)(r4)
	382	PPC_LL r25, VCPU_GPR(r25)(r4)
	383	PPC_LL r26, VCPU_GPR(r26)(r4)
	384	PPC_LL r27, VCPU_GPR(r27)(r4)
	385	PPC_LL r28, VCPU_GPR(r28)(r4)
	386	PPC_LL r29, VCPU_GPR(r29)(r4)
	387	PPC_LL r30, VCPU_GPR(r30)(r4)
	388	PPC_LL r31, VCPU_GPR(r31)(r4)
	389	skip_nv_load:
	390	/* Should we return to the guest? */
	391	andi. r5, r3, RESUME_FLAG_HOST
	392	beq lightweight_exit
	393
	394	srawi r3, r3, 2 /* Shift -ERR back down. */
	395
	396	heavyweight_exit:
	397	/* Not returning to guest. */
	398	PPC_LL r5, HOST_STACK_LR(r1)
	399
	400	/*
	401	* We already saved guest volatile register state; now save the
	402	* non-volatiles.
	403	*/
	404
	405	PPC_STL r15, VCPU_GPR(r15)(r4)
	406	PPC_STL r16, VCPU_GPR(r16)(r4)
	407	PPC_STL r17, VCPU_GPR(r17)(r4)
	408	PPC_STL r18, VCPU_GPR(r18)(r4)
	409	PPC_STL r19, VCPU_GPR(r19)(r4)
	410	PPC_STL r20, VCPU_GPR(r20)(r4)
	411	PPC_STL r21, VCPU_GPR(r21)(r4)
	412	PPC_STL r22, VCPU_GPR(r22)(r4)
	413	PPC_STL r23, VCPU_GPR(r23)(r4)
	414	PPC_STL r24, VCPU_GPR(r24)(r4)
	415	PPC_STL r25, VCPU_GPR(r25)(r4)
	416	PPC_STL r26, VCPU_GPR(r26)(r4)
	417	PPC_STL r27, VCPU_GPR(r27)(r4)
	418	PPC_STL r28, VCPU_GPR(r28)(r4)
	419	PPC_STL r29, VCPU_GPR(r29)(r4)
	420	PPC_STL r30, VCPU_GPR(r30)(r4)
	421	PPC_STL r31, VCPU_GPR(r31)(r4)
	422
	423	/* Load host non-volatile register state from host stack. */
424	PPC_LL r14, HOST_NV_GPR(r14)(r1)
425	PPC_LL r15, HOST_NV_GPR(r15)(r1)
426	PPC_LL r16, HOST_NV_GPR(r16)(r1)
427	PPC_LL r17, HOST_NV_GPR(r17)(r1)
428	PPC_LL r18, HOST_NV_GPR(r18)(r1)
429	PPC_LL r19, HOST_NV_GPR(r19)(r1)
430	PPC_LL r20, HOST_NV_GPR(r20)(r1)
431	PPC_LL r21, HOST_NV_GPR(r21)(r1)
432	PPC_LL r22, HOST_NV_GPR(r22)(r1)
433	PPC_LL r23, HOST_NV_GPR(r23)(r1)
434	PPC_LL r24, HOST_NV_GPR(r24)(r1)
435	PPC_LL r25, HOST_NV_GPR(r25)(r1)
436	PPC_LL r26, HOST_NV_GPR(r26)(r1)
437	PPC_LL r27, HOST_NV_GPR(r27)(r1)
438	PPC_LL r28, HOST_NV_GPR(r28)(r1)
439	PPC_LL r29, HOST_NV_GPR(r29)(r1)
440	PPC_LL r30, HOST_NV_GPR(r30)(r1)
441	PPC_LL r31, HOST_NV_GPR(r31)(r1)
442
443	/* Return to kvm_vcpu_run(). */
444	mtlr r5
445	addi r1, r1, HOST_STACK_SIZE
446	/* r3 still contains the return code from kvmppc_handle_exit(). */
447	blr
448
449	/* Registers:
450	* r3: kvm_run pointer
451	* r4: vcpu pointer
452	*/
453	_GLOBAL(__kvmppc_vcpu_run)
454	stwu r1, -HOST_STACK_SIZE(r1)
455	PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
456
457	/* Save host state to stack. */
458	PPC_STL r3, HOST_RUN(r1)
459	mflr r3
460	PPC_STL r3, HOST_STACK_LR(r1)
461
462	/* Save host non-volatile register state to stack. */
463	PPC_STL r14, HOST_NV_GPR(r14)(r1)
464	PPC_STL r15, HOST_NV_GPR(r15)(r1)
465	PPC_STL r16, HOST_NV_GPR(r16)(r1)
466	PPC_STL r17, HOST_NV_GPR(r17)(r1)
467	PPC_STL r18, HOST_NV_GPR(r18)(r1)
468	PPC_STL r19, HOST_NV_GPR(r19)(r1)
469	PPC_STL r20, HOST_NV_GPR(r20)(r1)
470	PPC_STL r21, HOST_NV_GPR(r21)(r1)
471	PPC_STL r22, HOST_NV_GPR(r22)(r1)
472	PPC_STL r23, HOST_NV_GPR(r23)(r1)
473	PPC_STL r24, HOST_NV_GPR(r24)(r1)
474	PPC_STL r25, HOST_NV_GPR(r25)(r1)
475	PPC_STL r26, HOST_NV_GPR(r26)(r1)
476	PPC_STL r27, HOST_NV_GPR(r27)(r1)
477	PPC_STL r28, HOST_NV_GPR(r28)(r1)
478	PPC_STL r29, HOST_NV_GPR(r29)(r1)
479	PPC_STL r30, HOST_NV_GPR(r30)(r1)
480	PPC_STL r31, HOST_NV_GPR(r31)(r1)
481
482	/* Load guest non-volatiles. */
483	PPC_LL r14, VCPU_GPR(r14)(r4)
484	PPC_LL r15, VCPU_GPR(r15)(r4)
485	PPC_LL r16, VCPU_GPR(r16)(r4)
486	PPC_LL r17, VCPU_GPR(r17)(r4)
487	PPC_LL r18, VCPU_GPR(r18)(r4)
488	PPC_LL r19, VCPU_GPR(r19)(r4)
489	PPC_LL r20, VCPU_GPR(r20)(r4)
490	PPC_LL r21, VCPU_GPR(r21)(r4)
491	PPC_LL r22, VCPU_GPR(r22)(r4)
492	PPC_LL r23, VCPU_GPR(r23)(r4)
493	PPC_LL r24, VCPU_GPR(r24)(r4)
494	PPC_LL r25, VCPU_GPR(r25)(r4)
495	PPC_LL r26, VCPU_GPR(r26)(r4)
496	PPC_LL r27, VCPU_GPR(r27)(r4)
497	PPC_LL r28, VCPU_GPR(r28)(r4)
498	PPC_LL r29, VCPU_GPR(r29)(r4)
499	PPC_LL r30, VCPU_GPR(r30)(r4)
500	PPC_LL r31, VCPU_GPR(r31)(r4)
501
502
503	lightweight_exit:
504	PPC_STL r2, HOST_R2(r1)
505
506	mfspr r3, SPRN_PID
507	stw r3, VCPU_HOST_PID(r4)
508	lwz r3, VCPU_GUEST_PID(r4)
509	mtspr SPRN_PID, r3
510
d30f6e48	511	PPC_LL r11, VCPU_SHARED(r4)
e9ba39c1 AG	512	/* Disable MAS register updates via exception */
	513	mfspr r3, SPRN_EPCR
	514	oris r3, r3, SPRN_EPCR_DMIUH@h
	515	mtspr SPRN_EPCR, r3
	516	isync
d30f6e48 SW	517	/* Save host mas4 and mas6 and load guest MAS registers */
	518	mfspr r3, SPRN_MAS4
	519	stw r3, VCPU_HOST_MAS4(r4)
	520	mfspr r3, SPRN_MAS6
	521	stw r3, VCPU_HOST_MAS6(r4)
	522	lwz r3, VCPU_SHARED_MAS0(r11)
	523	lwz r5, VCPU_SHARED_MAS1(r11)
8764b46e	524	#ifdef CONFIG_64BIT
d30f6e48	525	ld r6, (VCPU_SHARED_MAS2)(r11)
8764b46e AG	526	#else
8764b46e AG	527	lwz r6, (VCPU_SHARED_MAS2 + 4)(r11)
d30f6e48 SW	528	#endif
	529	lwz r7, VCPU_SHARED_MAS7_3+4(r11)
	530	lwz r8, VCPU_SHARED_MAS4(r11)
	531	mtspr SPRN_MAS0, r3
	532	mtspr SPRN_MAS1, r5
	533	mtspr SPRN_MAS2, r6
	534	mtspr SPRN_MAS3, r7
	535	mtspr SPRN_MAS4, r8
	536	lwz r3, VCPU_SHARED_MAS6(r11)
	537	lwz r5, VCPU_SHARED_MAS7_3+0(r11)
	538	mtspr SPRN_MAS6, r3
	539	mtspr SPRN_MAS7, r5
d30f6e48 SW	540
	541	/*
	542	* Host interrupt handlers may have clobbered these guest-readable
	543	* SPRGs, so we need to reload them here with the guest's values.
	544	*/
	545	lwz r3, VCPU_VRSAVE(r4)
	546	lwz r5, VCPU_SHARED_SPRG4(r11)
	547	mtspr SPRN_VRSAVE, r3
	548	lwz r6, VCPU_SHARED_SPRG5(r11)
	549	mtspr SPRN_SPRG4W, r5
	550	lwz r7, VCPU_SHARED_SPRG6(r11)
	551	mtspr SPRN_SPRG5W, r6
	552	lwz r8, VCPU_SHARED_SPRG7(r11)
	553	mtspr SPRN_SPRG6W, r7
	554	mtspr SPRN_SPRG7W, r8
	555
	556	/* Load some guest volatiles. */
	557	PPC_LL r3, VCPU_LR(r4)
	558	PPC_LL r5, VCPU_XER(r4)
	559	PPC_LL r6, VCPU_CTR(r4)
	560	PPC_LL r7, VCPU_CR(r4)
	561	PPC_LL r8, VCPU_PC(r4)
8764b46e	562	#ifdef CONFIG_64BIT
d30f6e48	563	ld r9, (VCPU_SHARED_MSR)(r11)
8764b46e AG	564	#else
8764b46e AG	565	lwz r9, (VCPU_SHARED_MSR + 4)(r11)
d30f6e48 SW	566	#endif
	567	PPC_LL r0, VCPU_GPR(r0)(r4)
	568	PPC_LL r1, VCPU_GPR(r1)(r4)
	569	PPC_LL r2, VCPU_GPR(r2)(r4)
	570	PPC_LL r10, VCPU_GPR(r10)(r4)
	571	PPC_LL r11, VCPU_GPR(r11)(r4)
	572	PPC_LL r12, VCPU_GPR(r12)(r4)
	573	PPC_LL r13, VCPU_GPR(r13)(r4)
	574	mtlr r3
	575	mtxer r5
	576	mtctr r6
	577	mtcr r7
	578	mtsrr0 r8
	579	mtsrr1 r9
	580
	581	#ifdef CONFIG_KVM_EXIT_TIMING
	582	/* save enter time */
	583	1:
	584	mfspr r6, SPRN_TBRU
	585	mfspr r7, SPRN_TBRL
	586	mfspr r8, SPRN_TBRU
	587	cmpw r8, r6
	588	PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
	589	bne 1b
	590	PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
	591	#endif
	592
	593	/* Finish loading guest volatiles and jump to guest. */
	594	PPC_LL r5, VCPU_GPR(r5)(r4)
	595	PPC_LL r6, VCPU_GPR(r6)(r4)
	596	PPC_LL r7, VCPU_GPR(r7)(r4)
	597	PPC_LL r8, VCPU_GPR(r8)(r4)
	598	PPC_LL r9, VCPU_GPR(r9)(r4)
	599
	600	PPC_LL r3, VCPU_GPR(r3)(r4)
	601	PPC_LL r4, VCPU_GPR(r4)(r4)
	602	rfi