Commit | Line | Data |
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bc8080cb | 1 | /* |
5ce941ee | 2 | * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All rights reserved. |
bc8080cb HB |
3 | * |
4 | * Author: Yu Liu, <yu.liu@freescale.com> | |
5 | * | |
6 | * Description: | |
7 | * This file is derived from arch/powerpc/kvm/44x_emulate.c, | |
8 | * by Hollis Blanchard <hollisb@us.ibm.com>. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License, version 2, as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <asm/kvm_ppc.h> | |
16 | #include <asm/disassemble.h> | |
4ab96919 | 17 | #include <asm/dbell.h> |
bc8080cb HB |
18 | |
19 | #include "booke.h" | |
29a5a6f9 | 20 | #include "e500.h" |
bc8080cb | 21 | |
4ab96919 AG |
22 | #define XOP_MSGSND 206 |
23 | #define XOP_MSGCLR 238 | |
bc8080cb HB |
24 | #define XOP_TLBIVAX 786 |
25 | #define XOP_TLBSX 914 | |
26 | #define XOP_TLBRE 946 | |
27 | #define XOP_TLBWE 978 | |
ab9fc405 | 28 | #define XOP_TLBILX 18 |
bc8080cb | 29 | |
4ab96919 AG |
30 | #ifdef CONFIG_KVM_E500MC |
31 | static int dbell2prio(ulong param) | |
32 | { | |
33 | int msg = param & PPC_DBELL_TYPE_MASK; | |
34 | int prio = -1; | |
35 | ||
36 | switch (msg) { | |
37 | case PPC_DBELL_TYPE(PPC_DBELL): | |
38 | prio = BOOKE_IRQPRIO_DBELL; | |
39 | break; | |
40 | case PPC_DBELL_TYPE(PPC_DBELL_CRIT): | |
41 | prio = BOOKE_IRQPRIO_DBELL_CRIT; | |
42 | break; | |
43 | default: | |
44 | break; | |
45 | } | |
46 | ||
47 | return prio; | |
48 | } | |
49 | ||
50 | static int kvmppc_e500_emul_msgclr(struct kvm_vcpu *vcpu, int rb) | |
51 | { | |
52 | ulong param = vcpu->arch.gpr[rb]; | |
53 | int prio = dbell2prio(param); | |
54 | ||
55 | if (prio < 0) | |
56 | return EMULATE_FAIL; | |
57 | ||
58 | clear_bit(prio, &vcpu->arch.pending_exceptions); | |
59 | return EMULATE_DONE; | |
60 | } | |
61 | ||
62 | static int kvmppc_e500_emul_msgsnd(struct kvm_vcpu *vcpu, int rb) | |
63 | { | |
64 | ulong param = vcpu->arch.gpr[rb]; | |
65 | int prio = dbell2prio(rb); | |
66 | int pir = param & PPC_DBELL_PIR_MASK; | |
67 | int i; | |
68 | struct kvm_vcpu *cvcpu; | |
69 | ||
70 | if (prio < 0) | |
71 | return EMULATE_FAIL; | |
72 | ||
73 | kvm_for_each_vcpu(i, cvcpu, vcpu->kvm) { | |
74 | int cpir = cvcpu->arch.shared->pir; | |
75 | if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { | |
76 | set_bit(prio, &cvcpu->arch.pending_exceptions); | |
77 | kvm_vcpu_kick(cvcpu); | |
78 | } | |
79 | } | |
80 | ||
81 | return EMULATE_DONE; | |
82 | } | |
83 | #endif | |
84 | ||
bc8080cb HB |
85 | int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, |
86 | unsigned int inst, int *advance) | |
87 | { | |
88 | int emulated = EMULATE_DONE; | |
c46dc9a8 AG |
89 | int ra = get_ra(inst); |
90 | int rb = get_rb(inst); | |
91 | int rt = get_rt(inst); | |
bc8080cb HB |
92 | |
93 | switch (get_op(inst)) { | |
94 | case 31: | |
95 | switch (get_xop(inst)) { | |
96 | ||
4ab96919 AG |
97 | #ifdef CONFIG_KVM_E500MC |
98 | case XOP_MSGSND: | |
c46dc9a8 | 99 | emulated = kvmppc_e500_emul_msgsnd(vcpu, rb); |
4ab96919 AG |
100 | break; |
101 | ||
102 | case XOP_MSGCLR: | |
c46dc9a8 | 103 | emulated = kvmppc_e500_emul_msgclr(vcpu, rb); |
4ab96919 AG |
104 | break; |
105 | #endif | |
106 | ||
bc8080cb HB |
107 | case XOP_TLBRE: |
108 | emulated = kvmppc_e500_emul_tlbre(vcpu); | |
109 | break; | |
110 | ||
111 | case XOP_TLBWE: | |
112 | emulated = kvmppc_e500_emul_tlbwe(vcpu); | |
113 | break; | |
114 | ||
115 | case XOP_TLBSX: | |
bc8080cb HB |
116 | emulated = kvmppc_e500_emul_tlbsx(vcpu,rb); |
117 | break; | |
118 | ||
ab9fc405 | 119 | case XOP_TLBILX: |
ab9fc405 SW |
120 | emulated = kvmppc_e500_emul_tlbilx(vcpu, rt, ra, rb); |
121 | break; | |
122 | ||
bc8080cb | 123 | case XOP_TLBIVAX: |
bc8080cb HB |
124 | emulated = kvmppc_e500_emul_tlbivax(vcpu, ra, rb); |
125 | break; | |
126 | ||
127 | default: | |
128 | emulated = EMULATE_FAIL; | |
129 | } | |
130 | ||
131 | break; | |
132 | ||
133 | default: | |
134 | emulated = EMULATE_FAIL; | |
135 | } | |
136 | ||
137 | if (emulated == EMULATE_FAIL) | |
138 | emulated = kvmppc_booke_emulate_op(run, vcpu, inst, advance); | |
139 | ||
140 | return emulated; | |
141 | } | |
142 | ||
143 | int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs) | |
144 | { | |
145 | struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); | |
146 | int emulated = EMULATE_DONE; | |
8e5b26b5 | 147 | ulong spr_val = kvmppc_get_gpr(vcpu, rs); |
bc8080cb HB |
148 | |
149 | switch (sprn) { | |
73196cd3 | 150 | #ifndef CONFIG_KVM_BOOKE_HV |
bc8080cb | 151 | case SPRN_PID: |
5ce941ee | 152 | kvmppc_set_pid(vcpu, spr_val); |
bc8080cb HB |
153 | break; |
154 | case SPRN_PID1: | |
dd9ebf1f LY |
155 | if (spr_val != 0) |
156 | return EMULATE_FAIL; | |
8e5b26b5 | 157 | vcpu_e500->pid[1] = spr_val; break; |
bc8080cb | 158 | case SPRN_PID2: |
dd9ebf1f LY |
159 | if (spr_val != 0) |
160 | return EMULATE_FAIL; | |
8e5b26b5 | 161 | vcpu_e500->pid[2] = spr_val; break; |
bc8080cb | 162 | case SPRN_MAS0: |
b5904972 | 163 | vcpu->arch.shared->mas0 = spr_val; break; |
bc8080cb | 164 | case SPRN_MAS1: |
b5904972 | 165 | vcpu->arch.shared->mas1 = spr_val; break; |
bc8080cb | 166 | case SPRN_MAS2: |
b5904972 | 167 | vcpu->arch.shared->mas2 = spr_val; break; |
bc8080cb | 168 | case SPRN_MAS3: |
b5904972 SW |
169 | vcpu->arch.shared->mas7_3 &= ~(u64)0xffffffff; |
170 | vcpu->arch.shared->mas7_3 |= spr_val; | |
dc83b8bc | 171 | break; |
bc8080cb | 172 | case SPRN_MAS4: |
b5904972 | 173 | vcpu->arch.shared->mas4 = spr_val; break; |
bc8080cb | 174 | case SPRN_MAS6: |
b5904972 | 175 | vcpu->arch.shared->mas6 = spr_val; break; |
bc8080cb | 176 | case SPRN_MAS7: |
b5904972 SW |
177 | vcpu->arch.shared->mas7_3 &= (u64)0xffffffff; |
178 | vcpu->arch.shared->mas7_3 |= (u64)spr_val << 32; | |
dc83b8bc | 179 | break; |
73196cd3 | 180 | #endif |
d86be077 LY |
181 | case SPRN_L1CSR0: |
182 | vcpu_e500->l1csr0 = spr_val; | |
183 | vcpu_e500->l1csr0 &= ~(L1CSR0_DCFI | L1CSR0_CLFC); | |
184 | break; | |
bc8080cb | 185 | case SPRN_L1CSR1: |
8e5b26b5 | 186 | vcpu_e500->l1csr1 = spr_val; break; |
bc8080cb | 187 | case SPRN_HID0: |
8e5b26b5 | 188 | vcpu_e500->hid0 = spr_val; break; |
bc8080cb | 189 | case SPRN_HID1: |
8e5b26b5 | 190 | vcpu_e500->hid1 = spr_val; break; |
bc8080cb | 191 | |
b0a1835d LY |
192 | case SPRN_MMUCSR0: |
193 | emulated = kvmppc_e500_emul_mt_mmucsr0(vcpu_e500, | |
8e5b26b5 | 194 | spr_val); |
b0a1835d LY |
195 | break; |
196 | ||
bb3a8a17 HB |
197 | /* extra exceptions */ |
198 | case SPRN_IVOR32: | |
8e5b26b5 | 199 | vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL] = spr_val; |
bb3a8a17 HB |
200 | break; |
201 | case SPRN_IVOR33: | |
8e5b26b5 | 202 | vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA] = spr_val; |
bb3a8a17 HB |
203 | break; |
204 | case SPRN_IVOR34: | |
8e5b26b5 | 205 | vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND] = spr_val; |
bb3a8a17 HB |
206 | break; |
207 | case SPRN_IVOR35: | |
8e5b26b5 | 208 | vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR] = spr_val; |
bb3a8a17 | 209 | break; |
73196cd3 SW |
210 | #ifdef CONFIG_KVM_BOOKE_HV |
211 | case SPRN_IVOR36: | |
212 | vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL] = spr_val; | |
213 | break; | |
214 | case SPRN_IVOR37: | |
215 | vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT] = spr_val; | |
216 | break; | |
217 | #endif | |
bc8080cb HB |
218 | default: |
219 | emulated = kvmppc_booke_emulate_mtspr(vcpu, sprn, rs); | |
220 | } | |
221 | ||
222 | return emulated; | |
223 | } | |
224 | ||
225 | int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt) | |
226 | { | |
227 | struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu); | |
228 | int emulated = EMULATE_DONE; | |
229 | ||
230 | switch (sprn) { | |
73196cd3 SW |
231 | #ifndef CONFIG_KVM_BOOKE_HV |
232 | unsigned long val; | |
233 | ||
bc8080cb | 234 | case SPRN_PID: |
8e5b26b5 | 235 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->pid[0]); break; |
bc8080cb | 236 | case SPRN_PID1: |
8e5b26b5 | 237 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->pid[1]); break; |
bc8080cb | 238 | case SPRN_PID2: |
8e5b26b5 | 239 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->pid[2]); break; |
bc8080cb | 240 | case SPRN_MAS0: |
b5904972 | 241 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas0); break; |
bc8080cb | 242 | case SPRN_MAS1: |
b5904972 | 243 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas1); break; |
bc8080cb | 244 | case SPRN_MAS2: |
b5904972 | 245 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas2); break; |
bc8080cb | 246 | case SPRN_MAS3: |
b5904972 SW |
247 | val = (u32)vcpu->arch.shared->mas7_3; |
248 | kvmppc_set_gpr(vcpu, rt, val); | |
249 | break; | |
bc8080cb | 250 | case SPRN_MAS4: |
b5904972 | 251 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas4); break; |
bc8080cb | 252 | case SPRN_MAS6: |
b5904972 | 253 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->mas6); break; |
bc8080cb | 254 | case SPRN_MAS7: |
b5904972 SW |
255 | val = vcpu->arch.shared->mas7_3 >> 32; |
256 | kvmppc_set_gpr(vcpu, rt, val); | |
257 | break; | |
73196cd3 | 258 | #endif |
bc8080cb | 259 | case SPRN_TLB0CFG: |
8fdd21a2 | 260 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.tlbcfg[0]); break; |
bc8080cb | 261 | case SPRN_TLB1CFG: |
8fdd21a2 | 262 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.tlbcfg[1]); break; |
d86be077 LY |
263 | case SPRN_L1CSR0: |
264 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->l1csr0); break; | |
bc8080cb | 265 | case SPRN_L1CSR1: |
8e5b26b5 | 266 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->l1csr1); break; |
bc8080cb | 267 | case SPRN_HID0: |
8e5b26b5 | 268 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->hid0); break; |
bc8080cb | 269 | case SPRN_HID1: |
8e5b26b5 | 270 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->hid1); break; |
90d34b0e SW |
271 | case SPRN_SVR: |
272 | kvmppc_set_gpr(vcpu, rt, vcpu_e500->svr); break; | |
bc8080cb | 273 | |
b0a1835d | 274 | case SPRN_MMUCSR0: |
8e5b26b5 | 275 | kvmppc_set_gpr(vcpu, rt, 0); break; |
b0a1835d | 276 | |
06579dd9 | 277 | case SPRN_MMUCFG: |
8fdd21a2 | 278 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.mmucfg); break; |
06579dd9 | 279 | |
bb3a8a17 HB |
280 | /* extra exceptions */ |
281 | case SPRN_IVOR32: | |
8e5b26b5 | 282 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL]); |
bb3a8a17 HB |
283 | break; |
284 | case SPRN_IVOR33: | |
8e5b26b5 | 285 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_DATA]); |
bb3a8a17 HB |
286 | break; |
287 | case SPRN_IVOR34: | |
8e5b26b5 | 288 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_FP_ROUND]); |
bb3a8a17 HB |
289 | break; |
290 | case SPRN_IVOR35: | |
8e5b26b5 | 291 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_PERFORMANCE_MONITOR]); |
bb3a8a17 | 292 | break; |
73196cd3 SW |
293 | #ifdef CONFIG_KVM_BOOKE_HV |
294 | case SPRN_IVOR36: | |
295 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL]); | |
296 | break; | |
297 | case SPRN_IVOR37: | |
298 | kvmppc_set_gpr(vcpu, rt, vcpu->arch.ivor[BOOKE_IRQPRIO_DBELL_CRIT]); | |
299 | break; | |
300 | #endif | |
bc8080cb HB |
301 | default: |
302 | emulated = kvmppc_booke_emulate_mfspr(vcpu, sprn, rt); | |
303 | } | |
304 | ||
305 | return emulated; | |
306 | } | |
307 |