projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 14cf11af PM |
1 | /* |
| 2 | * Modifications by Matt Porter (mporter@mvista.com) to support | |
| 3 | * PPC44x Book E processors. | |
| 4 | * | |
| 5 | * This file contains the routines for initializing the MMU | |
| 6 | * on the 4xx series of chips. | |
| 7 | * -- paulus | |
| 8 | * | |
| 9 | * Derived from arch/ppc/mm/init.c: | |
| 10 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
| 11 | * | |
| 12 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
| 13 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
| 14 | * Copyright (C) 1996 Paul Mackerras | |
| 14cf11af PM |
15 | * |
| 16 | * Derived from "arch/i386/mm/init.c" | |
| 17 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
| 18 | * | |
| 19 | * This program is free software; you can redistribute it and/or | |
| 20 | * modify it under the terms of the GNU General Public License | |
| 21 | * as published by the Free Software Foundation; either version | |
| 22 | * 2 of the License, or (at your option) any later version. | |
| 23 | * | |
| 24 | */ | |
| 25 | ||
| 14cf11af | 26 | #include <linux/init.h> |
| 14cf11af | 27 | #include <asm/mmu.h> |
| 57d7909e DG |
28 | #include <asm/system.h> |
| 29 | #include <asm/page.h> | |
| 14cf11af PM |
30 | |
| 31 | #include "mmu_decl.h" | |
| 32 | ||
| 14cf11af PM |
33 | /* Used by the 44x TLB replacement exception handler. |
| 34 | * Just needed it declared someplace. | |
| 35 | */ | |
| 57d7909e DG |
36 | unsigned int tlb_44x_index; /* = 0 */ |
| 37 | unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS; | |
| b98ac05d | 38 | int icache_44x_need_flush; |
| 14cf11af PM |
39 | |
| 40 | /* | |
| 41 | * "Pins" a 256MB TLB entry in AS0 for kernel lowmem | |
| 42 | */ | |
| 57d7909e | 43 | static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys) |
| 14cf11af | 44 | { |
| 57d7909e DG |
45 | __asm__ __volatile__( |
| 46 | "tlbwe %2,%3,%4\n" | |
| 47 | "tlbwe %1,%3,%5\n" | |
| 48 | "tlbwe %0,%3,%6\n" | |
| 14cf11af | 49 | : |
| 57d7909e DG |
50 | : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), |
| 51 | "r" (phys), | |
| 52 | "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M), | |
| 53 | "r" (tlb_44x_hwater--), /* slot for this TLB entry */ | |
| 14cf11af PM |
54 | "i" (PPC44x_TLB_PAGEID), |
| 55 | "i" (PPC44x_TLB_XLAT), | |
| 56 | "i" (PPC44x_TLB_ATTRIB)); | |
| 57 | } | |
| 58 | ||
| 14cf11af PM |
59 | void __init MMU_init_hw(void) |
| 60 | { | |
| 61 | flush_instruction_cache(); | |
| 62 | } | |
| 63 | ||
| 64 | unsigned long __init mmu_mapin_ram(void) | |
| 65 | { | |
| 57d7909e | 66 | unsigned long addr; |
| 14cf11af | 67 | |
| 57d7909e DG |
68 | /* Pin in enough TLBs to cover any lowmem not covered by the |
| 69 | * initial 256M mapping established in head_44x.S */ | |
| 70 | for (addr = PPC_PIN_SIZE; addr < total_lowmem; | |
| 71 | addr += PPC_PIN_SIZE) | |
| 72 | ppc44x_pin_tlb(addr + PAGE_OFFSET, addr); | |
| 14cf11af PM |
73 | |
| 74 | return total_lowmem; | |
| 75 | } |