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1 | /* |
2 | * arch/ppc/kernel/hashtable.S | |
3 | * | |
4 | * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $ | |
5 | * | |
6 | * PowerPC version | |
7 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
8 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
9 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
10 | * Adapted for Power Macintosh by Paul Mackerras. | |
11 | * Low-level exception handlers and MMU support | |
12 | * rewritten by Paul Mackerras. | |
13 | * Copyright (C) 1996 Paul Mackerras. | |
14 | * | |
15 | * This file contains low-level assembler routines for managing | |
16 | * the PowerPC MMU hash table. (PPC 8xx processors don't use a | |
17 | * hash table, so this file is not used on them.) | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/page.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/cputable.h> | |
31 | #include <asm/ppc_asm.h> | |
32 | #include <asm/thread_info.h> | |
33 | #include <asm/asm-offsets.h> | |
34 | ||
35 | #ifdef CONFIG_SMP | |
36 | .comm mmu_hash_lock,4 | |
37 | #endif /* CONFIG_SMP */ | |
38 | ||
39 | /* | |
40 | * Sync CPUs with hash_page taking & releasing the hash | |
41 | * table lock | |
42 | */ | |
43 | #ifdef CONFIG_SMP | |
44 | .text | |
45 | _GLOBAL(hash_page_sync) | |
46 | lis r8,mmu_hash_lock@h | |
47 | ori r8,r8,mmu_hash_lock@l | |
48 | lis r0,0x0fff | |
49 | b 10f | |
50 | 11: lwz r6,0(r8) | |
51 | cmpwi 0,r6,0 | |
52 | bne 11b | |
53 | 10: lwarx r6,0,r8 | |
54 | cmpwi 0,r6,0 | |
55 | bne- 11b | |
56 | stwcx. r0,0,r8 | |
57 | bne- 10b | |
58 | isync | |
59 | eieio | |
60 | li r0,0 | |
61 | stw r0,0(r8) | |
62 | blr | |
63 | #endif | |
64 | ||
65 | /* | |
66 | * Load a PTE into the hash table, if possible. | |
67 | * The address is in r4, and r3 contains an access flag: | |
68 | * _PAGE_RW (0x400) if a write. | |
69 | * r9 contains the SRR1 value, from which we use the MSR_PR bit. | |
70 | * SPRG3 contains the physical address of the current task's thread. | |
71 | * | |
72 | * Returns to the caller if the access is illegal or there is no | |
73 | * mapping for the address. Otherwise it places an appropriate PTE | |
74 | * in the hash table and returns from the exception. | |
75 | * Uses r0, r3 - r8, ctr, lr. | |
76 | */ | |
77 | .text | |
78 | _GLOBAL(hash_page) | |
79 | #ifdef CONFIG_PPC64BRIDGE | |
80 | mfmsr r0 | |
81 | clrldi r0,r0,1 /* make sure it's in 32-bit mode */ | |
82 | MTMSRD(r0) | |
83 | isync | |
84 | #endif | |
85 | tophys(r7,0) /* gets -KERNELBASE into r7 */ | |
86 | #ifdef CONFIG_SMP | |
87 | addis r8,r7,mmu_hash_lock@h | |
88 | ori r8,r8,mmu_hash_lock@l | |
89 | lis r0,0x0fff | |
90 | b 10f | |
91 | 11: lwz r6,0(r8) | |
92 | cmpwi 0,r6,0 | |
93 | bne 11b | |
94 | 10: lwarx r6,0,r8 | |
95 | cmpwi 0,r6,0 | |
96 | bne- 11b | |
97 | stwcx. r0,0,r8 | |
98 | bne- 10b | |
99 | isync | |
100 | #endif | |
101 | /* Get PTE (linux-style) and check access */ | |
102 | lis r0,KERNELBASE@h /* check if kernel address */ | |
103 | cmplw 0,r4,r0 | |
104 | mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */ | |
105 | ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ | |
106 | lwz r5,PGDIR(r8) /* virt page-table root */ | |
107 | blt+ 112f /* assume user more likely */ | |
108 | lis r5,swapper_pg_dir@ha /* if kernel address, use */ | |
109 | addi r5,r5,swapper_pg_dir@l /* kernel page table */ | |
110 | rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ | |
111 | 112: add r5,r5,r7 /* convert to phys addr */ | |
112 | rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ | |
113 | lwz r8,0(r5) /* get pmd entry */ | |
114 | rlwinm. r8,r8,0,0,19 /* extract address of pte page */ | |
115 | #ifdef CONFIG_SMP | |
116 | beq- hash_page_out /* return if no mapping */ | |
117 | #else | |
118 | /* XXX it seems like the 601 will give a machine fault on the | |
119 | rfi if its alignment is wrong (bottom 4 bits of address are | |
120 | 8 or 0xc) and we have had a not-taken conditional branch | |
121 | to the address following the rfi. */ | |
122 | beqlr- | |
123 | #endif | |
124 | rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ | |
125 | rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ | |
126 | ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE | |
127 | ||
128 | /* | |
129 | * Update the linux PTE atomically. We do the lwarx up-front | |
130 | * because almost always, there won't be a permission violation | |
131 | * and there won't already be an HPTE, and thus we will have | |
132 | * to update the PTE to set _PAGE_HASHPTE. -- paulus. | |
133 | */ | |
134 | retry: | |
135 | lwarx r6,0,r8 /* get linux-style pte */ | |
136 | andc. r5,r3,r6 /* check access & ~permission */ | |
137 | #ifdef CONFIG_SMP | |
138 | bne- hash_page_out /* return if access not permitted */ | |
139 | #else | |
140 | bnelr- | |
141 | #endif | |
142 | or r5,r0,r6 /* set accessed/dirty bits */ | |
143 | stwcx. r5,0,r8 /* attempt to update PTE */ | |
144 | bne- retry /* retry if someone got there first */ | |
145 | ||
146 | mfsrin r3,r4 /* get segment reg for segment */ | |
147 | mfctr r0 | |
148 | stw r0,_CTR(r11) | |
149 | bl create_hpte /* add the hash table entry */ | |
150 | ||
151 | #ifdef CONFIG_SMP | |
152 | eieio | |
153 | addis r8,r7,mmu_hash_lock@ha | |
154 | li r0,0 | |
155 | stw r0,mmu_hash_lock@l(r8) | |
156 | #endif | |
157 | ||
158 | /* Return from the exception */ | |
159 | lwz r5,_CTR(r11) | |
160 | mtctr r5 | |
161 | lwz r0,GPR0(r11) | |
162 | lwz r7,GPR7(r11) | |
163 | lwz r8,GPR8(r11) | |
164 | b fast_exception_return | |
165 | ||
166 | #ifdef CONFIG_SMP | |
167 | hash_page_out: | |
168 | eieio | |
169 | addis r8,r7,mmu_hash_lock@ha | |
170 | li r0,0 | |
171 | stw r0,mmu_hash_lock@l(r8) | |
172 | blr | |
173 | #endif /* CONFIG_SMP */ | |
174 | ||
175 | /* | |
176 | * Add an entry for a particular page to the hash table. | |
177 | * | |
178 | * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) | |
179 | * | |
180 | * We assume any necessary modifications to the pte (e.g. setting | |
181 | * the accessed bit) have already been done and that there is actually | |
182 | * a hash table in use (i.e. we're not on a 603). | |
183 | */ | |
184 | _GLOBAL(add_hash_page) | |
185 | mflr r0 | |
186 | stw r0,4(r1) | |
187 | ||
188 | /* Convert context and va to VSID */ | |
189 | mulli r3,r3,897*16 /* multiply context by context skew */ | |
190 | rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ | |
191 | mulli r0,r0,0x111 /* multiply by ESID skew */ | |
192 | add r3,r3,r0 /* note create_hpte trims to 24 bits */ | |
193 | ||
194 | #ifdef CONFIG_SMP | |
195 | rlwinm r8,r1,0,0,18 /* use cpu number to make tag */ | |
196 | lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ | |
197 | oris r8,r8,12 | |
198 | #endif /* CONFIG_SMP */ | |
199 | ||
200 | /* | |
201 | * We disable interrupts here, even on UP, because we don't | |
202 | * want to race with hash_page, and because we want the | |
203 | * _PAGE_HASHPTE bit to be a reliable indication of whether | |
204 | * the HPTE exists (or at least whether one did once). | |
205 | * We also turn off the MMU for data accesses so that we | |
206 | * we can't take a hash table miss (assuming the code is | |
207 | * covered by a BAT). -- paulus | |
208 | */ | |
209 | mfmsr r10 | |
210 | SYNC | |
211 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
212 | rlwinm r0,r0,0,28,26 /* clear MSR_DR */ | |
213 | mtmsr r0 | |
214 | SYNC_601 | |
215 | isync | |
216 | ||
217 | tophys(r7,0) | |
218 | ||
219 | #ifdef CONFIG_SMP | |
220 | addis r9,r7,mmu_hash_lock@ha | |
221 | addi r9,r9,mmu_hash_lock@l | |
222 | 10: lwarx r0,0,r9 /* take the mmu_hash_lock */ | |
223 | cmpi 0,r0,0 | |
224 | bne- 11f | |
225 | stwcx. r8,0,r9 | |
226 | beq+ 12f | |
227 | 11: lwz r0,0(r9) | |
228 | cmpi 0,r0,0 | |
229 | beq 10b | |
230 | b 11b | |
231 | 12: isync | |
232 | #endif | |
233 | ||
234 | /* | |
235 | * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. | |
236 | * If _PAGE_HASHPTE was already set, we don't replace the existing | |
237 | * HPTE, so we just unlock and return. | |
238 | */ | |
239 | mr r8,r5 | |
240 | rlwimi r8,r4,22,20,29 | |
241 | 1: lwarx r6,0,r8 | |
242 | andi. r0,r6,_PAGE_HASHPTE | |
243 | bne 9f /* if HASHPTE already set, done */ | |
244 | ori r5,r6,_PAGE_HASHPTE | |
245 | stwcx. r5,0,r8 | |
246 | bne- 1b | |
247 | ||
248 | bl create_hpte | |
249 | ||
250 | 9: | |
251 | #ifdef CONFIG_SMP | |
252 | eieio | |
253 | li r0,0 | |
254 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
255 | #endif | |
256 | ||
257 | /* reenable interrupts and DR */ | |
258 | mtmsr r10 | |
259 | SYNC_601 | |
260 | isync | |
261 | ||
262 | lwz r0,4(r1) | |
263 | mtlr r0 | |
264 | blr | |
265 | ||
266 | /* | |
267 | * This routine adds a hardware PTE to the hash table. | |
268 | * It is designed to be called with the MMU either on or off. | |
269 | * r3 contains the VSID, r4 contains the virtual address, | |
270 | * r5 contains the linux PTE, r6 contains the old value of the | |
271 | * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the | |
272 | * offset to be added to addresses (0 if the MMU is on, | |
273 | * -KERNELBASE if it is off). | |
274 | * On SMP, the caller should have the mmu_hash_lock held. | |
275 | * We assume that the caller has (or will) set the _PAGE_HASHPTE | |
276 | * bit in the linux PTE in memory. The value passed in r6 should | |
277 | * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set | |
278 | * this routine will skip the search for an existing HPTE. | |
279 | * This procedure modifies r0, r3 - r6, r8, cr0. | |
280 | * -- paulus. | |
281 | * | |
282 | * For speed, 4 of the instructions get patched once the size and | |
283 | * physical address of the hash table are known. These definitions | |
284 | * of Hash_base and Hash_bits below are just an example. | |
285 | */ | |
286 | Hash_base = 0xc0180000 | |
287 | Hash_bits = 12 /* e.g. 256kB hash table */ | |
288 | Hash_msk = (((1 << Hash_bits) - 1) * 64) | |
289 | ||
290 | #ifndef CONFIG_PPC64BRIDGE | |
291 | /* defines for the PTE format for 32-bit PPCs */ | |
292 | #define PTE_SIZE 8 | |
293 | #define PTEG_SIZE 64 | |
294 | #define LG_PTEG_SIZE 6 | |
295 | #define LDPTEu lwzu | |
296 | #define STPTE stw | |
297 | #define CMPPTE cmpw | |
298 | #define PTE_H 0x40 | |
299 | #define PTE_V 0x80000000 | |
300 | #define TST_V(r) rlwinm. r,r,0,0,0 | |
301 | #define SET_V(r) oris r,r,PTE_V@h | |
302 | #define CLR_V(r,t) rlwinm r,r,0,1,31 | |
303 | ||
304 | #else | |
305 | /* defines for the PTE format for 64-bit PPCs */ | |
306 | #define PTE_SIZE 16 | |
307 | #define PTEG_SIZE 128 | |
308 | #define LG_PTEG_SIZE 7 | |
309 | #define LDPTEu ldu | |
310 | #define STPTE std | |
311 | #define CMPPTE cmpd | |
312 | #define PTE_H 2 | |
313 | #define PTE_V 1 | |
314 | #define TST_V(r) andi. r,r,PTE_V | |
315 | #define SET_V(r) ori r,r,PTE_V | |
316 | #define CLR_V(r,t) li t,PTE_V; andc r,r,t | |
317 | #endif /* CONFIG_PPC64BRIDGE */ | |
318 | ||
319 | #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) | |
320 | #define HASH_RIGHT 31-LG_PTEG_SIZE | |
321 | ||
322 | _GLOBAL(create_hpte) | |
323 | /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ | |
324 | rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ | |
325 | rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ | |
326 | and r8,r8,r0 /* writable if _RW & _DIRTY */ | |
327 | rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ | |
328 | rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ | |
329 | ori r8,r8,0xe14 /* clear out reserved bits and M */ | |
330 | andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ | |
331 | BEGIN_FTR_SECTION | |
332 | ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */ | |
333 | END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT) | |
334 | ||
335 | /* Construct the high word of the PPC-style PTE (r5) */ | |
336 | #ifndef CONFIG_PPC64BRIDGE | |
337 | rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ | |
338 | rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ | |
339 | #else /* CONFIG_PPC64BRIDGE */ | |
340 | clrlwi r3,r3,8 /* reduce vsid to 24 bits */ | |
341 | sldi r5,r3,12 /* shift vsid into position */ | |
342 | rlwimi r5,r4,16,20,24 /* put in API (abbrev page index) */ | |
343 | #endif /* CONFIG_PPC64BRIDGE */ | |
344 | SET_V(r5) /* set V (valid) bit */ | |
345 | ||
346 | /* Get the address of the primary PTE group in the hash table (r3) */ | |
347 | _GLOBAL(hash_page_patch_A) | |
348 | addis r0,r7,Hash_base@h /* base address of hash table */ | |
349 | rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ | |
350 | rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ | |
351 | xor r3,r3,r0 /* make primary hash */ | |
352 | li r0,8 /* PTEs/group */ | |
353 | ||
354 | /* | |
355 | * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search | |
356 | * if it is clear, meaning that the HPTE isn't there already... | |
357 | */ | |
358 | andi. r6,r6,_PAGE_HASHPTE | |
359 | beq+ 10f /* no PTE: go look for an empty slot */ | |
360 | tlbie r4 | |
361 | ||
362 | addis r4,r7,htab_hash_searches@ha | |
363 | lwz r6,htab_hash_searches@l(r4) | |
364 | addi r6,r6,1 /* count how many searches we do */ | |
365 | stw r6,htab_hash_searches@l(r4) | |
366 | ||
367 | /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ | |
368 | mtctr r0 | |
369 | addi r4,r3,-PTE_SIZE | |
370 | 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ | |
371 | CMPPTE 0,r6,r5 | |
372 | bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ | |
373 | beq+ found_slot | |
374 | ||
375 | /* Search the secondary PTEG for a matching PTE */ | |
376 | ori r5,r5,PTE_H /* set H (secondary hash) bit */ | |
377 | _GLOBAL(hash_page_patch_B) | |
378 | xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ | |
379 | xori r4,r4,(-PTEG_SIZE & 0xffff) | |
380 | addi r4,r4,-PTE_SIZE | |
381 | mtctr r0 | |
382 | 2: LDPTEu r6,PTE_SIZE(r4) | |
383 | CMPPTE 0,r6,r5 | |
384 | bdnzf 2,2b | |
385 | beq+ found_slot | |
386 | xori r5,r5,PTE_H /* clear H bit again */ | |
387 | ||
388 | /* Search the primary PTEG for an empty slot */ | |
389 | 10: mtctr r0 | |
390 | addi r4,r3,-PTE_SIZE /* search primary PTEG */ | |
391 | 1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ | |
392 | TST_V(r6) /* test valid bit */ | |
393 | bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ | |
394 | beq+ found_empty | |
395 | ||
396 | /* update counter of times that the primary PTEG is full */ | |
397 | addis r4,r7,primary_pteg_full@ha | |
398 | lwz r6,primary_pteg_full@l(r4) | |
399 | addi r6,r6,1 | |
400 | stw r6,primary_pteg_full@l(r4) | |
401 | ||
402 | /* Search the secondary PTEG for an empty slot */ | |
403 | ori r5,r5,PTE_H /* set H (secondary hash) bit */ | |
404 | _GLOBAL(hash_page_patch_C) | |
405 | xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ | |
406 | xori r4,r4,(-PTEG_SIZE & 0xffff) | |
407 | addi r4,r4,-PTE_SIZE | |
408 | mtctr r0 | |
409 | 2: LDPTEu r6,PTE_SIZE(r4) | |
410 | TST_V(r6) | |
411 | bdnzf 2,2b | |
412 | beq+ found_empty | |
413 | xori r5,r5,PTE_H /* clear H bit again */ | |
414 | ||
415 | /* | |
416 | * Choose an arbitrary slot in the primary PTEG to overwrite. | |
417 | * Since both the primary and secondary PTEGs are full, and we | |
418 | * have no information that the PTEs in the primary PTEG are | |
419 | * more important or useful than those in the secondary PTEG, | |
420 | * and we know there is a definite (although small) speed | |
421 | * advantage to putting the PTE in the primary PTEG, we always | |
422 | * put the PTE in the primary PTEG. | |
423 | */ | |
424 | addis r4,r7,next_slot@ha | |
425 | lwz r6,next_slot@l(r4) | |
426 | addi r6,r6,PTE_SIZE | |
427 | andi. r6,r6,7*PTE_SIZE | |
428 | stw r6,next_slot@l(r4) | |
429 | add r4,r3,r6 | |
430 | ||
431 | #ifndef CONFIG_SMP | |
432 | /* Store PTE in PTEG */ | |
433 | found_empty: | |
434 | STPTE r5,0(r4) | |
435 | found_slot: | |
436 | STPTE r8,PTE_SIZE/2(r4) | |
437 | ||
438 | #else /* CONFIG_SMP */ | |
439 | /* | |
440 | * Between the tlbie above and updating the hash table entry below, | |
441 | * another CPU could read the hash table entry and put it in its TLB. | |
442 | * There are 3 cases: | |
443 | * 1. using an empty slot | |
444 | * 2. updating an earlier entry to change permissions (i.e. enable write) | |
445 | * 3. taking over the PTE for an unrelated address | |
446 | * | |
447 | * In each case it doesn't really matter if the other CPUs have the old | |
448 | * PTE in their TLB. So we don't need to bother with another tlbie here, | |
449 | * which is convenient as we've overwritten the register that had the | |
450 | * address. :-) The tlbie above is mainly to make sure that this CPU comes | |
451 | * and gets the new PTE from the hash table. | |
452 | * | |
453 | * We do however have to make sure that the PTE is never in an invalid | |
454 | * state with the V bit set. | |
455 | */ | |
456 | found_empty: | |
457 | found_slot: | |
458 | CLR_V(r5,r0) /* clear V (valid) bit in PTE */ | |
459 | STPTE r5,0(r4) | |
460 | sync | |
461 | TLBSYNC | |
462 | STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ | |
463 | sync | |
464 | SET_V(r5) | |
465 | STPTE r5,0(r4) /* finally set V bit in PTE */ | |
466 | #endif /* CONFIG_SMP */ | |
467 | ||
468 | sync /* make sure pte updates get to memory */ | |
469 | blr | |
470 | ||
471 | .comm next_slot,4 | |
472 | .comm primary_pteg_full,4 | |
473 | .comm htab_hash_searches,4 | |
474 | ||
475 | /* | |
476 | * Flush the entry for a particular page from the hash table. | |
477 | * | |
478 | * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, | |
479 | * int count) | |
480 | * | |
481 | * We assume that there is a hash table in use (Hash != 0). | |
482 | */ | |
483 | _GLOBAL(flush_hash_pages) | |
484 | tophys(r7,0) | |
485 | ||
486 | /* | |
487 | * We disable interrupts here, even on UP, because we want | |
488 | * the _PAGE_HASHPTE bit to be a reliable indication of | |
489 | * whether the HPTE exists (or at least whether one did once). | |
490 | * We also turn off the MMU for data accesses so that we | |
491 | * we can't take a hash table miss (assuming the code is | |
492 | * covered by a BAT). -- paulus | |
493 | */ | |
494 | mfmsr r10 | |
495 | SYNC | |
496 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
497 | rlwinm r0,r0,0,28,26 /* clear MSR_DR */ | |
498 | mtmsr r0 | |
499 | SYNC_601 | |
500 | isync | |
501 | ||
502 | /* First find a PTE in the range that has _PAGE_HASHPTE set */ | |
503 | rlwimi r5,r4,22,20,29 | |
504 | 1: lwz r0,0(r5) | |
505 | cmpwi cr1,r6,1 | |
506 | andi. r0,r0,_PAGE_HASHPTE | |
507 | bne 2f | |
508 | ble cr1,19f | |
509 | addi r4,r4,0x1000 | |
510 | addi r5,r5,4 | |
511 | addi r6,r6,-1 | |
512 | b 1b | |
513 | ||
514 | /* Convert context and va to VSID */ | |
515 | 2: mulli r3,r3,897*16 /* multiply context by context skew */ | |
516 | rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ | |
517 | mulli r0,r0,0x111 /* multiply by ESID skew */ | |
518 | add r3,r3,r0 /* note code below trims to 24 bits */ | |
519 | ||
520 | /* Construct the high word of the PPC-style PTE (r11) */ | |
521 | #ifndef CONFIG_PPC64BRIDGE | |
522 | rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ | |
523 | rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ | |
524 | #else /* CONFIG_PPC64BRIDGE */ | |
525 | clrlwi r3,r3,8 /* reduce vsid to 24 bits */ | |
526 | sldi r11,r3,12 /* shift vsid into position */ | |
527 | rlwimi r11,r4,16,20,24 /* put in API (abbrev page index) */ | |
528 | #endif /* CONFIG_PPC64BRIDGE */ | |
529 | SET_V(r11) /* set V (valid) bit */ | |
530 | ||
531 | #ifdef CONFIG_SMP | |
532 | addis r9,r7,mmu_hash_lock@ha | |
533 | addi r9,r9,mmu_hash_lock@l | |
534 | rlwinm r8,r1,0,0,18 | |
535 | add r8,r8,r7 | |
536 | lwz r8,TI_CPU(r8) | |
537 | oris r8,r8,9 | |
538 | 10: lwarx r0,0,r9 | |
539 | cmpi 0,r0,0 | |
540 | bne- 11f | |
541 | stwcx. r8,0,r9 | |
542 | beq+ 12f | |
543 | 11: lwz r0,0(r9) | |
544 | cmpi 0,r0,0 | |
545 | beq 10b | |
546 | b 11b | |
547 | 12: isync | |
548 | #endif | |
549 | ||
550 | /* | |
551 | * Check the _PAGE_HASHPTE bit in the linux PTE. If it is | |
552 | * already clear, we're done (for this pte). If not, | |
553 | * clear it (atomically) and proceed. -- paulus. | |
554 | */ | |
555 | 33: lwarx r8,0,r5 /* fetch the pte */ | |
556 | andi. r0,r8,_PAGE_HASHPTE | |
557 | beq 8f /* done if HASHPTE is already clear */ | |
558 | rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ | |
559 | stwcx. r8,0,r5 /* update the pte */ | |
560 | bne- 33b | |
561 | ||
562 | /* Get the address of the primary PTE group in the hash table (r3) */ | |
563 | _GLOBAL(flush_hash_patch_A) | |
564 | addis r8,r7,Hash_base@h /* base address of hash table */ | |
565 | rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ | |
566 | rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ | |
567 | xor r8,r0,r8 /* make primary hash */ | |
568 | ||
569 | /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ | |
570 | li r0,8 /* PTEs/group */ | |
571 | mtctr r0 | |
572 | addi r12,r8,-PTE_SIZE | |
573 | 1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */ | |
574 | CMPPTE 0,r0,r11 | |
575 | bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ | |
576 | beq+ 3f | |
577 | ||
578 | /* Search the secondary PTEG for a matching PTE */ | |
579 | ori r11,r11,PTE_H /* set H (secondary hash) bit */ | |
580 | li r0,8 /* PTEs/group */ | |
581 | _GLOBAL(flush_hash_patch_B) | |
582 | xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ | |
583 | xori r12,r12,(-PTEG_SIZE & 0xffff) | |
584 | addi r12,r12,-PTE_SIZE | |
585 | mtctr r0 | |
586 | 2: LDPTEu r0,PTE_SIZE(r12) | |
587 | CMPPTE 0,r0,r11 | |
588 | bdnzf 2,2b | |
589 | xori r11,r11,PTE_H /* clear H again */ | |
590 | bne- 4f /* should rarely fail to find it */ | |
591 | ||
592 | 3: li r0,0 | |
593 | STPTE r0,0(r12) /* invalidate entry */ | |
594 | 4: sync | |
595 | tlbie r4 /* in hw tlb too */ | |
596 | sync | |
597 | ||
598 | 8: ble cr1,9f /* if all ptes checked */ | |
599 | 81: addi r6,r6,-1 | |
600 | addi r5,r5,4 /* advance to next pte */ | |
601 | addi r4,r4,0x1000 | |
602 | lwz r0,0(r5) /* check next pte */ | |
603 | cmpwi cr1,r6,1 | |
604 | andi. r0,r0,_PAGE_HASHPTE | |
605 | bne 33b | |
606 | bgt cr1,81b | |
607 | ||
608 | 9: | |
609 | #ifdef CONFIG_SMP | |
610 | TLBSYNC | |
611 | li r0,0 | |
612 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
613 | #endif | |
614 | ||
615 | 19: mtmsr r10 | |
616 | SYNC_601 | |
617 | isync | |
618 | blr |