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1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 LT |
23 | |
24 | #include <linux/config.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/stat.h> | |
30 | #include <linux/sysctl.h> | |
31 | #include <linux/ctype.h> | |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
35 | ||
1da177e4 LT |
36 | #include <asm/processor.h> |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/mmu.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/page.h> | |
41 | #include <asm/types.h> | |
42 | #include <asm/system.h> | |
43 | #include <asm/uaccess.h> | |
44 | #include <asm/machdep.h> | |
45 | #include <asm/lmb.h> | |
46 | #include <asm/abs_addr.h> | |
47 | #include <asm/tlbflush.h> | |
48 | #include <asm/io.h> | |
49 | #include <asm/eeh.h> | |
50 | #include <asm/tlb.h> | |
51 | #include <asm/cacheflush.h> | |
52 | #include <asm/cputable.h> | |
53 | #include <asm/abs_addr.h> | |
54 | #include <asm/sections.h> | |
55 | ||
56 | #ifdef DEBUG | |
57 | #define DBG(fmt...) udbg_printf(fmt) | |
58 | #else | |
59 | #define DBG(fmt...) | |
60 | #endif | |
61 | ||
3c726f8d BH |
62 | #ifdef DEBUG_LOW |
63 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
64 | #else | |
65 | #define DBG_LOW(fmt...) | |
66 | #endif | |
67 | ||
68 | #define KB (1024) | |
69 | #define MB (1024*KB) | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Note: pte --> Linux PTE | |
73 | * HPTE --> PowerPC Hashed Page Table Entry | |
74 | * | |
75 | * Execution context: | |
76 | * htab_initialize is called with the MMU off (of course), but | |
77 | * the kernel has been copied down to zero so it can directly | |
78 | * reference global data. At this point it is very difficult | |
79 | * to print debug info. | |
80 | * | |
81 | */ | |
82 | ||
83 | #ifdef CONFIG_U3_DART | |
84 | extern unsigned long dart_tablebase; | |
85 | #endif /* CONFIG_U3_DART */ | |
86 | ||
96e28449 DG |
87 | hpte_t *htab_address; |
88 | unsigned long htab_hash_mask; | |
ab1f9dac | 89 | unsigned long _SDR1; |
3c726f8d BH |
90 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; |
91 | int mmu_linear_psize = MMU_PAGE_4K; | |
92 | int mmu_virtual_psize = MMU_PAGE_4K; | |
93 | #ifdef CONFIG_HUGETLB_PAGE | |
94 | int mmu_huge_psize = MMU_PAGE_16M; | |
95 | unsigned int HPAGE_SHIFT; | |
96 | #endif | |
1da177e4 | 97 | |
3c726f8d BH |
98 | /* There are definitions of page sizes arrays to be used when none |
99 | * is provided by the firmware. | |
100 | */ | |
1da177e4 | 101 | |
3c726f8d BH |
102 | /* Pre-POWER4 CPUs (4k pages only) |
103 | */ | |
104 | struct mmu_psize_def mmu_psize_defaults_old[] = { | |
105 | [MMU_PAGE_4K] = { | |
106 | .shift = 12, | |
107 | .sllp = 0, | |
108 | .penc = 0, | |
109 | .avpnm = 0, | |
110 | .tlbiel = 0, | |
111 | }, | |
112 | }; | |
113 | ||
114 | /* POWER4, GPUL, POWER5 | |
115 | * | |
116 | * Support for 16Mb large pages | |
117 | */ | |
118 | struct mmu_psize_def mmu_psize_defaults_gp[] = { | |
119 | [MMU_PAGE_4K] = { | |
120 | .shift = 12, | |
121 | .sllp = 0, | |
122 | .penc = 0, | |
123 | .avpnm = 0, | |
124 | .tlbiel = 1, | |
125 | }, | |
126 | [MMU_PAGE_16M] = { | |
127 | .shift = 24, | |
128 | .sllp = SLB_VSID_L, | |
129 | .penc = 0, | |
130 | .avpnm = 0x1UL, | |
131 | .tlbiel = 0, | |
132 | }, | |
133 | }; | |
134 | ||
135 | ||
136 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
137 | unsigned long pstart, unsigned long mode, int psize) | |
1da177e4 | 138 | { |
3c726f8d BH |
139 | unsigned long vaddr, paddr; |
140 | unsigned int step, shift; | |
1da177e4 | 141 | unsigned long tmp_mode; |
3c726f8d | 142 | int ret = 0; |
1da177e4 | 143 | |
3c726f8d BH |
144 | shift = mmu_psize_defs[psize].shift; |
145 | step = 1 << shift; | |
1da177e4 | 146 | |
3c726f8d BH |
147 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
148 | vaddr += step, paddr += step) { | |
1da177e4 | 149 | unsigned long vpn, hash, hpteg; |
3c726f8d BH |
150 | unsigned long vsid = get_kernel_vsid(vaddr); |
151 | unsigned long va = (vsid << 28) | (vaddr & 0x0fffffff); | |
1da177e4 | 152 | |
3c726f8d | 153 | vpn = va >> shift; |
1da177e4 LT |
154 | tmp_mode = mode; |
155 | ||
156 | /* Make non-kernel text non-executable */ | |
3c726f8d BH |
157 | if (!in_kernel_text(vaddr)) |
158 | tmp_mode = mode | HPTE_R_N; | |
1da177e4 | 159 | |
3c726f8d | 160 | hash = hpt_hash(va, shift); |
1da177e4 LT |
161 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
162 | ||
3c726f8d BH |
163 | /* The crap below can be cleaned once ppd_md.probe() can |
164 | * set up the hash callbacks, thus we can just used the | |
165 | * normal insert callback here. | |
166 | */ | |
4c55130b | 167 | #ifdef CONFIG_PPC_ISERIES |
3c726f8d BH |
168 | if (systemcfg->platform == PLATFORM_ISERIES_LPAR) |
169 | ret = iSeries_hpte_insert(hpteg, va, | |
170 | virt_to_abs(paddr), | |
171 | tmp_mode, | |
172 | HPTE_V_BOLTED, | |
173 | psize); | |
4c55130b ME |
174 | else |
175 | #endif | |
1da177e4 LT |
176 | #ifdef CONFIG_PPC_PSERIES |
177 | if (systemcfg->platform & PLATFORM_LPAR) | |
178 | ret = pSeries_lpar_hpte_insert(hpteg, va, | |
3c726f8d BH |
179 | virt_to_abs(paddr), |
180 | tmp_mode, | |
181 | HPTE_V_BOLTED, | |
182 | psize); | |
1da177e4 | 183 | else |
4c55130b ME |
184 | #endif |
185 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1da177e4 | 186 | ret = native_hpte_insert(hpteg, va, |
3c726f8d BH |
187 | virt_to_abs(paddr), |
188 | tmp_mode, HPTE_V_BOLTED, | |
189 | psize); | |
4c55130b | 190 | #endif |
3c726f8d BH |
191 | if (ret < 0) |
192 | break; | |
193 | } | |
194 | return ret < 0 ? ret : 0; | |
195 | } | |
1da177e4 | 196 | |
3c726f8d BH |
197 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
198 | const char *uname, int depth, | |
199 | void *data) | |
200 | { | |
201 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
202 | u32 *prop; | |
203 | unsigned long size = 0; | |
204 | ||
205 | /* We are scanning "cpu" nodes only */ | |
206 | if (type == NULL || strcmp(type, "cpu") != 0) | |
207 | return 0; | |
208 | ||
209 | prop = (u32 *)of_get_flat_dt_prop(node, | |
210 | "ibm,segment-page-sizes", &size); | |
211 | if (prop != NULL) { | |
212 | DBG("Page sizes from device-tree:\n"); | |
213 | size /= 4; | |
214 | cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE); | |
215 | while(size > 0) { | |
216 | unsigned int shift = prop[0]; | |
217 | unsigned int slbenc = prop[1]; | |
218 | unsigned int lpnum = prop[2]; | |
219 | unsigned int lpenc = 0; | |
220 | struct mmu_psize_def *def; | |
221 | int idx = -1; | |
222 | ||
223 | size -= 3; prop += 3; | |
224 | while(size > 0 && lpnum) { | |
225 | if (prop[0] == shift) | |
226 | lpenc = prop[1]; | |
227 | prop += 2; size -= 2; | |
228 | lpnum--; | |
229 | } | |
230 | switch(shift) { | |
231 | case 0xc: | |
232 | idx = MMU_PAGE_4K; | |
233 | break; | |
234 | case 0x10: | |
235 | idx = MMU_PAGE_64K; | |
236 | break; | |
237 | case 0x14: | |
238 | idx = MMU_PAGE_1M; | |
239 | break; | |
240 | case 0x18: | |
241 | idx = MMU_PAGE_16M; | |
242 | cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE; | |
243 | break; | |
244 | case 0x22: | |
245 | idx = MMU_PAGE_16G; | |
246 | break; | |
247 | } | |
248 | if (idx < 0) | |
249 | continue; | |
250 | def = &mmu_psize_defs[idx]; | |
251 | def->shift = shift; | |
252 | if (shift <= 23) | |
253 | def->avpnm = 0; | |
254 | else | |
255 | def->avpnm = (1 << (shift - 23)) - 1; | |
256 | def->sllp = slbenc; | |
257 | def->penc = lpenc; | |
258 | /* We don't know for sure what's up with tlbiel, so | |
259 | * for now we only set it for 4K and 64K pages | |
260 | */ | |
261 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
262 | def->tlbiel = 1; | |
263 | else | |
264 | def->tlbiel = 0; | |
265 | ||
266 | DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, " | |
267 | "tlbiel=%d, penc=%d\n", | |
268 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
269 | def->penc); | |
1da177e4 | 270 | } |
3c726f8d BH |
271 | return 1; |
272 | } | |
273 | return 0; | |
274 | } | |
275 | ||
276 | ||
277 | static void __init htab_init_page_sizes(void) | |
278 | { | |
279 | int rc; | |
280 | ||
281 | /* Default to 4K pages only */ | |
282 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
283 | sizeof(mmu_psize_defaults_old)); | |
284 | ||
285 | /* | |
286 | * Try to find the available page sizes in the device-tree | |
287 | */ | |
288 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
289 | if (rc != 0) /* Found */ | |
290 | goto found; | |
291 | ||
292 | /* | |
293 | * Not in the device-tree, let's fallback on known size | |
294 | * list for 16M capable GP & GR | |
295 | */ | |
296 | if ((systemcfg->platform != PLATFORM_ISERIES_LPAR) && | |
297 | cpu_has_feature(CPU_FTR_16M_PAGE)) | |
298 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, | |
299 | sizeof(mmu_psize_defaults_gp)); | |
300 | found: | |
301 | /* | |
302 | * Pick a size for the linear mapping. Currently, we only support | |
303 | * 16M, 1M and 4K which is the default | |
304 | */ | |
305 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
306 | mmu_linear_psize = MMU_PAGE_16M; | |
307 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
308 | mmu_linear_psize = MMU_PAGE_1M; | |
309 | ||
310 | /* | |
311 | * Pick a size for the ordinary pages. Default is 4K, we support | |
312 | * 64K if cache inhibited large pages are supported by the | |
313 | * processor | |
314 | */ | |
315 | #ifdef CONFIG_PPC_64K_PAGES | |
316 | if (mmu_psize_defs[MMU_PAGE_64K].shift && | |
317 | cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) | |
318 | mmu_virtual_psize = MMU_PAGE_64K; | |
319 | #endif | |
320 | ||
321 | printk(KERN_INFO "Page orders: linear mapping = %d, others = %d\n", | |
322 | mmu_psize_defs[mmu_linear_psize].shift, | |
323 | mmu_psize_defs[mmu_virtual_psize].shift); | |
324 | ||
325 | #ifdef CONFIG_HUGETLB_PAGE | |
326 | /* Init large page size. Currently, we pick 16M or 1M depending | |
327 | * on what is available | |
328 | */ | |
329 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
330 | mmu_huge_psize = MMU_PAGE_16M; | |
7d24f0b8 DG |
331 | /* With 4k/4level pagetables, we can't (for now) cope with a |
332 | * huge page size < PMD_SIZE */ | |
3c726f8d BH |
333 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) |
334 | mmu_huge_psize = MMU_PAGE_1M; | |
335 | ||
336 | /* Calculate HPAGE_SHIFT and sanity check it */ | |
7d24f0b8 DG |
337 | if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT && |
338 | mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT) | |
3c726f8d BH |
339 | HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift; |
340 | else | |
341 | HPAGE_SHIFT = 0; /* No huge pages dude ! */ | |
342 | #endif /* CONFIG_HUGETLB_PAGE */ | |
343 | } | |
344 | ||
345 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
346 | const char *uname, int depth, | |
347 | void *data) | |
348 | { | |
349 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
350 | u32 *prop; | |
351 | ||
352 | /* We are scanning "cpu" nodes only */ | |
353 | if (type == NULL || strcmp(type, "cpu") != 0) | |
354 | return 0; | |
355 | ||
356 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
357 | if (prop != NULL) { | |
358 | /* pft_size[0] is the NUMA CEC cookie */ | |
359 | ppc64_pft_size = prop[1]; | |
360 | return 1; | |
1da177e4 | 361 | } |
3c726f8d | 362 | return 0; |
1da177e4 LT |
363 | } |
364 | ||
3c726f8d | 365 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 PM |
366 | { |
367 | unsigned long rnd_mem_size, pteg_count; | |
368 | ||
3c726f8d BH |
369 | /* If hash size isn't already provided by the platform, we try to |
370 | * retreive it from the device-tree. If it's not there neither, we | |
371 | * calculate it now based on the total RAM size | |
3eac8c69 | 372 | */ |
3c726f8d BH |
373 | if (ppc64_pft_size == 0) |
374 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
375 | if (ppc64_pft_size) |
376 | return 1UL << ppc64_pft_size; | |
377 | ||
378 | /* round mem_size up to next power of 2 */ | |
379 | rnd_mem_size = 1UL << __ilog2(systemcfg->physicalMemorySize); | |
380 | if (rnd_mem_size < systemcfg->physicalMemorySize) | |
381 | rnd_mem_size <<= 1; | |
382 | ||
383 | /* # pages / 2 */ | |
384 | pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11); | |
385 | ||
386 | return pteg_count << 7; | |
387 | } | |
388 | ||
1da177e4 LT |
389 | void __init htab_initialize(void) |
390 | { | |
391 | unsigned long table, htab_size_bytes; | |
392 | unsigned long pteg_count; | |
393 | unsigned long mode_rw; | |
1da177e4 | 394 | unsigned long base = 0, size = 0; |
3c726f8d BH |
395 | int i; |
396 | ||
1da177e4 LT |
397 | extern unsigned long tce_alloc_start, tce_alloc_end; |
398 | ||
399 | DBG(" -> htab_initialize()\n"); | |
400 | ||
3c726f8d BH |
401 | /* Initialize page sizes */ |
402 | htab_init_page_sizes(); | |
403 | ||
1da177e4 LT |
404 | /* |
405 | * Calculate the required size of the htab. We want the number of | |
406 | * PTEGs to equal one half the number of real pages. | |
407 | */ | |
3c726f8d | 408 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
409 | pteg_count = htab_size_bytes >> 7; |
410 | ||
1da177e4 LT |
411 | htab_hash_mask = pteg_count - 1; |
412 | ||
413 | if (systemcfg->platform & PLATFORM_LPAR) { | |
414 | /* Using a hypervisor which owns the htab */ | |
415 | htab_address = NULL; | |
416 | _SDR1 = 0; | |
417 | } else { | |
418 | /* Find storage for the HPT. Must be contiguous in | |
419 | * the absolute address space. | |
420 | */ | |
421 | table = lmb_alloc(htab_size_bytes, htab_size_bytes); | |
3c726f8d | 422 | BUG_ON(table == 0); |
1da177e4 LT |
423 | |
424 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
425 | htab_size_bytes); | |
426 | ||
1da177e4 LT |
427 | htab_address = abs_to_virt(table); |
428 | ||
429 | /* htab absolute addr + encoded htabsize */ | |
430 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
431 | ||
432 | /* Initialize the HPT with no entries */ | |
433 | memset((void *)table, 0, htab_size_bytes); | |
434 | } | |
435 | ||
515bae9c | 436 | mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX; |
1da177e4 LT |
437 | |
438 | /* On U3 based machines, we need to reserve the DART area and | |
439 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
440 | * cacheable later on | |
441 | */ | |
1da177e4 LT |
442 | |
443 | /* create bolted the linear mapping in the hash table */ | |
444 | for (i=0; i < lmb.memory.cnt; i++) { | |
180379dc | 445 | base = lmb.memory.region[i].base + KERNELBASE; |
1da177e4 LT |
446 | size = lmb.memory.region[i].size; |
447 | ||
448 | DBG("creating mapping for region: %lx : %lx\n", base, size); | |
449 | ||
450 | #ifdef CONFIG_U3_DART | |
451 | /* Do not map the DART space. Fortunately, it will be aligned | |
3c726f8d BH |
452 | * in such a way that it will not cross two lmb regions and |
453 | * will fit within a single 16Mb page. | |
454 | * The DART space is assumed to be a full 16Mb region even if | |
455 | * we only use 2Mb of that space. We will use more of it later | |
456 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
457 | */ |
458 | DBG("DART base: %lx\n", dart_tablebase); | |
459 | ||
460 | if (dart_tablebase != 0 && dart_tablebase >= base | |
461 | && dart_tablebase < (base + size)) { | |
462 | if (base != dart_tablebase) | |
3c726f8d BH |
463 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
464 | base, mode_rw, | |
465 | mmu_linear_psize)); | |
1da177e4 | 466 | if ((base + size) > (dart_tablebase + 16*MB)) |
3c726f8d BH |
467 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
468 | base + size, | |
469 | dart_tablebase+16*MB, | |
470 | mode_rw, | |
471 | mmu_linear_psize)); | |
1da177e4 LT |
472 | continue; |
473 | } | |
474 | #endif /* CONFIG_U3_DART */ | |
3c726f8d BH |
475 | BUG_ON(htab_bolt_mapping(base, base + size, base, |
476 | mode_rw, mmu_linear_psize)); | |
477 | } | |
1da177e4 LT |
478 | |
479 | /* | |
480 | * If we have a memory_limit and we've allocated TCEs then we need to | |
481 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
482 | * case that the TCEs start below memory_limit. | |
483 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
484 | * for either 4K or 16MB pages. | |
485 | */ | |
486 | if (tce_alloc_start) { | |
487 | tce_alloc_start += KERNELBASE; | |
488 | tce_alloc_end += KERNELBASE; | |
489 | ||
490 | if (base + size >= tce_alloc_start) | |
491 | tce_alloc_start = base + size + 1; | |
492 | ||
3c726f8d BH |
493 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
494 | tce_alloc_start, mode_rw, | |
495 | mmu_linear_psize)); | |
1da177e4 LT |
496 | } |
497 | ||
498 | DBG(" <- htab_initialize()\n"); | |
499 | } | |
500 | #undef KB | |
501 | #undef MB | |
1da177e4 LT |
502 | |
503 | /* | |
504 | * Called by asm hashtable.S for doing lazy icache flush | |
505 | */ | |
506 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
507 | { | |
508 | struct page *page; | |
509 | ||
76c8e25b BH |
510 | if (!pfn_valid(pte_pfn(pte))) |
511 | return pp; | |
512 | ||
1da177e4 LT |
513 | page = pte_page(pte); |
514 | ||
515 | /* page is dirty */ | |
516 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
517 | if (trap == 0x400) { | |
518 | __flush_dcache_icache(page_address(page)); | |
519 | set_bit(PG_arch_1, &page->flags); | |
520 | } else | |
3c726f8d | 521 | pp |= HPTE_R_N; |
1da177e4 LT |
522 | } |
523 | return pp; | |
524 | } | |
525 | ||
526 | /* Result code is: | |
527 | * 0 - handled | |
528 | * 1 - normal page fault | |
529 | * -1 - critical hash insertion error | |
530 | */ | |
531 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
532 | { | |
533 | void *pgdir; | |
534 | unsigned long vsid; | |
535 | struct mm_struct *mm; | |
536 | pte_t *ptep; | |
1da177e4 | 537 | cpumask_t tmp; |
3c726f8d | 538 | int rc, user_region = 0, local = 0; |
1da177e4 | 539 | |
3c726f8d BH |
540 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
541 | ea, access, trap); | |
1f8d419e | 542 | |
3c726f8d BH |
543 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
544 | DBG_LOW(" out of pgtable range !\n"); | |
545 | return 1; | |
546 | } | |
547 | ||
548 | /* Get region & vsid */ | |
1da177e4 LT |
549 | switch (REGION_ID(ea)) { |
550 | case USER_REGION_ID: | |
551 | user_region = 1; | |
552 | mm = current->mm; | |
3c726f8d BH |
553 | if (! mm) { |
554 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 555 | return 1; |
3c726f8d | 556 | } |
1da177e4 LT |
557 | vsid = get_vsid(mm->context.id, ea); |
558 | break; | |
1da177e4 | 559 | case VMALLOC_REGION_ID: |
1da177e4 LT |
560 | mm = &init_mm; |
561 | vsid = get_kernel_vsid(ea); | |
562 | break; | |
1da177e4 LT |
563 | default: |
564 | /* Not a valid range | |
565 | * Send the problem up to do_page_fault | |
566 | */ | |
567 | return 1; | |
1da177e4 | 568 | } |
3c726f8d | 569 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 570 | |
3c726f8d | 571 | /* Get pgdir */ |
1da177e4 | 572 | pgdir = mm->pgd; |
1da177e4 LT |
573 | if (pgdir == NULL) |
574 | return 1; | |
575 | ||
3c726f8d | 576 | /* Check CPU locality */ |
1da177e4 LT |
577 | tmp = cpumask_of_cpu(smp_processor_id()); |
578 | if (user_region && cpus_equal(mm->cpu_vm_mask, tmp)) | |
579 | local = 1; | |
580 | ||
3c726f8d BH |
581 | /* Handle hugepage regions */ |
582 | if (unlikely(in_hugepage_area(mm->context, ea))) { | |
583 | DBG_LOW(" -> huge page !\n"); | |
584 | return hash_huge_page(mm, access, ea, vsid, local); | |
585 | } | |
586 | ||
587 | /* Get PTE and page size from page tables */ | |
588 | ptep = find_linux_pte(pgdir, ea); | |
589 | if (ptep == NULL || !pte_present(*ptep)) { | |
590 | DBG_LOW(" no PTE !\n"); | |
591 | return 1; | |
592 | } | |
593 | ||
594 | #ifndef CONFIG_PPC_64K_PAGES | |
595 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
596 | #else | |
597 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
598 | pte_val(*(ptep + PTRS_PER_PTE))); | |
599 | #endif | |
600 | /* Pre-check access permissions (will be re-checked atomically | |
601 | * in __hash_page_XX but this pre-check is a fast path | |
602 | */ | |
603 | if (access & ~pte_val(*ptep)) { | |
604 | DBG_LOW(" no access !\n"); | |
605 | return 1; | |
1da177e4 LT |
606 | } |
607 | ||
3c726f8d BH |
608 | /* Do actual hashing */ |
609 | #ifndef CONFIG_PPC_64K_PAGES | |
610 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
611 | #else | |
612 | if (mmu_virtual_psize == MMU_PAGE_64K) | |
613 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local); | |
614 | else | |
615 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
616 | #endif /* CONFIG_PPC_64K_PAGES */ | |
617 | ||
618 | #ifndef CONFIG_PPC_64K_PAGES | |
619 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
620 | #else | |
621 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
622 | pte_val(*(ptep + PTRS_PER_PTE))); | |
623 | #endif | |
624 | DBG_LOW(" -> rc=%d\n", rc); | |
625 | return rc; | |
1da177e4 LT |
626 | } |
627 | ||
3c726f8d BH |
628 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
629 | unsigned long access, unsigned long trap) | |
1da177e4 | 630 | { |
3c726f8d BH |
631 | unsigned long vsid; |
632 | void *pgdir; | |
633 | pte_t *ptep; | |
634 | cpumask_t mask; | |
635 | unsigned long flags; | |
636 | int local = 0; | |
637 | ||
638 | /* We don't want huge pages prefaulted for now | |
639 | */ | |
640 | if (unlikely(in_hugepage_area(mm->context, ea))) | |
641 | return; | |
642 | ||
643 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
644 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 645 | |
3c726f8d BH |
646 | /* Get PTE, VSID, access mask */ |
647 | pgdir = mm->pgd; | |
648 | if (pgdir == NULL) | |
649 | return; | |
650 | ptep = find_linux_pte(pgdir, ea); | |
651 | if (!ptep) | |
652 | return; | |
653 | vsid = get_vsid(mm->context.id, ea); | |
654 | ||
655 | /* Hash it in */ | |
656 | local_irq_save(flags); | |
657 | mask = cpumask_of_cpu(smp_processor_id()); | |
658 | if (cpus_equal(mm->cpu_vm_mask, mask)) | |
659 | local = 1; | |
660 | #ifndef CONFIG_PPC_64K_PAGES | |
661 | __hash_page_4K(ea, access, vsid, ptep, trap, local); | |
662 | #else | |
663 | if (mmu_virtual_psize == MMU_PAGE_64K) | |
664 | __hash_page_64K(ea, access, vsid, ptep, trap, local); | |
1da177e4 | 665 | else |
3c726f8d BH |
666 | __hash_page_4K(ea, access, vsid, ptep, trap, local); |
667 | #endif /* CONFIG_PPC_64K_PAGES */ | |
668 | local_irq_restore(flags); | |
669 | } | |
670 | ||
671 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int local) | |
672 | { | |
673 | unsigned long hash, index, shift, hidx, slot; | |
674 | ||
675 | DBG_LOW("flush_hash_page(va=%016x)\n", va); | |
676 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { | |
677 | hash = hpt_hash(va, shift); | |
678 | hidx = __rpte_to_hidx(pte, index); | |
679 | if (hidx & _PTEIDX_SECONDARY) | |
680 | hash = ~hash; | |
681 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
682 | slot += hidx & _PTEIDX_GROUP_IX; | |
683 | DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx); | |
684 | ppc_md.hpte_invalidate(slot, va, psize, local); | |
685 | } pte_iterate_hashed_end(); | |
1da177e4 LT |
686 | } |
687 | ||
61b1a942 | 688 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 689 | { |
3c726f8d | 690 | if (ppc_md.flush_hash_range) |
61b1a942 | 691 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 692 | else { |
1da177e4 | 693 | int i; |
61b1a942 BH |
694 | struct ppc64_tlb_batch *batch = |
695 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
696 | |
697 | for (i = 0; i < number; i++) | |
3c726f8d BH |
698 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
699 | batch->psize, local); | |
1da177e4 LT |
700 | } |
701 | } | |
702 | ||
703 | static inline void make_bl(unsigned int *insn_addr, void *func) | |
704 | { | |
705 | unsigned long funcp = *((unsigned long *)func); | |
706 | int offset = funcp - (unsigned long)insn_addr; | |
707 | ||
708 | *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc)); | |
709 | flush_icache_range((unsigned long)insn_addr, 4+ | |
710 | (unsigned long)insn_addr); | |
711 | } | |
712 | ||
713 | /* | |
714 | * low_hash_fault is called when we the low level hash code failed | |
715 | * to instert a PTE due to an hypervisor error | |
716 | */ | |
717 | void low_hash_fault(struct pt_regs *regs, unsigned long address) | |
718 | { | |
719 | if (user_mode(regs)) { | |
720 | siginfo_t info; | |
721 | ||
722 | info.si_signo = SIGBUS; | |
723 | info.si_errno = 0; | |
724 | info.si_code = BUS_ADRERR; | |
725 | info.si_addr = (void __user *)address; | |
726 | force_sig_info(SIGBUS, &info, current); | |
727 | return; | |
728 | } | |
729 | bad_page_fault(regs, address, SIGBUS); | |
730 | } | |
731 | ||
732 | void __init htab_finish_init(void) | |
733 | { | |
734 | extern unsigned int *htab_call_hpte_insert1; | |
735 | extern unsigned int *htab_call_hpte_insert2; | |
736 | extern unsigned int *htab_call_hpte_remove; | |
737 | extern unsigned int *htab_call_hpte_updatepp; | |
738 | ||
3c726f8d BH |
739 | #ifdef CONFIG_PPC_64K_PAGES |
740 | extern unsigned int *ht64_call_hpte_insert1; | |
741 | extern unsigned int *ht64_call_hpte_insert2; | |
742 | extern unsigned int *ht64_call_hpte_remove; | |
743 | extern unsigned int *ht64_call_hpte_updatepp; | |
744 | ||
745 | make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert); | |
746 | make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert); | |
747 | make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove); | |
748 | make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
749 | #endif /* CONFIG_PPC_64K_PAGES */ | |
750 | ||
1da177e4 LT |
751 | make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert); |
752 | make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert); | |
753 | make_bl(htab_call_hpte_remove, ppc_md.hpte_remove); | |
754 | make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp); | |
755 | } |