Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * PowerPC64 port by Mike Corrigan and Dave Engebretsen | |
3 | * {mikejc|engebret}@us.ibm.com | |
4 | * | |
5 | * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com> | |
6 | * | |
7 | * SMP scalability work: | |
8 | * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * | |
10 | * Module name: htab.c | |
11 | * | |
12 | * Description: | |
13 | * PowerPC Hashed Page Table functions | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
3c726f8d | 22 | #undef DEBUG_LOW |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/errno.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/proc_fs.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/sysctl.h> | |
66b15db6 | 30 | #include <linux/export.h> |
1da177e4 LT |
31 | #include <linux/ctype.h> |
32 | #include <linux/cache.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/signal.h> | |
95f72d1e | 35 | #include <linux/memblock.h> |
1da177e4 | 36 | |
1da177e4 LT |
37 | #include <asm/processor.h> |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/mmu.h> | |
40 | #include <asm/mmu_context.h> | |
41 | #include <asm/page.h> | |
42 | #include <asm/types.h> | |
43 | #include <asm/system.h> | |
44 | #include <asm/uaccess.h> | |
45 | #include <asm/machdep.h> | |
d9b2b2a2 | 46 | #include <asm/prom.h> |
1da177e4 LT |
47 | #include <asm/abs_addr.h> |
48 | #include <asm/tlbflush.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/eeh.h> | |
51 | #include <asm/tlb.h> | |
52 | #include <asm/cacheflush.h> | |
53 | #include <asm/cputable.h> | |
1da177e4 | 54 | #include <asm/sections.h> |
d0f13e3c | 55 | #include <asm/spu.h> |
aa39be09 | 56 | #include <asm/udbg.h> |
b68a70c4 | 57 | #include <asm/code-patching.h> |
3ccc00a7 | 58 | #include <asm/fadump.h> |
f5339277 | 59 | #include <asm/firmware.h> |
1da177e4 LT |
60 | |
61 | #ifdef DEBUG | |
62 | #define DBG(fmt...) udbg_printf(fmt) | |
63 | #else | |
64 | #define DBG(fmt...) | |
65 | #endif | |
66 | ||
3c726f8d BH |
67 | #ifdef DEBUG_LOW |
68 | #define DBG_LOW(fmt...) udbg_printf(fmt) | |
69 | #else | |
70 | #define DBG_LOW(fmt...) | |
71 | #endif | |
72 | ||
73 | #define KB (1024) | |
74 | #define MB (1024*KB) | |
658013e9 | 75 | #define GB (1024L*MB) |
3c726f8d | 76 | |
1da177e4 LT |
77 | /* |
78 | * Note: pte --> Linux PTE | |
79 | * HPTE --> PowerPC Hashed Page Table Entry | |
80 | * | |
81 | * Execution context: | |
82 | * htab_initialize is called with the MMU off (of course), but | |
83 | * the kernel has been copied down to zero so it can directly | |
84 | * reference global data. At this point it is very difficult | |
85 | * to print debug info. | |
86 | * | |
87 | */ | |
88 | ||
89 | #ifdef CONFIG_U3_DART | |
90 | extern unsigned long dart_tablebase; | |
91 | #endif /* CONFIG_U3_DART */ | |
92 | ||
799d6046 PM |
93 | static unsigned long _SDR1; |
94 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
95 | ||
8e561e7e | 96 | struct hash_pte *htab_address; |
337a7128 | 97 | unsigned long htab_size_bytes; |
96e28449 | 98 | unsigned long htab_hash_mask; |
4ab79aa8 | 99 | EXPORT_SYMBOL_GPL(htab_hash_mask); |
3c726f8d BH |
100 | int mmu_linear_psize = MMU_PAGE_4K; |
101 | int mmu_virtual_psize = MMU_PAGE_4K; | |
bf72aeba | 102 | int mmu_vmalloc_psize = MMU_PAGE_4K; |
cec08e7a BH |
103 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
104 | int mmu_vmemmap_psize = MMU_PAGE_4K; | |
105 | #endif | |
bf72aeba | 106 | int mmu_io_psize = MMU_PAGE_4K; |
1189be65 PM |
107 | int mmu_kernel_ssize = MMU_SEGSIZE_256M; |
108 | int mmu_highuser_ssize = MMU_SEGSIZE_256M; | |
584f8b71 | 109 | u16 mmu_slb_size = 64; |
4ab79aa8 | 110 | EXPORT_SYMBOL_GPL(mmu_slb_size); |
bf72aeba PM |
111 | #ifdef CONFIG_PPC_64K_PAGES |
112 | int mmu_ci_restrictions; | |
113 | #endif | |
370a908d BH |
114 | #ifdef CONFIG_DEBUG_PAGEALLOC |
115 | static u8 *linear_map_hash_slots; | |
116 | static unsigned long linear_map_hash_count; | |
ed166692 | 117 | static DEFINE_SPINLOCK(linear_map_hash_lock); |
370a908d | 118 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1da177e4 | 119 | |
3c726f8d BH |
120 | /* There are definitions of page sizes arrays to be used when none |
121 | * is provided by the firmware. | |
122 | */ | |
1da177e4 | 123 | |
3c726f8d BH |
124 | /* Pre-POWER4 CPUs (4k pages only) |
125 | */ | |
09de9ff8 | 126 | static struct mmu_psize_def mmu_psize_defaults_old[] = { |
3c726f8d BH |
127 | [MMU_PAGE_4K] = { |
128 | .shift = 12, | |
129 | .sllp = 0, | |
130 | .penc = 0, | |
131 | .avpnm = 0, | |
132 | .tlbiel = 0, | |
133 | }, | |
134 | }; | |
135 | ||
136 | /* POWER4, GPUL, POWER5 | |
137 | * | |
138 | * Support for 16Mb large pages | |
139 | */ | |
09de9ff8 | 140 | static struct mmu_psize_def mmu_psize_defaults_gp[] = { |
3c726f8d BH |
141 | [MMU_PAGE_4K] = { |
142 | .shift = 12, | |
143 | .sllp = 0, | |
144 | .penc = 0, | |
145 | .avpnm = 0, | |
146 | .tlbiel = 1, | |
147 | }, | |
148 | [MMU_PAGE_16M] = { | |
149 | .shift = 24, | |
150 | .sllp = SLB_VSID_L, | |
151 | .penc = 0, | |
152 | .avpnm = 0x1UL, | |
153 | .tlbiel = 0, | |
154 | }, | |
155 | }; | |
156 | ||
bc033b63 BH |
157 | static unsigned long htab_convert_pte_flags(unsigned long pteflags) |
158 | { | |
159 | unsigned long rflags = pteflags & 0x1fa; | |
160 | ||
161 | /* _PAGE_EXEC -> NOEXEC */ | |
162 | if ((pteflags & _PAGE_EXEC) == 0) | |
163 | rflags |= HPTE_R_N; | |
164 | ||
165 | /* PP bits. PAGE_USER is already PP bit 0x2, so we only | |
166 | * need to add in 0x1 if it's a read-only user page | |
167 | */ | |
168 | if ((pteflags & _PAGE_USER) && !((pteflags & _PAGE_RW) && | |
169 | (pteflags & _PAGE_DIRTY))) | |
170 | rflags |= 1; | |
171 | ||
172 | /* Always add C */ | |
173 | return rflags | HPTE_R_C; | |
174 | } | |
3c726f8d BH |
175 | |
176 | int htab_bolt_mapping(unsigned long vstart, unsigned long vend, | |
bc033b63 | 177 | unsigned long pstart, unsigned long prot, |
1189be65 | 178 | int psize, int ssize) |
1da177e4 | 179 | { |
3c726f8d BH |
180 | unsigned long vaddr, paddr; |
181 | unsigned int step, shift; | |
3c726f8d | 182 | int ret = 0; |
1da177e4 | 183 | |
3c726f8d BH |
184 | shift = mmu_psize_defs[psize].shift; |
185 | step = 1 << shift; | |
1da177e4 | 186 | |
bc033b63 BH |
187 | prot = htab_convert_pte_flags(prot); |
188 | ||
189 | DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n", | |
190 | vstart, vend, pstart, prot, psize, ssize); | |
191 | ||
3c726f8d BH |
192 | for (vaddr = vstart, paddr = pstart; vaddr < vend; |
193 | vaddr += step, paddr += step) { | |
370a908d | 194 | unsigned long hash, hpteg; |
1189be65 PM |
195 | unsigned long vsid = get_kernel_vsid(vaddr, ssize); |
196 | unsigned long va = hpt_va(vaddr, vsid, ssize); | |
9e88ba4e PM |
197 | unsigned long tprot = prot; |
198 | ||
199 | /* Make kernel text executable */ | |
549e8152 | 200 | if (overlaps_kernel_text(vaddr, vaddr + step)) |
9e88ba4e | 201 | tprot &= ~HPTE_R_N; |
1da177e4 | 202 | |
1189be65 | 203 | hash = hpt_hash(va, shift, ssize); |
1da177e4 LT |
204 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
205 | ||
c30a4df3 | 206 | BUG_ON(!ppc_md.hpte_insert); |
9e88ba4e | 207 | ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot, |
bc033b63 | 208 | HPTE_V_BOLTED, psize, ssize); |
c30a4df3 | 209 | |
3c726f8d BH |
210 | if (ret < 0) |
211 | break; | |
370a908d BH |
212 | #ifdef CONFIG_DEBUG_PAGEALLOC |
213 | if ((paddr >> PAGE_SHIFT) < linear_map_hash_count) | |
214 | linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80; | |
215 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
3c726f8d BH |
216 | } |
217 | return ret < 0 ? ret : 0; | |
218 | } | |
1da177e4 | 219 | |
ae86f008 | 220 | #ifdef CONFIG_MEMORY_HOTPLUG |
52db9b44 | 221 | static int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
f8c8803b BP |
222 | int psize, int ssize) |
223 | { | |
224 | unsigned long vaddr; | |
225 | unsigned int step, shift; | |
226 | ||
227 | shift = mmu_psize_defs[psize].shift; | |
228 | step = 1 << shift; | |
229 | ||
230 | if (!ppc_md.hpte_removebolted) { | |
52db9b44 BP |
231 | printk(KERN_WARNING "Platform doesn't implement " |
232 | "hpte_removebolted\n"); | |
233 | return -EINVAL; | |
f8c8803b BP |
234 | } |
235 | ||
236 | for (vaddr = vstart; vaddr < vend; vaddr += step) | |
237 | ppc_md.hpte_removebolted(vaddr, psize, ssize); | |
52db9b44 BP |
238 | |
239 | return 0; | |
f8c8803b | 240 | } |
ae86f008 | 241 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
f8c8803b | 242 | |
1189be65 PM |
243 | static int __init htab_dt_scan_seg_sizes(unsigned long node, |
244 | const char *uname, int depth, | |
245 | void *data) | |
246 | { | |
247 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
248 | u32 *prop; | |
249 | unsigned long size = 0; | |
250 | ||
251 | /* We are scanning "cpu" nodes only */ | |
252 | if (type == NULL || strcmp(type, "cpu") != 0) | |
253 | return 0; | |
254 | ||
255 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", | |
256 | &size); | |
257 | if (prop == NULL) | |
258 | return 0; | |
259 | for (; size >= 4; size -= 4, ++prop) { | |
260 | if (prop[0] == 40) { | |
261 | DBG("1T segment support detected\n"); | |
44ae3ab3 | 262 | cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT; |
f5534004 | 263 | return 1; |
1189be65 | 264 | } |
1189be65 | 265 | } |
44ae3ab3 | 266 | cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B; |
1189be65 PM |
267 | return 0; |
268 | } | |
269 | ||
270 | static void __init htab_init_seg_sizes(void) | |
271 | { | |
272 | of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL); | |
273 | } | |
274 | ||
3c726f8d BH |
275 | static int __init htab_dt_scan_page_sizes(unsigned long node, |
276 | const char *uname, int depth, | |
277 | void *data) | |
278 | { | |
279 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
280 | u32 *prop; | |
281 | unsigned long size = 0; | |
282 | ||
283 | /* We are scanning "cpu" nodes only */ | |
284 | if (type == NULL || strcmp(type, "cpu") != 0) | |
285 | return 0; | |
286 | ||
287 | prop = (u32 *)of_get_flat_dt_prop(node, | |
288 | "ibm,segment-page-sizes", &size); | |
289 | if (prop != NULL) { | |
290 | DBG("Page sizes from device-tree:\n"); | |
291 | size /= 4; | |
44ae3ab3 | 292 | cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE); |
3c726f8d BH |
293 | while(size > 0) { |
294 | unsigned int shift = prop[0]; | |
295 | unsigned int slbenc = prop[1]; | |
296 | unsigned int lpnum = prop[2]; | |
297 | unsigned int lpenc = 0; | |
298 | struct mmu_psize_def *def; | |
299 | int idx = -1; | |
300 | ||
301 | size -= 3; prop += 3; | |
302 | while(size > 0 && lpnum) { | |
303 | if (prop[0] == shift) | |
304 | lpenc = prop[1]; | |
305 | prop += 2; size -= 2; | |
306 | lpnum--; | |
307 | } | |
308 | switch(shift) { | |
309 | case 0xc: | |
310 | idx = MMU_PAGE_4K; | |
311 | break; | |
312 | case 0x10: | |
313 | idx = MMU_PAGE_64K; | |
314 | break; | |
315 | case 0x14: | |
316 | idx = MMU_PAGE_1M; | |
317 | break; | |
318 | case 0x18: | |
319 | idx = MMU_PAGE_16M; | |
44ae3ab3 | 320 | cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE; |
3c726f8d BH |
321 | break; |
322 | case 0x22: | |
323 | idx = MMU_PAGE_16G; | |
324 | break; | |
325 | } | |
326 | if (idx < 0) | |
327 | continue; | |
328 | def = &mmu_psize_defs[idx]; | |
329 | def->shift = shift; | |
330 | if (shift <= 23) | |
331 | def->avpnm = 0; | |
332 | else | |
333 | def->avpnm = (1 << (shift - 23)) - 1; | |
334 | def->sllp = slbenc; | |
335 | def->penc = lpenc; | |
336 | /* We don't know for sure what's up with tlbiel, so | |
337 | * for now we only set it for 4K and 64K pages | |
338 | */ | |
339 | if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K) | |
340 | def->tlbiel = 1; | |
341 | else | |
342 | def->tlbiel = 0; | |
343 | ||
5c339919 | 344 | DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, " |
3c726f8d BH |
345 | "tlbiel=%d, penc=%d\n", |
346 | idx, shift, def->sllp, def->avpnm, def->tlbiel, | |
347 | def->penc); | |
1da177e4 | 348 | } |
3c726f8d BH |
349 | return 1; |
350 | } | |
351 | return 0; | |
352 | } | |
353 | ||
e16a9c09 | 354 | #ifdef CONFIG_HUGETLB_PAGE |
658013e9 JT |
355 | /* Scan for 16G memory blocks that have been set aside for huge pages |
356 | * and reserve those blocks for 16G huge pages. | |
357 | */ | |
358 | static int __init htab_dt_scan_hugepage_blocks(unsigned long node, | |
359 | const char *uname, int depth, | |
360 | void *data) { | |
361 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
362 | unsigned long *addr_prop; | |
363 | u32 *page_count_prop; | |
364 | unsigned int expected_pages; | |
365 | long unsigned int phys_addr; | |
366 | long unsigned int block_size; | |
367 | ||
368 | /* We are scanning "memory" nodes only */ | |
369 | if (type == NULL || strcmp(type, "memory") != 0) | |
370 | return 0; | |
371 | ||
372 | /* This property is the log base 2 of the number of virtual pages that | |
373 | * will represent this memory block. */ | |
374 | page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL); | |
375 | if (page_count_prop == NULL) | |
376 | return 0; | |
377 | expected_pages = (1 << page_count_prop[0]); | |
378 | addr_prop = of_get_flat_dt_prop(node, "reg", NULL); | |
379 | if (addr_prop == NULL) | |
380 | return 0; | |
381 | phys_addr = addr_prop[0]; | |
382 | block_size = addr_prop[1]; | |
383 | if (block_size != (16 * GB)) | |
384 | return 0; | |
385 | printk(KERN_INFO "Huge page(16GB) memory: " | |
386 | "addr = 0x%lX size = 0x%lX pages = %d\n", | |
387 | phys_addr, block_size, expected_pages); | |
95f72d1e YL |
388 | if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) { |
389 | memblock_reserve(phys_addr, block_size * expected_pages); | |
4792adba JT |
390 | add_gpage(phys_addr, block_size, expected_pages); |
391 | } | |
658013e9 JT |
392 | return 0; |
393 | } | |
e16a9c09 | 394 | #endif /* CONFIG_HUGETLB_PAGE */ |
658013e9 | 395 | |
3c726f8d BH |
396 | static void __init htab_init_page_sizes(void) |
397 | { | |
398 | int rc; | |
399 | ||
400 | /* Default to 4K pages only */ | |
401 | memcpy(mmu_psize_defs, mmu_psize_defaults_old, | |
402 | sizeof(mmu_psize_defaults_old)); | |
403 | ||
404 | /* | |
405 | * Try to find the available page sizes in the device-tree | |
406 | */ | |
407 | rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL); | |
408 | if (rc != 0) /* Found */ | |
409 | goto found; | |
410 | ||
411 | /* | |
412 | * Not in the device-tree, let's fallback on known size | |
413 | * list for 16M capable GP & GR | |
414 | */ | |
44ae3ab3 | 415 | if (mmu_has_feature(MMU_FTR_16M_PAGE)) |
3c726f8d BH |
416 | memcpy(mmu_psize_defs, mmu_psize_defaults_gp, |
417 | sizeof(mmu_psize_defaults_gp)); | |
418 | found: | |
370a908d | 419 | #ifndef CONFIG_DEBUG_PAGEALLOC |
3c726f8d BH |
420 | /* |
421 | * Pick a size for the linear mapping. Currently, we only support | |
422 | * 16M, 1M and 4K which is the default | |
423 | */ | |
424 | if (mmu_psize_defs[MMU_PAGE_16M].shift) | |
425 | mmu_linear_psize = MMU_PAGE_16M; | |
426 | else if (mmu_psize_defs[MMU_PAGE_1M].shift) | |
427 | mmu_linear_psize = MMU_PAGE_1M; | |
370a908d | 428 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
3c726f8d | 429 | |
bf72aeba | 430 | #ifdef CONFIG_PPC_64K_PAGES |
3c726f8d BH |
431 | /* |
432 | * Pick a size for the ordinary pages. Default is 4K, we support | |
bf72aeba PM |
433 | * 64K for user mappings and vmalloc if supported by the processor. |
434 | * We only use 64k for ioremap if the processor | |
435 | * (and firmware) support cache-inhibited large pages. | |
436 | * If not, we use 4k and set mmu_ci_restrictions so that | |
437 | * hash_page knows to switch processes that use cache-inhibited | |
438 | * mappings to 4k pages. | |
3c726f8d | 439 | */ |
bf72aeba | 440 | if (mmu_psize_defs[MMU_PAGE_64K].shift) { |
3c726f8d | 441 | mmu_virtual_psize = MMU_PAGE_64K; |
bf72aeba | 442 | mmu_vmalloc_psize = MMU_PAGE_64K; |
370a908d BH |
443 | if (mmu_linear_psize == MMU_PAGE_4K) |
444 | mmu_linear_psize = MMU_PAGE_64K; | |
44ae3ab3 | 445 | if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) { |
cfe666b1 PM |
446 | /* |
447 | * Don't use 64k pages for ioremap on pSeries, since | |
448 | * that would stop us accessing the HEA ethernet. | |
449 | */ | |
450 | if (!machine_is(pseries)) | |
451 | mmu_io_psize = MMU_PAGE_64K; | |
452 | } else | |
bf72aeba PM |
453 | mmu_ci_restrictions = 1; |
454 | } | |
370a908d | 455 | #endif /* CONFIG_PPC_64K_PAGES */ |
3c726f8d | 456 | |
cec08e7a BH |
457 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
458 | /* We try to use 16M pages for vmemmap if that is supported | |
459 | * and we have at least 1G of RAM at boot | |
460 | */ | |
461 | if (mmu_psize_defs[MMU_PAGE_16M].shift && | |
95f72d1e | 462 | memblock_phys_mem_size() >= 0x40000000) |
cec08e7a BH |
463 | mmu_vmemmap_psize = MMU_PAGE_16M; |
464 | else if (mmu_psize_defs[MMU_PAGE_64K].shift) | |
465 | mmu_vmemmap_psize = MMU_PAGE_64K; | |
466 | else | |
467 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
468 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
469 | ||
bf72aeba | 470 | printk(KERN_DEBUG "Page orders: linear mapping = %d, " |
cec08e7a BH |
471 | "virtual = %d, io = %d" |
472 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
473 | ", vmemmap = %d" | |
474 | #endif | |
475 | "\n", | |
3c726f8d | 476 | mmu_psize_defs[mmu_linear_psize].shift, |
bf72aeba | 477 | mmu_psize_defs[mmu_virtual_psize].shift, |
cec08e7a BH |
478 | mmu_psize_defs[mmu_io_psize].shift |
479 | #ifdef CONFIG_SPARSEMEM_VMEMMAP | |
480 | ,mmu_psize_defs[mmu_vmemmap_psize].shift | |
481 | #endif | |
482 | ); | |
3c726f8d BH |
483 | |
484 | #ifdef CONFIG_HUGETLB_PAGE | |
658013e9 JT |
485 | /* Reserve 16G huge page memory sections for huge pages */ |
486 | of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL); | |
3c726f8d BH |
487 | #endif /* CONFIG_HUGETLB_PAGE */ |
488 | } | |
489 | ||
490 | static int __init htab_dt_scan_pftsize(unsigned long node, | |
491 | const char *uname, int depth, | |
492 | void *data) | |
493 | { | |
494 | char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
495 | u32 *prop; | |
496 | ||
497 | /* We are scanning "cpu" nodes only */ | |
498 | if (type == NULL || strcmp(type, "cpu") != 0) | |
499 | return 0; | |
500 | ||
501 | prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL); | |
502 | if (prop != NULL) { | |
503 | /* pft_size[0] is the NUMA CEC cookie */ | |
504 | ppc64_pft_size = prop[1]; | |
505 | return 1; | |
1da177e4 | 506 | } |
3c726f8d | 507 | return 0; |
1da177e4 LT |
508 | } |
509 | ||
3c726f8d | 510 | static unsigned long __init htab_get_table_size(void) |
3eac8c69 | 511 | { |
13870b65 | 512 | unsigned long mem_size, rnd_mem_size, pteg_count, psize; |
3eac8c69 | 513 | |
3c726f8d | 514 | /* If hash size isn't already provided by the platform, we try to |
943ffb58 | 515 | * retrieve it from the device-tree. If it's not there neither, we |
3c726f8d | 516 | * calculate it now based on the total RAM size |
3eac8c69 | 517 | */ |
3c726f8d BH |
518 | if (ppc64_pft_size == 0) |
519 | of_scan_flat_dt(htab_dt_scan_pftsize, NULL); | |
3eac8c69 PM |
520 | if (ppc64_pft_size) |
521 | return 1UL << ppc64_pft_size; | |
522 | ||
523 | /* round mem_size up to next power of 2 */ | |
95f72d1e | 524 | mem_size = memblock_phys_mem_size(); |
799d6046 PM |
525 | rnd_mem_size = 1UL << __ilog2(mem_size); |
526 | if (rnd_mem_size < mem_size) | |
3eac8c69 PM |
527 | rnd_mem_size <<= 1; |
528 | ||
529 | /* # pages / 2 */ | |
13870b65 AB |
530 | psize = mmu_psize_defs[mmu_virtual_psize].shift; |
531 | pteg_count = max(rnd_mem_size >> (psize + 1), 1UL << 11); | |
3eac8c69 PM |
532 | |
533 | return pteg_count << 7; | |
534 | } | |
535 | ||
54b79248 | 536 | #ifdef CONFIG_MEMORY_HOTPLUG |
a1194097 | 537 | int create_section_mapping(unsigned long start, unsigned long end) |
54b79248 | 538 | { |
a1194097 | 539 | return htab_bolt_mapping(start, end, __pa(start), |
f5ea64dc | 540 | pgprot_val(PAGE_KERNEL), mmu_linear_psize, |
a1194097 | 541 | mmu_kernel_ssize); |
54b79248 | 542 | } |
f8c8803b | 543 | |
52db9b44 | 544 | int remove_section_mapping(unsigned long start, unsigned long end) |
f8c8803b | 545 | { |
52db9b44 BP |
546 | return htab_remove_mapping(start, end, mmu_linear_psize, |
547 | mmu_kernel_ssize); | |
f8c8803b | 548 | } |
54b79248 MK |
549 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
550 | ||
b68a70c4 | 551 | #define FUNCTION_TEXT(A) ((*(unsigned long *)(A))) |
7d0daae4 ME |
552 | |
553 | static void __init htab_finish_init(void) | |
554 | { | |
555 | extern unsigned int *htab_call_hpte_insert1; | |
556 | extern unsigned int *htab_call_hpte_insert2; | |
557 | extern unsigned int *htab_call_hpte_remove; | |
558 | extern unsigned int *htab_call_hpte_updatepp; | |
559 | ||
16c2d476 | 560 | #ifdef CONFIG_PPC_HAS_HASH_64K |
7d0daae4 ME |
561 | extern unsigned int *ht64_call_hpte_insert1; |
562 | extern unsigned int *ht64_call_hpte_insert2; | |
563 | extern unsigned int *ht64_call_hpte_remove; | |
564 | extern unsigned int *ht64_call_hpte_updatepp; | |
565 | ||
b68a70c4 AB |
566 | patch_branch(ht64_call_hpte_insert1, |
567 | FUNCTION_TEXT(ppc_md.hpte_insert), | |
568 | BRANCH_SET_LINK); | |
569 | patch_branch(ht64_call_hpte_insert2, | |
570 | FUNCTION_TEXT(ppc_md.hpte_insert), | |
571 | BRANCH_SET_LINK); | |
572 | patch_branch(ht64_call_hpte_remove, | |
573 | FUNCTION_TEXT(ppc_md.hpte_remove), | |
574 | BRANCH_SET_LINK); | |
575 | patch_branch(ht64_call_hpte_updatepp, | |
576 | FUNCTION_TEXT(ppc_md.hpte_updatepp), | |
577 | BRANCH_SET_LINK); | |
578 | ||
5b825831 | 579 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
7d0daae4 | 580 | |
b68a70c4 AB |
581 | patch_branch(htab_call_hpte_insert1, |
582 | FUNCTION_TEXT(ppc_md.hpte_insert), | |
583 | BRANCH_SET_LINK); | |
584 | patch_branch(htab_call_hpte_insert2, | |
585 | FUNCTION_TEXT(ppc_md.hpte_insert), | |
586 | BRANCH_SET_LINK); | |
587 | patch_branch(htab_call_hpte_remove, | |
588 | FUNCTION_TEXT(ppc_md.hpte_remove), | |
589 | BRANCH_SET_LINK); | |
590 | patch_branch(htab_call_hpte_updatepp, | |
591 | FUNCTION_TEXT(ppc_md.hpte_updatepp), | |
592 | BRANCH_SET_LINK); | |
7d0daae4 ME |
593 | } |
594 | ||
757c74d2 | 595 | static void __init htab_initialize(void) |
1da177e4 | 596 | { |
337a7128 | 597 | unsigned long table; |
1da177e4 | 598 | unsigned long pteg_count; |
9e88ba4e | 599 | unsigned long prot; |
41d824bf | 600 | unsigned long base = 0, size = 0, limit; |
28be7072 | 601 | struct memblock_region *reg; |
3c726f8d | 602 | |
1da177e4 LT |
603 | DBG(" -> htab_initialize()\n"); |
604 | ||
1189be65 PM |
605 | /* Initialize segment sizes */ |
606 | htab_init_seg_sizes(); | |
607 | ||
3c726f8d BH |
608 | /* Initialize page sizes */ |
609 | htab_init_page_sizes(); | |
610 | ||
44ae3ab3 | 611 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) { |
1189be65 PM |
612 | mmu_kernel_ssize = MMU_SEGSIZE_1T; |
613 | mmu_highuser_ssize = MMU_SEGSIZE_1T; | |
614 | printk(KERN_INFO "Using 1TB segments\n"); | |
615 | } | |
616 | ||
1da177e4 LT |
617 | /* |
618 | * Calculate the required size of the htab. We want the number of | |
619 | * PTEGs to equal one half the number of real pages. | |
620 | */ | |
3c726f8d | 621 | htab_size_bytes = htab_get_table_size(); |
1da177e4 LT |
622 | pteg_count = htab_size_bytes >> 7; |
623 | ||
1da177e4 LT |
624 | htab_hash_mask = pteg_count - 1; |
625 | ||
57cfb814 | 626 | if (firmware_has_feature(FW_FEATURE_LPAR)) { |
1da177e4 LT |
627 | /* Using a hypervisor which owns the htab */ |
628 | htab_address = NULL; | |
629 | _SDR1 = 0; | |
3ccc00a7 MS |
630 | #ifdef CONFIG_FA_DUMP |
631 | /* | |
632 | * If firmware assisted dump is active firmware preserves | |
633 | * the contents of htab along with entire partition memory. | |
634 | * Clear the htab if firmware assisted dump is active so | |
635 | * that we dont end up using old mappings. | |
636 | */ | |
637 | if (is_fadump_active() && ppc_md.hpte_clear_all) | |
638 | ppc_md.hpte_clear_all(); | |
639 | #endif | |
1da177e4 LT |
640 | } else { |
641 | /* Find storage for the HPT. Must be contiguous in | |
41d824bf | 642 | * the absolute address space. On cell we want it to be |
31bf1119 | 643 | * in the first 2 Gig so we can use it for IOMMU hacks. |
1da177e4 | 644 | */ |
41d824bf | 645 | if (machine_is(cell)) |
31bf1119 | 646 | limit = 0x80000000; |
41d824bf | 647 | else |
27f574c2 | 648 | limit = MEMBLOCK_ALLOC_ANYWHERE; |
41d824bf | 649 | |
95f72d1e | 650 | table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit); |
1da177e4 LT |
651 | |
652 | DBG("Hash table allocated at %lx, size: %lx\n", table, | |
653 | htab_size_bytes); | |
654 | ||
1da177e4 LT |
655 | htab_address = abs_to_virt(table); |
656 | ||
657 | /* htab absolute addr + encoded htabsize */ | |
658 | _SDR1 = table + __ilog2(pteg_count) - 11; | |
659 | ||
660 | /* Initialize the HPT with no entries */ | |
661 | memset((void *)table, 0, htab_size_bytes); | |
799d6046 PM |
662 | |
663 | /* Set SDR1 */ | |
664 | mtspr(SPRN_SDR1, _SDR1); | |
1da177e4 LT |
665 | } |
666 | ||
f5ea64dc | 667 | prot = pgprot_val(PAGE_KERNEL); |
1da177e4 | 668 | |
370a908d | 669 | #ifdef CONFIG_DEBUG_PAGEALLOC |
95f72d1e YL |
670 | linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT; |
671 | linear_map_hash_slots = __va(memblock_alloc_base(linear_map_hash_count, | |
cd3db0c4 | 672 | 1, ppc64_rma_size)); |
370a908d BH |
673 | memset(linear_map_hash_slots, 0, linear_map_hash_count); |
674 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
675 | ||
1da177e4 LT |
676 | /* On U3 based machines, we need to reserve the DART area and |
677 | * _NOT_ map it to avoid cache paradoxes as it's remapped non | |
678 | * cacheable later on | |
679 | */ | |
1da177e4 LT |
680 | |
681 | /* create bolted the linear mapping in the hash table */ | |
28be7072 BH |
682 | for_each_memblock(memory, reg) { |
683 | base = (unsigned long)__va(reg->base); | |
684 | size = reg->size; | |
1da177e4 | 685 | |
5c339919 | 686 | DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", |
9e88ba4e | 687 | base, size, prot); |
1da177e4 LT |
688 | |
689 | #ifdef CONFIG_U3_DART | |
690 | /* Do not map the DART space. Fortunately, it will be aligned | |
95f72d1e | 691 | * in such a way that it will not cross two memblock regions and |
3c726f8d BH |
692 | * will fit within a single 16Mb page. |
693 | * The DART space is assumed to be a full 16Mb region even if | |
694 | * we only use 2Mb of that space. We will use more of it later | |
695 | * for AGP GART. We have to use a full 16Mb large page. | |
1da177e4 LT |
696 | */ |
697 | DBG("DART base: %lx\n", dart_tablebase); | |
698 | ||
699 | if (dart_tablebase != 0 && dart_tablebase >= base | |
700 | && dart_tablebase < (base + size)) { | |
caf80e57 | 701 | unsigned long dart_table_end = dart_tablebase + 16 * MB; |
1da177e4 | 702 | if (base != dart_tablebase) |
3c726f8d | 703 | BUG_ON(htab_bolt_mapping(base, dart_tablebase, |
9e88ba4e | 704 | __pa(base), prot, |
1189be65 PM |
705 | mmu_linear_psize, |
706 | mmu_kernel_ssize)); | |
caf80e57 | 707 | if ((base + size) > dart_table_end) |
3c726f8d | 708 | BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB, |
caf80e57 ME |
709 | base + size, |
710 | __pa(dart_table_end), | |
9e88ba4e | 711 | prot, |
1189be65 PM |
712 | mmu_linear_psize, |
713 | mmu_kernel_ssize)); | |
1da177e4 LT |
714 | continue; |
715 | } | |
716 | #endif /* CONFIG_U3_DART */ | |
caf80e57 | 717 | BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), |
9e88ba4e | 718 | prot, mmu_linear_psize, mmu_kernel_ssize)); |
e63075a3 BH |
719 | } |
720 | memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE); | |
1da177e4 LT |
721 | |
722 | /* | |
723 | * If we have a memory_limit and we've allocated TCEs then we need to | |
724 | * explicitly map the TCE area at the top of RAM. We also cope with the | |
725 | * case that the TCEs start below memory_limit. | |
726 | * tce_alloc_start/end are 16MB aligned so the mapping should work | |
727 | * for either 4K or 16MB pages. | |
728 | */ | |
729 | if (tce_alloc_start) { | |
b5666f70 ME |
730 | tce_alloc_start = (unsigned long)__va(tce_alloc_start); |
731 | tce_alloc_end = (unsigned long)__va(tce_alloc_end); | |
1da177e4 LT |
732 | |
733 | if (base + size >= tce_alloc_start) | |
734 | tce_alloc_start = base + size + 1; | |
735 | ||
caf80e57 | 736 | BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end, |
bc033b63 | 737 | __pa(tce_alloc_start), prot, |
1189be65 | 738 | mmu_linear_psize, mmu_kernel_ssize)); |
1da177e4 LT |
739 | } |
740 | ||
7d0daae4 ME |
741 | htab_finish_init(); |
742 | ||
1da177e4 LT |
743 | DBG(" <- htab_initialize()\n"); |
744 | } | |
745 | #undef KB | |
746 | #undef MB | |
1da177e4 | 747 | |
757c74d2 | 748 | void __init early_init_mmu(void) |
799d6046 | 749 | { |
757c74d2 BH |
750 | /* Setup initial STAB address in the PACA */ |
751 | get_paca()->stab_real = __pa((u64)&initial_stab); | |
752 | get_paca()->stab_addr = (u64)&initial_stab; | |
753 | ||
754 | /* Initialize the MMU Hash table and create the linear mapping | |
755 | * of memory. Has to be done before stab/slb initialization as | |
756 | * this is currently where the page size encoding is obtained | |
757 | */ | |
758 | htab_initialize(); | |
759 | ||
f5339277 | 760 | /* Initialize stab / SLB management */ |
44ae3ab3 | 761 | if (mmu_has_feature(MMU_FTR_SLB)) |
757c74d2 | 762 | slb_initialize(); |
757c74d2 BH |
763 | } |
764 | ||
765 | #ifdef CONFIG_SMP | |
24f1ce80 | 766 | void __cpuinit early_init_mmu_secondary(void) |
757c74d2 BH |
767 | { |
768 | /* Initialize hash table for that CPU */ | |
57cfb814 | 769 | if (!firmware_has_feature(FW_FEATURE_LPAR)) |
799d6046 | 770 | mtspr(SPRN_SDR1, _SDR1); |
757c74d2 BH |
771 | |
772 | /* Initialize STAB/SLB. We use a virtual address as it works | |
f5339277 | 773 | * in real mode on pSeries. |
757c74d2 | 774 | */ |
44ae3ab3 | 775 | if (mmu_has_feature(MMU_FTR_SLB)) |
757c74d2 BH |
776 | slb_initialize(); |
777 | else | |
778 | stab_initialize(get_paca()->stab_addr); | |
799d6046 | 779 | } |
757c74d2 | 780 | #endif /* CONFIG_SMP */ |
799d6046 | 781 | |
1da177e4 LT |
782 | /* |
783 | * Called by asm hashtable.S for doing lazy icache flush | |
784 | */ | |
785 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap) | |
786 | { | |
787 | struct page *page; | |
788 | ||
76c8e25b BH |
789 | if (!pfn_valid(pte_pfn(pte))) |
790 | return pp; | |
791 | ||
1da177e4 LT |
792 | page = pte_page(pte); |
793 | ||
794 | /* page is dirty */ | |
795 | if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) { | |
796 | if (trap == 0x400) { | |
0895ecda | 797 | flush_dcache_icache_page(page); |
1da177e4 LT |
798 | set_bit(PG_arch_1, &page->flags); |
799 | } else | |
3c726f8d | 800 | pp |= HPTE_R_N; |
1da177e4 LT |
801 | } |
802 | return pp; | |
803 | } | |
804 | ||
3a8247cc PM |
805 | #ifdef CONFIG_PPC_MM_SLICES |
806 | unsigned int get_paca_psize(unsigned long addr) | |
807 | { | |
808 | unsigned long index, slices; | |
809 | ||
810 | if (addr < SLICE_LOW_TOP) { | |
811 | slices = get_paca()->context.low_slices_psize; | |
812 | index = GET_LOW_SLICE_INDEX(addr); | |
813 | } else { | |
814 | slices = get_paca()->context.high_slices_psize; | |
815 | index = GET_HIGH_SLICE_INDEX(addr); | |
816 | } | |
817 | return (slices >> (index * 4)) & 0xF; | |
818 | } | |
819 | ||
820 | #else | |
821 | unsigned int get_paca_psize(unsigned long addr) | |
822 | { | |
823 | return get_paca()->context.user_psize; | |
824 | } | |
825 | #endif | |
826 | ||
721151d0 PM |
827 | /* |
828 | * Demote a segment to using 4k pages. | |
829 | * For now this makes the whole process use 4k pages. | |
830 | */ | |
721151d0 | 831 | #ifdef CONFIG_PPC_64K_PAGES |
fa28237c | 832 | void demote_segment_4k(struct mm_struct *mm, unsigned long addr) |
16f1c746 | 833 | { |
3a8247cc | 834 | if (get_slice_psize(mm, addr) == MMU_PAGE_4K) |
721151d0 | 835 | return; |
3a8247cc | 836 | slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K); |
1e57ba8d | 837 | #ifdef CONFIG_SPU_BASE |
721151d0 PM |
838 | spu_flush_all_slbs(mm); |
839 | #endif | |
3a8247cc | 840 | if (get_paca_psize(addr) != MMU_PAGE_4K) { |
fa28237c PM |
841 | get_paca()->context = mm->context; |
842 | slb_flush_and_rebolt(); | |
843 | } | |
721151d0 | 844 | } |
16f1c746 | 845 | #endif /* CONFIG_PPC_64K_PAGES */ |
721151d0 | 846 | |
fa28237c PM |
847 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
848 | /* | |
849 | * This looks up a 2-bit protection code for a 4k subpage of a 64k page. | |
850 | * Userspace sets the subpage permissions using the subpage_prot system call. | |
851 | * | |
852 | * Result is 0: full permissions, _PAGE_RW: read-only, | |
853 | * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access. | |
854 | */ | |
d28513bc | 855 | static int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c | 856 | { |
d28513bc | 857 | struct subpage_prot_table *spt = &mm->context.spt; |
fa28237c PM |
858 | u32 spp = 0; |
859 | u32 **sbpm, *sbpp; | |
860 | ||
861 | if (ea >= spt->maxaddr) | |
862 | return 0; | |
863 | if (ea < 0x100000000) { | |
864 | /* addresses below 4GB use spt->low_prot */ | |
865 | sbpm = spt->low_prot; | |
866 | } else { | |
867 | sbpm = spt->protptrs[ea >> SBP_L3_SHIFT]; | |
868 | if (!sbpm) | |
869 | return 0; | |
870 | } | |
871 | sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)]; | |
872 | if (!sbpp) | |
873 | return 0; | |
874 | spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)]; | |
875 | ||
876 | /* extract 2-bit bitfield for this 4k subpage */ | |
877 | spp >>= 30 - 2 * ((ea >> 12) & 0xf); | |
878 | ||
879 | /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */ | |
880 | spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0); | |
881 | return spp; | |
882 | } | |
883 | ||
884 | #else /* CONFIG_PPC_SUBPAGE_PROT */ | |
d28513bc | 885 | static inline int subpage_protection(struct mm_struct *mm, unsigned long ea) |
fa28237c PM |
886 | { |
887 | return 0; | |
888 | } | |
889 | #endif | |
890 | ||
4b8692c0 BH |
891 | void hash_failure_debug(unsigned long ea, unsigned long access, |
892 | unsigned long vsid, unsigned long trap, | |
893 | int ssize, int psize, unsigned long pte) | |
894 | { | |
895 | if (!printk_ratelimit()) | |
896 | return; | |
897 | pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n", | |
898 | ea, access, current->comm); | |
899 | pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n", | |
900 | trap, vsid, ssize, psize, pte); | |
901 | } | |
902 | ||
1da177e4 LT |
903 | /* Result code is: |
904 | * 0 - handled | |
905 | * 1 - normal page fault | |
906 | * -1 - critical hash insertion error | |
fa28237c | 907 | * -2 - access not permitted by subpage protection mechanism |
1da177e4 LT |
908 | */ |
909 | int hash_page(unsigned long ea, unsigned long access, unsigned long trap) | |
910 | { | |
a1128f8f | 911 | pgd_t *pgdir; |
1da177e4 LT |
912 | unsigned long vsid; |
913 | struct mm_struct *mm; | |
914 | pte_t *ptep; | |
a4fe3ce7 | 915 | unsigned hugeshift; |
56aa4129 | 916 | const struct cpumask *tmp; |
3c726f8d | 917 | int rc, user_region = 0, local = 0; |
1189be65 | 918 | int psize, ssize; |
1da177e4 | 919 | |
3c726f8d BH |
920 | DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n", |
921 | ea, access, trap); | |
1f8d419e | 922 | |
3c726f8d BH |
923 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) { |
924 | DBG_LOW(" out of pgtable range !\n"); | |
925 | return 1; | |
926 | } | |
927 | ||
928 | /* Get region & vsid */ | |
1da177e4 LT |
929 | switch (REGION_ID(ea)) { |
930 | case USER_REGION_ID: | |
931 | user_region = 1; | |
932 | mm = current->mm; | |
3c726f8d BH |
933 | if (! mm) { |
934 | DBG_LOW(" user region with no mm !\n"); | |
1da177e4 | 935 | return 1; |
3c726f8d | 936 | } |
16c2d476 | 937 | psize = get_slice_psize(mm, ea); |
1189be65 PM |
938 | ssize = user_segment_size(ea); |
939 | vsid = get_vsid(mm->context.id, ea, ssize); | |
1da177e4 | 940 | break; |
1da177e4 | 941 | case VMALLOC_REGION_ID: |
1da177e4 | 942 | mm = &init_mm; |
1189be65 | 943 | vsid = get_kernel_vsid(ea, mmu_kernel_ssize); |
bf72aeba PM |
944 | if (ea < VMALLOC_END) |
945 | psize = mmu_vmalloc_psize; | |
946 | else | |
947 | psize = mmu_io_psize; | |
1189be65 | 948 | ssize = mmu_kernel_ssize; |
1da177e4 | 949 | break; |
1da177e4 LT |
950 | default: |
951 | /* Not a valid range | |
952 | * Send the problem up to do_page_fault | |
953 | */ | |
954 | return 1; | |
1da177e4 | 955 | } |
3c726f8d | 956 | DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid); |
1da177e4 | 957 | |
3c726f8d | 958 | /* Get pgdir */ |
1da177e4 | 959 | pgdir = mm->pgd; |
1da177e4 LT |
960 | if (pgdir == NULL) |
961 | return 1; | |
962 | ||
3c726f8d | 963 | /* Check CPU locality */ |
56aa4129 RR |
964 | tmp = cpumask_of(smp_processor_id()); |
965 | if (user_region && cpumask_equal(mm_cpumask(mm), tmp)) | |
1da177e4 LT |
966 | local = 1; |
967 | ||
16c2d476 | 968 | #ifndef CONFIG_PPC_64K_PAGES |
a4fe3ce7 DG |
969 | /* If we use 4K pages and our psize is not 4K, then we might |
970 | * be hitting a special driver mapping, and need to align the | |
971 | * address before we fetch the PTE. | |
972 | * | |
973 | * It could also be a hugepage mapping, in which case this is | |
974 | * not necessary, but it's not harmful, either. | |
16c2d476 BH |
975 | */ |
976 | if (psize != MMU_PAGE_4K) | |
977 | ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1); | |
978 | #endif /* CONFIG_PPC_64K_PAGES */ | |
979 | ||
3c726f8d | 980 | /* Get PTE and page size from page tables */ |
a4fe3ce7 | 981 | ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugeshift); |
3c726f8d BH |
982 | if (ptep == NULL || !pte_present(*ptep)) { |
983 | DBG_LOW(" no PTE !\n"); | |
984 | return 1; | |
985 | } | |
986 | ||
ca91e6c0 BH |
987 | /* Add _PAGE_PRESENT to the required access perm */ |
988 | access |= _PAGE_PRESENT; | |
989 | ||
990 | /* Pre-check access permissions (will be re-checked atomically | |
991 | * in __hash_page_XX but this pre-check is a fast path | |
992 | */ | |
993 | if (access & ~pte_val(*ptep)) { | |
994 | DBG_LOW(" no access !\n"); | |
995 | return 1; | |
996 | } | |
997 | ||
a4fe3ce7 DG |
998 | #ifdef CONFIG_HUGETLB_PAGE |
999 | if (hugeshift) | |
1000 | return __hash_page_huge(ea, access, vsid, ptep, trap, local, | |
1001 | ssize, hugeshift, psize); | |
1002 | #endif /* CONFIG_HUGETLB_PAGE */ | |
1003 | ||
3c726f8d BH |
1004 | #ifndef CONFIG_PPC_64K_PAGES |
1005 | DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep)); | |
1006 | #else | |
1007 | DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep), | |
1008 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1009 | #endif | |
3c726f8d | 1010 | /* Do actual hashing */ |
16c2d476 | 1011 | #ifdef CONFIG_PPC_64K_PAGES |
721151d0 | 1012 | /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */ |
3a8247cc | 1013 | if ((pte_val(*ptep) & _PAGE_4K_PFN) && psize == MMU_PAGE_64K) { |
721151d0 PM |
1014 | demote_segment_4k(mm, ea); |
1015 | psize = MMU_PAGE_4K; | |
1016 | } | |
1017 | ||
16f1c746 BH |
1018 | /* If this PTE is non-cacheable and we have restrictions on |
1019 | * using non cacheable large pages, then we switch to 4k | |
1020 | */ | |
1021 | if (mmu_ci_restrictions && psize == MMU_PAGE_64K && | |
1022 | (pte_val(*ptep) & _PAGE_NO_CACHE)) { | |
1023 | if (user_region) { | |
1024 | demote_segment_4k(mm, ea); | |
1025 | psize = MMU_PAGE_4K; | |
1026 | } else if (ea < VMALLOC_END) { | |
1027 | /* | |
1028 | * some driver did a non-cacheable mapping | |
1029 | * in vmalloc space, so switch vmalloc | |
1030 | * to 4k pages | |
1031 | */ | |
1032 | printk(KERN_ALERT "Reducing vmalloc segment " | |
1033 | "to 4kB pages because of " | |
1034 | "non-cacheable mapping\n"); | |
1035 | psize = mmu_vmalloc_psize = MMU_PAGE_4K; | |
1e57ba8d | 1036 | #ifdef CONFIG_SPU_BASE |
94b2a439 BH |
1037 | spu_flush_all_slbs(mm); |
1038 | #endif | |
bf72aeba | 1039 | } |
16f1c746 BH |
1040 | } |
1041 | if (user_region) { | |
3a8247cc | 1042 | if (psize != get_paca_psize(ea)) { |
f6ab0b92 | 1043 | get_paca()->context = mm->context; |
bf72aeba PM |
1044 | slb_flush_and_rebolt(); |
1045 | } | |
16f1c746 BH |
1046 | } else if (get_paca()->vmalloc_sllp != |
1047 | mmu_psize_defs[mmu_vmalloc_psize].sllp) { | |
1048 | get_paca()->vmalloc_sllp = | |
1049 | mmu_psize_defs[mmu_vmalloc_psize].sllp; | |
67439b76 | 1050 | slb_vmalloc_update(); |
bf72aeba | 1051 | } |
16c2d476 | 1052 | #endif /* CONFIG_PPC_64K_PAGES */ |
16f1c746 | 1053 | |
16c2d476 | 1054 | #ifdef CONFIG_PPC_HAS_HASH_64K |
bf72aeba | 1055 | if (psize == MMU_PAGE_64K) |
1189be65 | 1056 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
3c726f8d | 1057 | else |
16c2d476 | 1058 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
fa28237c | 1059 | { |
a1128f8f | 1060 | int spp = subpage_protection(mm, ea); |
fa28237c PM |
1061 | if (access & spp) |
1062 | rc = -2; | |
1063 | else | |
1064 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, | |
1065 | local, ssize, spp); | |
1066 | } | |
3c726f8d | 1067 | |
4b8692c0 BH |
1068 | /* Dump some info in case of hash insertion failure, they should |
1069 | * never happen so it is really useful to know if/when they do | |
1070 | */ | |
1071 | if (rc == -1) | |
1072 | hash_failure_debug(ea, access, vsid, trap, ssize, psize, | |
1073 | pte_val(*ptep)); | |
3c726f8d BH |
1074 | #ifndef CONFIG_PPC_64K_PAGES |
1075 | DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep)); | |
1076 | #else | |
1077 | DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep), | |
1078 | pte_val(*(ptep + PTRS_PER_PTE))); | |
1079 | #endif | |
1080 | DBG_LOW(" -> rc=%d\n", rc); | |
1081 | return rc; | |
1da177e4 | 1082 | } |
67207b96 | 1083 | EXPORT_SYMBOL_GPL(hash_page); |
1da177e4 | 1084 | |
3c726f8d BH |
1085 | void hash_preload(struct mm_struct *mm, unsigned long ea, |
1086 | unsigned long access, unsigned long trap) | |
1da177e4 | 1087 | { |
3c726f8d | 1088 | unsigned long vsid; |
0b97fee0 | 1089 | pgd_t *pgdir; |
3c726f8d | 1090 | pte_t *ptep; |
3c726f8d | 1091 | unsigned long flags; |
4b8692c0 | 1092 | int rc, ssize, local = 0; |
3c726f8d | 1093 | |
d0f13e3c BH |
1094 | BUG_ON(REGION_ID(ea) != USER_REGION_ID); |
1095 | ||
1096 | #ifdef CONFIG_PPC_MM_SLICES | |
1097 | /* We only prefault standard pages for now */ | |
2b02d139 | 1098 | if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize)) |
3c726f8d | 1099 | return; |
d0f13e3c | 1100 | #endif |
3c726f8d BH |
1101 | |
1102 | DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx," | |
1103 | " trap=%lx\n", mm, mm->pgd, ea, access, trap); | |
1da177e4 | 1104 | |
16f1c746 | 1105 | /* Get Linux PTE if available */ |
3c726f8d BH |
1106 | pgdir = mm->pgd; |
1107 | if (pgdir == NULL) | |
1108 | return; | |
1109 | ptep = find_linux_pte(pgdir, ea); | |
1110 | if (!ptep) | |
1111 | return; | |
16f1c746 BH |
1112 | |
1113 | #ifdef CONFIG_PPC_64K_PAGES | |
1114 | /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on | |
1115 | * a 64K kernel), then we don't preload, hash_page() will take | |
1116 | * care of it once we actually try to access the page. | |
1117 | * That way we don't have to duplicate all of the logic for segment | |
1118 | * page size demotion here | |
1119 | */ | |
1120 | if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE)) | |
1121 | return; | |
1122 | #endif /* CONFIG_PPC_64K_PAGES */ | |
1123 | ||
1124 | /* Get VSID */ | |
1189be65 PM |
1125 | ssize = user_segment_size(ea); |
1126 | vsid = get_vsid(mm->context.id, ea, ssize); | |
3c726f8d | 1127 | |
16c2d476 | 1128 | /* Hash doesn't like irqs */ |
3c726f8d | 1129 | local_irq_save(flags); |
16c2d476 BH |
1130 | |
1131 | /* Is that local to this CPU ? */ | |
56aa4129 | 1132 | if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) |
3c726f8d | 1133 | local = 1; |
16c2d476 BH |
1134 | |
1135 | /* Hash it in */ | |
1136 | #ifdef CONFIG_PPC_HAS_HASH_64K | |
bf72aeba | 1137 | if (mm->context.user_psize == MMU_PAGE_64K) |
4b8692c0 | 1138 | rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize); |
1da177e4 | 1139 | else |
5b825831 | 1140 | #endif /* CONFIG_PPC_HAS_HASH_64K */ |
4b8692c0 | 1141 | rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize, |
1c2c25c7 | 1142 | subpage_protection(mm, ea)); |
4b8692c0 BH |
1143 | |
1144 | /* Dump some info in case of hash insertion failure, they should | |
1145 | * never happen so it is really useful to know if/when they do | |
1146 | */ | |
1147 | if (rc == -1) | |
1148 | hash_failure_debug(ea, access, vsid, trap, ssize, | |
1149 | mm->context.user_psize, pte_val(*ptep)); | |
16c2d476 | 1150 | |
3c726f8d BH |
1151 | local_irq_restore(flags); |
1152 | } | |
1153 | ||
f6ab0b92 BH |
1154 | /* WARNING: This is called from hash_low_64.S, if you change this prototype, |
1155 | * do not forget to update the assembly call site ! | |
1156 | */ | |
1189be65 PM |
1157 | void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize, |
1158 | int local) | |
3c726f8d BH |
1159 | { |
1160 | unsigned long hash, index, shift, hidx, slot; | |
1161 | ||
5c339919 | 1162 | DBG_LOW("flush_hash_page(va=%016lx)\n", va); |
3c726f8d | 1163 | pte_iterate_hashed_subpages(pte, psize, va, index, shift) { |
1189be65 | 1164 | hash = hpt_hash(va, shift, ssize); |
3c726f8d BH |
1165 | hidx = __rpte_to_hidx(pte, index); |
1166 | if (hidx & _PTEIDX_SECONDARY) | |
1167 | hash = ~hash; | |
1168 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1169 | slot += hidx & _PTEIDX_GROUP_IX; | |
5c339919 | 1170 | DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx); |
1189be65 | 1171 | ppc_md.hpte_invalidate(slot, va, psize, ssize, local); |
3c726f8d | 1172 | } pte_iterate_hashed_end(); |
1da177e4 LT |
1173 | } |
1174 | ||
61b1a942 | 1175 | void flush_hash_range(unsigned long number, int local) |
1da177e4 | 1176 | { |
3c726f8d | 1177 | if (ppc_md.flush_hash_range) |
61b1a942 | 1178 | ppc_md.flush_hash_range(number, local); |
3c726f8d | 1179 | else { |
1da177e4 | 1180 | int i; |
61b1a942 BH |
1181 | struct ppc64_tlb_batch *batch = |
1182 | &__get_cpu_var(ppc64_tlb_batch); | |
1da177e4 LT |
1183 | |
1184 | for (i = 0; i < number; i++) | |
3c726f8d | 1185 | flush_hash_page(batch->vaddr[i], batch->pte[i], |
1189be65 | 1186 | batch->psize, batch->ssize, local); |
1da177e4 LT |
1187 | } |
1188 | } | |
1189 | ||
1da177e4 LT |
1190 | /* |
1191 | * low_hash_fault is called when we the low level hash code failed | |
1192 | * to instert a PTE due to an hypervisor error | |
1193 | */ | |
fa28237c | 1194 | void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc) |
1da177e4 LT |
1195 | { |
1196 | if (user_mode(regs)) { | |
fa28237c PM |
1197 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
1198 | if (rc == -2) | |
1199 | _exception(SIGSEGV, regs, SEGV_ACCERR, address); | |
1200 | else | |
1201 | #endif | |
1202 | _exception(SIGBUS, regs, BUS_ADRERR, address); | |
1203 | } else | |
1204 | bad_page_fault(regs, address, SIGBUS); | |
1da177e4 | 1205 | } |
370a908d BH |
1206 | |
1207 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
1208 | static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi) | |
1209 | { | |
1189be65 PM |
1210 | unsigned long hash, hpteg; |
1211 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1212 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
bc033b63 | 1213 | unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL); |
370a908d BH |
1214 | int ret; |
1215 | ||
1189be65 | 1216 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1217 | hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); |
1218 | ||
1219 | ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr), | |
1189be65 PM |
1220 | mode, HPTE_V_BOLTED, |
1221 | mmu_linear_psize, mmu_kernel_ssize); | |
370a908d BH |
1222 | BUG_ON (ret < 0); |
1223 | spin_lock(&linear_map_hash_lock); | |
1224 | BUG_ON(linear_map_hash_slots[lmi] & 0x80); | |
1225 | linear_map_hash_slots[lmi] = ret | 0x80; | |
1226 | spin_unlock(&linear_map_hash_lock); | |
1227 | } | |
1228 | ||
1229 | static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi) | |
1230 | { | |
1189be65 PM |
1231 | unsigned long hash, hidx, slot; |
1232 | unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize); | |
1233 | unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize); | |
370a908d | 1234 | |
1189be65 | 1235 | hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize); |
370a908d BH |
1236 | spin_lock(&linear_map_hash_lock); |
1237 | BUG_ON(!(linear_map_hash_slots[lmi] & 0x80)); | |
1238 | hidx = linear_map_hash_slots[lmi] & 0x7f; | |
1239 | linear_map_hash_slots[lmi] = 0; | |
1240 | spin_unlock(&linear_map_hash_lock); | |
1241 | if (hidx & _PTEIDX_SECONDARY) | |
1242 | hash = ~hash; | |
1243 | slot = (hash & htab_hash_mask) * HPTES_PER_GROUP; | |
1244 | slot += hidx & _PTEIDX_GROUP_IX; | |
1189be65 | 1245 | ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0); |
370a908d BH |
1246 | } |
1247 | ||
1248 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
1249 | { | |
1250 | unsigned long flags, vaddr, lmi; | |
1251 | int i; | |
1252 | ||
1253 | local_irq_save(flags); | |
1254 | for (i = 0; i < numpages; i++, page++) { | |
1255 | vaddr = (unsigned long)page_address(page); | |
1256 | lmi = __pa(vaddr) >> PAGE_SHIFT; | |
1257 | if (lmi >= linear_map_hash_count) | |
1258 | continue; | |
1259 | if (enable) | |
1260 | kernel_map_linear_page(vaddr, lmi); | |
1261 | else | |
1262 | kernel_unmap_linear_page(vaddr, lmi); | |
1263 | } | |
1264 | local_irq_restore(flags); | |
1265 | } | |
1266 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
cd3db0c4 BH |
1267 | |
1268 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
1269 | phys_addr_t first_memblock_size) | |
1270 | { | |
1271 | /* We don't currently support the first MEMBLOCK not mapping 0 | |
1272 | * physical on those processors | |
1273 | */ | |
1274 | BUG_ON(first_memblock_base != 0); | |
1275 | ||
1276 | /* On LPAR systems, the first entry is our RMA region, | |
1277 | * non-LPAR 64-bit hash MMU systems don't have a limitation | |
1278 | * on real mode access, but using the first entry works well | |
1279 | * enough. We also clamp it to 1G to avoid some funky things | |
1280 | * such as RTAS bugs etc... | |
1281 | */ | |
1282 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
1283 | ||
1284 | /* Finally limit subsequent allocations */ | |
1285 | memblock_set_current_limit(ppc64_rma_size); | |
1286 | } |