projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 14cf11af PM |
1 | /* |
| 2 | * Declarations of procedures and variables shared between files | |
| 3 | * in arch/ppc/mm/. | |
| 4 | * | |
| 5 | * Derived from arch/ppc/mm/init.c: | |
| 6 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
| 7 | * | |
| 8 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
| 9 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
| 10 | * Copyright (C) 1996 Paul Mackerras | |
| 14cf11af PM |
11 | * |
| 12 | * Derived from "arch/i386/mm/init.c" | |
| 13 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or | |
| 16 | * modify it under the terms of the GNU General Public License | |
| 17 | * as published by the Free Software Foundation; either version | |
| 18 | * 2 of the License, or (at your option) any later version. | |
| 19 | * | |
| 20 | */ | |
| 62102307 | 21 | #include <linux/mm.h> |
| 14cf11af PM |
22 | #include <asm/tlbflush.h> |
| 23 | #include <asm/mmu.h> | |
| 24 | ||
| ee4f2ea4 BH |
25 | extern void hash_preload(struct mm_struct *mm, unsigned long ea, |
| 26 | unsigned long access, unsigned long trap); | |
| 27 | ||
| 28 | ||
| ab1f9dac | 29 | #ifdef CONFIG_PPC32 |
| 14cf11af PM |
30 | extern void mapin_ram(void); |
| 31 | extern int map_page(unsigned long va, phys_addr_t pa, int flags); | |
| 7c5c4325 | 32 | extern void setbat(int index, unsigned long virt, phys_addr_t phys, |
| 14cf11af | 33 | unsigned int size, int flags); |
| 14cf11af PM |
34 | extern void settlbcam(int index, unsigned long virt, phys_addr_t phys, |
| 35 | unsigned int size, int flags, unsigned int pid); | |
| 36 | extern void invalidate_tlbcam_entry(int index); | |
| 37 | ||
| 38 | extern int __map_without_bats; | |
| 39 | extern unsigned long ioremap_base; | |
| 14cf11af PM |
40 | extern unsigned int rtas_data, rtas_size; |
| 41 | ||
| 8e561e7e DG |
42 | struct hash_pte; |
| 43 | extern struct hash_pte *Hash, *Hash_end; | |
| 14cf11af PM |
44 | extern unsigned long Hash_size, Hash_mask; |
| 45 | ||
| 46 | extern unsigned int num_tlbcam_entries; | |
| ab1f9dac PM |
47 | #endif |
| 48 | ||
| 800fc3ee | 49 | extern unsigned long ioremap_bot; |
| ab1f9dac | 50 | extern unsigned long __max_low_memory; |
| 09b5e63f | 51 | extern phys_addr_t __initial_memory_limit_addr; |
| 2bf3016f SR |
52 | extern phys_addr_t total_memory; |
| 53 | extern phys_addr_t total_lowmem; | |
| 99c62dd7 | 54 | extern phys_addr_t memstart_addr; |
| d7917ba7 | 55 | extern phys_addr_t lowmem_end_addr; |
| 14cf11af PM |
56 | |
| 57 | /* ...and now those things that may be slightly different between processor | |
| 58 | * architectures. -- Dan | |
| 59 | */ | |
| 60 | #if defined(CONFIG_8xx) | |
| 0b47759d | 61 | #define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */) |
| 14cf11af PM |
62 | #define MMU_init_hw() do { } while(0) |
| 63 | #define mmu_mapin_ram() (0UL) | |
| 64 | ||
| 65 | #elif defined(CONFIG_4xx) | |
| e701d269 | 66 | #define flush_HPTE(pid, va, pg) _tlbie(va, pid) |
| 14cf11af PM |
67 | extern void MMU_init_hw(void); |
| 68 | extern unsigned long mmu_mapin_ram(void); | |
| 69 | ||
| 70 | #elif defined(CONFIG_FSL_BOOKE) | |
| e701d269 | 71 | #define flush_HPTE(pid, va, pg) _tlbie(va, pid) |
| 14cf11af PM |
72 | extern void MMU_init_hw(void); |
| 73 | extern unsigned long mmu_mapin_ram(void); | |
| 74 | extern void adjust_total_lowmem(void); | |
| 75 | ||
| ab1f9dac PM |
76 | #elif defined(CONFIG_PPC32) |
| 77 | /* anything 32-bit except 4xx or 8xx */ | |
| 14cf11af PM |
78 | extern void MMU_init_hw(void); |
| 79 | extern unsigned long mmu_mapin_ram(void); | |
| 80 | ||
| 81 | /* Be careful....this needs to be updated if we ever encounter 603 SMPs, | |
| 82 | * which includes all new 82xx processors. We need tlbie/tlbsync here | |
| 83 | * in that case (I think). -- Dan. | |
| 84 | */ | |
| 85 | static inline void flush_HPTE(unsigned context, unsigned long va, | |
| 86 | unsigned long pdval) | |
| 87 | { | |
| 88 | if ((Hash != 0) && | |
| 89 | cpu_has_feature(CPU_FTR_HPTE_TABLE)) | |
| 90 | flush_hash_pages(0, va, pdval, 1); | |
| 91 | else | |
| 92 | _tlbie(va); | |
| 93 | } | |
| 94 | #endif |