[deliverable/linux.git] / arch / powerpc / mm / slb_low.S

/*
 * Low-level SLB routines
 *
 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
 *
 * Based on earlier C version:
 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
 *    Copyright (c) 2001 Dave Engebretsen
 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <asm/processor.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cputable.h>
#include <asm/page.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/firmware.h>

/* void slb_allocate_realmode(unsigned long ea);
 *
 * Create an SLB entry for the given EA (user or kernel).
 * 	r3 = faulting address, r13 = PACA
 *	r9, r10, r11 are clobbered by this function
 * No other registers are examined or changed.
 */
_GLOBAL(slb_allocate_realmode)
	/*
	 * check for bad kernel/user address
	 * (ea & ~REGION_MASK) >= PGTABLE_RANGE
	 */
	rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
	bne-	8f

	srdi	r9,r3,60		/* get region */
	srdi	r10,r3,SID_SHIFT	/* get esid */
	cmpldi	cr7,r9,0xc		/* cmp PAGE_OFFSET for later use */

	/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
	blt	cr7,0f			/* user or kernel? */

	/* kernel address: proto-VSID = ESID */
	/* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
	 * this code will generate the protoVSID 0xfffffffff for the
	 * top segment.  That's ok, the scramble below will translate
	 * it to VSID 0, which is reserved as a bad VSID - one which
	 * will never have any pages in it.  */

	/* Check if hitting the linear mapping or some other kernel space
	*/
	bne	cr7,1f

	/* Linear mapping encoding bits, the "li" instruction below will
	 * be patched by the kernel at boot
	 */
.globl slb_miss_kernel_load_linear
slb_miss_kernel_load_linear:
	li	r11,0
	/*
	 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
	 * r9 = region id.
	 */
	addis	r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
	addi	r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l


BEGIN_FTR_SECTION
	b	slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
	b	slb_finish_load_1T

1:
#ifdef CONFIG_SPARSEMEM_VMEMMAP
	/* Check virtual memmap region. To be patches at kernel boot */
	cmpldi	cr0,r9,0xf
	bne	1f
.globl slb_miss_kernel_load_vmemmap
slb_miss_kernel_load_vmemmap:
	li	r11,0
	b	6f
1:
#endif /* CONFIG_SPARSEMEM_VMEMMAP */

	/* vmalloc mapping gets the encoding from the PACA as the mapping
	 * can be demoted from 64K -> 4K dynamically on some machines
	 */
	clrldi	r11,r10,48
	cmpldi	r11,(H_VMALLOC_SIZE >> 28) - 1
	bgt	5f
	lhz	r11,PACAVMALLOCSLLP(r13)
	b	6f
5:
	/* IO mapping */
.globl slb_miss_kernel_load_io
slb_miss_kernel_load_io:
	li	r11,0
6:
	/*
	 * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
	 * r9 = region id.
	 */
	addis	r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
	addi	r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l

BEGIN_FTR_SECTION
	b	slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
	b	slb_finish_load_1T

0:
	/* when using slices, we extract the psize off the slice bitmaps
	 * and then we need to get the sllp encoding off the mmu_psize_defs
	 * array.
	 *
	 * XXX This is a bit inefficient especially for the normal case,
	 * so we should try to implement a fast path for the standard page
	 * size using the old sllp value so we avoid the array. We cannot
	 * really do dynamic patching unfortunately as processes might flip
	 * between 4k and 64k standard page size
	 */
#ifdef CONFIG_PPC_MM_SLICES
	/* r10 have esid */
	cmpldi	r10,16
	/* below SLICE_LOW_TOP */
	blt	5f
	/*
	 * Handle hpsizes,
	 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
	 */
	srdi    r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
	addi	r9,r11,PACAHIGHSLICEPSIZE
	lbzx	r9,r13,r9		/* r9 is hpsizes[r11] */
	/* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
	rldicl	r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
	b	6f

5:
	/*
	 * Handle lpsizes
	 * r9 is get_paca()->context.low_slices_psize, r11 is index
	 */
	ld	r9,PACALOWSLICESPSIZE(r13)
	mr	r11,r10
6:
	sldi	r11,r11,2  /* index * 4 */
	/* Extract the psize and multiply to get an array offset */
	srd	r9,r9,r11
	andi.	r9,r9,0xf
	mulli	r9,r9,MMUPSIZEDEFSIZE

	/* Now get to the array and obtain the sllp
	 */
	ld	r11,PACATOC(r13)
	ld	r11,mmu_psize_defs@got(r11)
	add	r11,r11,r9
	ld	r11,MMUPSIZESLLP(r11)
	ori	r11,r11,SLB_VSID_USER
#else
	/* paca context sllp already contains the SLB_VSID_USER bits */
	lhz	r11,PACACONTEXTSLLP(r13)
#endif /* CONFIG_PPC_MM_SLICES */

	ld	r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
	cmpldi	r10,0x1000
	bge	slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
	b	slb_finish_load

8:	/* invalid EA */
	li	r10,0			/* BAD_VSID */
	li	r9,0			/* BAD_VSID */
	li	r11,SLB_VSID_USER	/* flags don't much matter */
	b	slb_finish_load

/*
 * Finish loading of an SLB entry and return
 *
 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
 */
slb_finish_load:
	rldimi  r10,r9,ESID_BITS,0
	ASM_VSID_SCRAMBLE(r10,r9,256M)
	/*
	 * bits above VSID_BITS_256M need to be ignored from r10
	 * also combine VSID and flags
	 */
	rldimi	r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))

	/* r3 = EA, r11 = VSID data */
	/*
	 * Find a slot, round robin. Previously we tried to find a
	 * free slot first but that took too long. Unfortunately we
 	 * dont have any LRU information to help us choose a slot.
 	 */

7:	ld	r10,PACASTABRR(r13)
	addi	r10,r10,1
	/* This gets soft patched on boot. */
.globl slb_compare_rr_to_size
slb_compare_rr_to_size:
	cmpldi	r10,0

	blt+	4f
	li	r10,SLB_NUM_BOLTED

4:
	std	r10,PACASTABRR(r13)

3:
	rldimi	r3,r10,0,36		/* r3= EA[0:35] | entry */
	oris	r10,r3,SLB_ESID_V@h	/* r3 |= SLB_ESID_V */

	/* r3 = ESID data, r11 = VSID data */

	/*
	 * No need for an isync before or after this slbmte. The exception
	 * we enter with and the rfid we exit with are context synchronizing.
	 */
	slbmte	r11,r10

	/* we're done for kernel addresses */
	crclr	4*cr0+eq		/* set result to "success" */
	bgelr	cr7

	/* Update the slb cache */
	lhz	r3,PACASLBCACHEPTR(r13)	/* offset = paca->slb_cache_ptr */
	cmpldi	r3,SLB_CACHE_ENTRIES
	bge	1f

	/* still room in the slb cache */
	sldi	r11,r3,2		/* r11 = offset * sizeof(u32) */
	srdi    r10,r10,28		/* get the 36 bits of the ESID */
	add	r11,r11,r13		/* r11 = (u32 *)paca + offset */
	stw	r10,PACASLBCACHE(r11)	/* paca->slb_cache[offset] = esid */
	addi	r3,r3,1			/* offset++ */
	b	2f
1:					/* offset >= SLB_CACHE_ENTRIES */
	li	r3,SLB_CACHE_ENTRIES+1
2:
	sth	r3,PACASLBCACHEPTR(r13)	/* paca->slb_cache_ptr = offset */
	crclr	4*cr0+eq		/* set result to "success" */
	blr

/*
 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
 *
 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
 */
slb_finish_load_1T:
	srdi	r10,r10,(SID_SHIFT_1T - SID_SHIFT)	/* get 1T ESID */
	rldimi  r10,r9,ESID_BITS_1T,0
	ASM_VSID_SCRAMBLE(r10,r9,1T)
	/*
	 * bits above VSID_BITS_1T need to be ignored from r10
	 * also combine VSID and flags
	 */
	rldimi	r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
	li	r10,MMU_SEGSIZE_1T
	rldimi	r11,r10,SLB_VSID_SSIZE_SHIFT,0	/* insert segment size */

	/* r3 = EA, r11 = VSID data */
	clrrdi	r3,r3,SID_SHIFT_1T	/* clear out non-ESID bits */
	b	7b
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Low-level SLB routines
	3	*
	4	* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
	5	*
	6	* Based on earlier C version:
	7	* Dave Engebretsen and Mike Corrigan {engebret\|mikejc}@us.ibm.com
	8	* Copyright (c) 2001 Dave Engebretsen
	9	* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* as published by the Free Software Foundation; either version
	14	* 2 of the License, or (at your option) any later version.
	15	*/
	16
1da177e4	17	#include <asm/processor.h>
1da177e4	18	#include <asm/ppc_asm.h>
0013a854	19	#include <asm/asm-offsets.h>
1da177e4	20	#include <asm/cputable.h>
3c726f8d BH	21	#include <asm/page.h>
	22	#include <asm/mmu.h>
	23	#include <asm/pgtable.h>
3f639ee8	24	#include <asm/firmware.h>
1da177e4	25
3c726f8d	26	/* void slb_allocate_realmode(unsigned long ea);
1da177e4 LT	27	*
	28	* Create an SLB entry for the given EA (user or kernel).
	29	* r3 = faulting address, r13 = PACA
	30	* r9, r10, r11 are clobbered by this function
	31	* No other registers are examined or changed.
	32	*/
3c726f8d	33	_GLOBAL(slb_allocate_realmode)
c60ac569 AK	34	/*
	35	* check for bad kernel/user address
	36	* (ea & ~REGION_MASK) >= PGTABLE_RANGE
	37	*/
dd1842a2	38	rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
c60ac569	39	bne- 8f
1da177e4 LT	40
1da177e4 LT	41	srdi r9,r3,60 /* get region */
c60ac569	42	srdi r10,r3,SID_SHIFT /* get esid */
b5666f70	43	cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
1da177e4	44
b5666f70	45	/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
1da177e4 LT	46	blt cr7,0f /* user or kernel? */
	47
	48	/* kernel address: proto-VSID = ESID */
	49	/* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
	50	* this code will generate the protoVSID 0xfffffffff for the
	51	* top segment. That's ok, the scramble below will translate
	52	* it to VSID 0, which is reserved as a bad VSID - one which
	53	* will never have any pages in it. */
1da177e4	54
cec08e7a	55	/* Check if hitting the linear mapping or some other kernel space
3c726f8d BH	56	*/
	57	bne cr7,1f
	58
	59	/* Linear mapping encoding bits, the "li" instruction below will
	60	* be patched by the kernel at boot
	61	*/
b86206e4 AB	62	.globl slb_miss_kernel_load_linear
b86206e4 AB	63	slb_miss_kernel_load_linear:
3c726f8d	64	li r11,0
048ee099	65	/*
c60ac569 AK	66	* context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
c60ac569 AK	67	* r9 = region id.
048ee099	68	*/
c60ac569 AK	69	addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
	70	addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
	71
	72
1189be65	73	BEGIN_FTR_SECTION
3c726f8d	74	b slb_finish_load
44ae3ab3	75	END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
1189be65	76	b slb_finish_load_1T
3c726f8d	77
cec08e7a BH	78	1:
	79	#ifdef CONFIG_SPARSEMEM_VMEMMAP
	80	/* Check virtual memmap region. To be patches at kernel boot */
	81	cmpldi cr0,r9,0xf
	82	bne 1f
b86206e4 AB	83	.globl slb_miss_kernel_load_vmemmap
b86206e4 AB	84	slb_miss_kernel_load_vmemmap:
cec08e7a BH	85	li r11,0
	86	b 6f
	87	1:
	88	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
	89
8d8997f3 BH	90	/* vmalloc mapping gets the encoding from the PACA as the mapping
8d8997f3 BH	91	* can be demoted from 64K -> 4K dynamically on some machines
3c726f8d	92	*/
bf72aeba	93	clrldi r11,r10,48
d6a9996e	94	cmpldi r11,(H_VMALLOC_SIZE >> 28) - 1
bf72aeba PM	95	bgt 5f
bf72aeba PM	96	lhz r11,PACAVMALLOCSLLP(r13)
1189be65	97	b 6f
bf72aeba	98	5:
8d8997f3	99	/* IO mapping */
b86206e4 AB	100	.globl slb_miss_kernel_load_io
b86206e4 AB	101	slb_miss_kernel_load_io:
3c726f8d	102	li r11,0
1189be65	103	6:
048ee099	104	/*
c60ac569 AK	105	* context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
c60ac569 AK	106	* r9 = region id.
048ee099	107	*/
c60ac569 AK	108	addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
	109	addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
	110
1189be65	111	BEGIN_FTR_SECTION
3c726f8d	112	b slb_finish_load
44ae3ab3	113	END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
1189be65	114	b slb_finish_load_1T
3c726f8d	115
c60ac569	116	0:
d0f13e3c BH	117	/* when using slices, we extract the psize off the slice bitmaps
	118	* and then we need to get the sllp encoding off the mmu_psize_defs
	119	* array.
	120	*
	121	* XXX This is a bit inefficient especially for the normal case,
	122	* so we should try to implement a fast path for the standard page
	123	* size using the old sllp value so we avoid the array. We cannot
	124	* really do dynamic patching unfortunately as processes might flip
	125	* between 4k and 64k standard page size
	126	*/
	127	#ifdef CONFIG_PPC_MM_SLICES
7aa0727f	128	/* r10 have esid */
7d24f0b8	129	cmpldi r10,16
7aa0727f	130	/* below SLICE_LOW_TOP */
7d24f0b8	131	blt 5f
7aa0727f AK	132	/*
	133	* Handle hpsizes,
	134	* r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
	135	*/
	136	srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
	137	addi r9,r11,PACAHIGHSLICEPSIZE
	138	lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
	139	/* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
	140	rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
	141	b 6f
7d24f0b8	142
7aa0727f AK	143	5:
	144	/*
	145	* Handle lpsizes
	146	* r9 is get_paca()->context.low_slices_psize, r11 is index
	147	*/
	148	ld r9,PACALOWSLICESPSIZE(r13)
	149	mr r11,r10
	150	6:
	151	sldi r11,r11,2 /* index * 4 */
	152	/* Extract the psize and multiply to get an array offset */
d0f13e3c BH	153	srd r9,r9,r11
	154	andi. r9,r9,0xf
	155	mulli r9,r9,MMUPSIZEDEFSIZE
c594adad	156
d0f13e3c BH	157	/* Now get to the array and obtain the sllp
	158	*/
	159	ld r11,PACATOC(r13)
	160	ld r11,mmu_psize_defs@got(r11)
	161	add r11,r11,r9
	162	ld r11,MMUPSIZESLLP(r11)
	163	ori r11,r11,SLB_VSID_USER
	164	#else
	165	/* paca context sllp already contains the SLB_VSID_USER bits */
bf72aeba	166	lhz r11,PACACONTEXTSLLP(r13)
d0f13e3c BH	167	#endif /* CONFIG_PPC_MM_SLICES */
d0f13e3c BH	168
3c726f8d	169	ld r9,PACACONTEXTID(r13)
1189be65 PM	170	BEGIN_FTR_SECTION
1189be65 PM	171	cmpldi r10,0x1000
1189be65	172	bge slb_finish_load_1T
44ae3ab3	173	END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
3c726f8d BH	174	b slb_finish_load
	175
	176	8: /* invalid EA */
	177	li r10,0 /* BAD_VSID */
c60ac569	178	li r9,0 /* BAD_VSID */
3c726f8d BH	179	li r11,SLB_VSID_USER /* flags don't much matter */
	180	b slb_finish_load
	181
3c726f8d BH	182	/*
	183	* Finish loading of an SLB entry and return
	184	*
c60ac569	185	* r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
3c726f8d BH	186	*/
3c726f8d BH	187	slb_finish_load:
af81d787	188	rldimi r10,r9,ESID_BITS,0
1189be65	189	ASM_VSID_SCRAMBLE(r10,r9,256M)
ac8dc282 AK	190	/*
	191	* bits above VSID_BITS_256M need to be ignored from r10
	192	* also combine VSID and flags
	193	*/
	194	rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))
3c726f8d BH	195
	196	/* r3 = EA, r11 = VSID data */
	197	/*
	198	* Find a slot, round robin. Previously we tried to find a
	199	* free slot first but that took too long. Unfortunately we
	200	* dont have any LRU information to help us choose a slot.
	201	*/
3c726f8d	202
1189be65	203	7: ld r10,PACASTABRR(r13)
3c726f8d	204	addi r10,r10,1
584f8b71	205	/* This gets soft patched on boot. */
b86206e4 AB	206	.globl slb_compare_rr_to_size
b86206e4 AB	207	slb_compare_rr_to_size:
584f8b71	208	cmpldi r10,0
3c726f8d BH	209
	210	blt+ 4f
	211	li r10,SLB_NUM_BOLTED
	212
	213	4:
	214	std r10,PACASTABRR(r13)
	215
	216	3:
	217	rldimi r3,r10,0,36 /* r3= EA[0:35] \| entry */
	218	oris r10,r3,SLB_ESID_V@h /* r3 \|= SLB_ESID_V */
	219
	220	/* r3 = ESID data, r11 = VSID data */
1da177e4 LT	221
	222	/*
	223	* No need for an isync before or after this slbmte. The exception
	224	* we enter with and the rfid we exit with are context synchronizing.
	225	*/
	226	slbmte r11,r10
	227
3c726f8d BH	228	/* we're done for kernel addresses */
	229	crclr 4cr0+eq / set result to "success" */
	230	bgelr cr7
1da177e4 LT	231
	232	/* Update the slb cache */
	233	lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
	234	cmpldi r3,SLB_CACHE_ENTRIES
	235	bge 1f
	236
	237	/* still room in the slb cache */
735cafc3 AK	238	sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
	239	srdi r10,r10,28 /* get the 36 bits of the ESID */
	240	add r11,r11,r13 /* r11 = (u32 )paca + offset /
	241	stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
1da177e4 LT	242	addi r3,r3,1 /* offset++ */
	243	b 2f
	244	1: /* offset >= SLB_CACHE_ENTRIES */
	245	li r3,SLB_CACHE_ENTRIES+1
	246	2:
	247	sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
3c726f8d	248	crclr 4cr0+eq / set result to "success" */
1da177e4 LT	249	blr
1da177e4 LT	250
1189be65 PM	251	/*
1189be65 PM	252	* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
1189be65	253	*
c60ac569	254	* r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
1189be65 PM	255	*/
1189be65 PM	256	slb_finish_load_1T:
c60ac569	257	srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
af81d787	258	rldimi r10,r9,ESID_BITS_1T,0
1189be65	259	ASM_VSID_SCRAMBLE(r10,r9,1T)
ac8dc282 AK	260	/*
	261	* bits above VSID_BITS_1T need to be ignored from r10
	262	* also combine VSID and flags
	263	*/
	264	rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
1189be65 PM	265	li r10,MMU_SEGSIZE_1T
	266	rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
	267
	268	/* r3 = EA, r11 = VSID data */
	269	clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
	270	b 7b
	271