[deliverable/linux.git] / arch / powerpc / mm / tlb_hash64.c

/*
 * This file contains the routines for flushing entries from the
 * TLB and MMU hash table.
 *
 *  Derived from arch/ppc64/mm/init.c:
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
 *    Copyright (C) 1996 Paul Mackerras
 *
 *  Derived from "arch/i386/mm/init.c"
 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
 *
 *  Dave Engebretsen <engebret@us.ibm.com>
 *      Rework for PPC64 port.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/percpu.h>
#include <linux/hardirq.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#include <asm/tlb.h>
#include <asm/bug.h>

DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);

/*
 * A linux PTE was changed and the corresponding hash table entry
 * neesd to be flushed. This function will either perform the flush
 * immediately or will batch it up if the current CPU has an active
 * batch on it.
 */
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
		     pte_t *ptep, unsigned long pte, int huge)
{
	struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
	unsigned long vsid, vaddr;
	unsigned int psize;
	int ssize;
	real_pte_t rpte;
	int i;

	i = batch->index;

	/* Get page size (maybe move back to caller).
	 *
	 * NOTE: when using special 64K mappings in 4K environment like
	 * for SPEs, we obtain the page size from the slice, which thus
	 * must still exist (and thus the VMA not reused) at the time
	 * of this call
	 */
	if (huge) {
#ifdef CONFIG_HUGETLB_PAGE
		psize = get_slice_psize(mm, addr);
		/* Mask the address for the correct page size */
		addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
#else
		BUG();
		psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
#endif
	} else {
		psize = pte_pagesize_index(mm, addr, pte);
		/* Mask the address for the standard page size.  If we
		 * have a 64k page kernel, but the hardware does not
		 * support 64k pages, this might be different from the
		 * hardware page size encoded in the slice table. */
		addr &= PAGE_MASK;
	}


	/* Build full vaddr */
	if (!is_kernel_addr(addr)) {
		ssize = user_segment_size(addr);
		vsid = get_vsid(mm->context.id, addr, ssize);
		WARN_ON(vsid == 0);
	} else {
		vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
		ssize = mmu_kernel_ssize;
	}
	vaddr = hpt_va(addr, vsid, ssize);
	rpte = __real_pte(__pte(pte), ptep);

	/*
	 * Check if we have an active batch on this CPU. If not, just
	 * flush now and return. For now, we don global invalidates
	 * in that case, might be worth testing the mm cpu mask though
	 * and decide to use local invalidates instead...
	 */
	if (!batch->active) {
		flush_hash_page(vaddr, rpte, psize, ssize, 0);
		put_cpu_var(ppc64_tlb_batch);
		return;
	}

	/*
	 * This can happen when we are in the middle of a TLB batch and
	 * we encounter memory pressure (eg copy_page_range when it tries
	 * to allocate a new pte). If we have to reclaim memory and end
	 * up scanning and resetting referenced bits then our batch context
	 * will change mid stream.
	 *
	 * We also need to ensure only one page size is present in a given
	 * batch
	 */
	if (i != 0 && (mm != batch->mm || batch->psize != psize ||
		       batch->ssize != ssize)) {
		__flush_tlb_pending(batch);
		i = 0;
	}
	if (i == 0) {
		batch->mm = mm;
		batch->psize = psize;
		batch->ssize = ssize;
	}
	batch->pte[i] = rpte;
	batch->vaddr[i] = vaddr;
	batch->index = ++i;
	if (i >= PPC64_TLB_BATCH_NR)
		__flush_tlb_pending(batch);
	put_cpu_var(ppc64_tlb_batch);
}

/*
 * This function is called when terminating an mmu batch or when a batch
 * is full. It will perform the flush of all the entries currently stored
 * in a batch.
 *
 * Must be called from within some kind of spinlock/non-preempt region...
 */
void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
{
	const struct cpumask *tmp;
	int i, local = 0;

	i = batch->index;
	tmp = cpumask_of(smp_processor_id());
	if (cpumask_equal(mm_cpumask(batch->mm), tmp))
		local = 1;
	if (i == 1)
		flush_hash_page(batch->vaddr[0], batch->pte[0],
				batch->psize, batch->ssize, local);
	else
		flush_hash_range(i, local);
	batch->index = 0;
}

void tlb_flush(struct mmu_gather *tlb)
{
	struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);

	/* If there's a TLB batch pending, then we must flush it because the
	 * pages are going to be freed and we really don't want to have a CPU
	 * access a freed page because it has a stale TLB
	 */
	if (tlbbatch->index)
		__flush_tlb_pending(tlbbatch);

	/* Push out batch of freed page tables */
	pte_free_finish();
}

/**
 * __flush_hash_table_range - Flush all HPTEs for a given address range
 *                            from the hash table (and the TLB). But keeps
 *                            the linux PTEs intact.
 *
 * @mm		: mm_struct of the target address space (generally init_mm)
 * @start	: starting address
 * @end         : ending address (not included in the flush)
 *
 * This function is mostly to be used by some IO hotplug code in order
 * to remove all hash entries from a given address range used to map IO
 * space on a removed PCI-PCI bidge without tearing down the full mapping
 * since 64K pages may overlap with other bridges when using 64K pages
 * with 4K HW pages on IO space.
 *
 * Because of that usage pattern, it's only available with CONFIG_HOTPLUG
 * and is implemented for small size rather than speed.
 */
#ifdef CONFIG_HOTPLUG

void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
			      unsigned long end)
{
	unsigned long flags;

	start = _ALIGN_DOWN(start, PAGE_SIZE);
	end = _ALIGN_UP(end, PAGE_SIZE);

	BUG_ON(!mm->pgd);

	/* Note: Normally, we should only ever use a batch within a
	 * PTE locked section. This violates the rule, but will work
	 * since we don't actually modify the PTEs, we just flush the
	 * hash while leaving the PTEs intact (including their reference
	 * to being hashed). This is not the most performance oriented
	 * way to do things but is fine for our needs here.
	 */
	local_irq_save(flags);
	arch_enter_lazy_mmu_mode();
	for (; start < end; start += PAGE_SIZE) {
		pte_t *ptep = find_linux_pte(mm->pgd, start);
		unsigned long pte;

		if (ptep == NULL)
			continue;
		pte = pte_val(*ptep);
		if (!(pte & _PAGE_HASHPTE))
			continue;
		hpte_need_flush(mm, start, ptep, pte, 0);
	}
	arch_leave_lazy_mmu_mode();
	local_irq_restore(flags);
}

#endif /* CONFIG_HOTPLUG */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file contains the routines for flushing entries from the
	3	* TLB and MMU hash table.
	4	*
	5	* Derived from arch/ppc64/mm/init.c:
	6	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	7	*
	8	* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
	9	* and Cort Dougan (PReP) (cort@cs.nmt.edu)
	10	* Copyright (C) 1996 Paul Mackerras
1da177e4 LT	11	*
	12	* Derived from "arch/i386/mm/init.c"
	13	* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
	14	*
	15	* Dave Engebretsen <engebret@us.ibm.com>
	16	* Rework for PPC64 port.
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*/
3c726f8d	23
1da177e4 LT	24	#include <linux/kernel.h>
	25	#include <linux/mm.h>
	26	#include <linux/init.h>
	27	#include <linux/percpu.h>
	28	#include <linux/hardirq.h>
	29	#include <asm/pgalloc.h>
	30	#include <asm/tlbflush.h>
	31	#include <asm/tlb.h>
3c726f8d	32	#include <asm/bug.h>
1da177e4 LT	33
	34	DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
	35
1da177e4	36	/*
a741e679 BH	37	* A linux PTE was changed and the corresponding hash table entry
	38	* neesd to be flushed. This function will either perform the flush
	39	* immediately or will batch it up if the current CPU has an active
	40	* batch on it.
1da177e4	41	*/
a741e679 BH	42	void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
a741e679 BH	43	pte_t *ptep, unsigned long pte, int huge)
1da177e4	44	{
f342552b	45	struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch);
a741e679	46	unsigned long vsid, vaddr;
bf72aeba	47	unsigned int psize;
1189be65	48	int ssize;
a741e679	49	real_pte_t rpte;
61b1a942	50	int i;
1da177e4	51
1da177e4 LT	52	i = batch->index;
1da177e4 LT	53
16c2d476 BH	54	/* Get page size (maybe move back to caller).
	55	*
	56	* NOTE: when using special 64K mappings in 4K environment like
	57	* for SPEs, we obtain the page size from the slice, which thus
	58	* must still exist (and thus the VMA not reused) at the time
	59	* of this call
	60	*/
3c726f8d BH	61	if (huge) {
3c726f8d BH	62	#ifdef CONFIG_HUGETLB_PAGE
d258e64e	63	psize = get_slice_psize(mm, addr);
77058e1a DG	64	/* Mask the address for the correct page size */
77058e1a DG	65	addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
3c726f8d BH	66	#else
3c726f8d BH	67	BUG();
16c2d476	68	psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
3c726f8d	69	#endif
77058e1a	70	} else {
16c2d476	71	psize = pte_pagesize_index(mm, addr, pte);
77058e1a DG	72	/* Mask the address for the standard page size. If we
	73	* have a 64k page kernel, but the hardware does not
	74	* support 64k pages, this might be different from the
	75	* hardware page size encoded in the slice table. */
	76	addr &= PAGE_MASK;
	77	}
3c726f8d	78
f71dc176	79
a741e679 BH	80	/* Build full vaddr */
a741e679 BH	81	if (!is_kernel_addr(addr)) {
1189be65 PM	82	ssize = user_segment_size(addr);
1189be65 PM	83	vsid = get_vsid(mm->context.id, addr, ssize);
a741e679	84	WARN_ON(vsid == 0);
1189be65 PM	85	} else {
	86	vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
	87	ssize = mmu_kernel_ssize;
	88	}
	89	vaddr = hpt_va(addr, vsid, ssize);
a741e679 BH	90	rpte = __real_pte(__pte(pte), ptep);
	91
	92	/*
	93	* Check if we have an active batch on this CPU. If not, just
	94	* flush now and return. For now, we don global invalidates
	95	* in that case, might be worth testing the mm cpu mask though
	96	* and decide to use local invalidates instead...
	97	*/
	98	if (!batch->active) {
1189be65	99	flush_hash_page(vaddr, rpte, psize, ssize, 0);
f342552b	100	put_cpu_var(ppc64_tlb_batch);
a741e679 BH	101	return;
	102	}
	103
1da177e4 LT	104	/*
	105	* This can happen when we are in the middle of a TLB batch and
	106	* we encounter memory pressure (eg copy_page_range when it tries
	107	* to allocate a new pte). If we have to reclaim memory and end
	108	* up scanning and resetting referenced bits then our batch context
	109	* will change mid stream.
3c726f8d BH	110	*
	111	* We also need to ensure only one page size is present in a given
	112	* batch
1da177e4	113	*/
1189be65 PM	114	if (i != 0 && (mm != batch->mm \|\| batch->psize != psize \|\|
1189be65 PM	115	batch->ssize != ssize)) {
a741e679	116	__flush_tlb_pending(batch);
1da177e4 LT	117	i = 0;
1da177e4 LT	118	}
1da177e4	119	if (i == 0) {
1da177e4	120	batch->mm = mm;
3c726f8d	121	batch->psize = psize;
1189be65	122	batch->ssize = ssize;
1da177e4	123	}
a741e679 BH	124	batch->pte[i] = rpte;
a741e679 BH	125	batch->vaddr[i] = vaddr;
1da177e4 LT	126	batch->index = ++i;
1da177e4 LT	127	if (i >= PPC64_TLB_BATCH_NR)
a741e679	128	__flush_tlb_pending(batch);
f342552b	129	put_cpu_var(ppc64_tlb_batch);
1da177e4 LT	130	}
1da177e4 LT	131
a741e679 BH	132	/*
	133	* This function is called when terminating an mmu batch or when a batch
	134	* is full. It will perform the flush of all the entries currently stored
	135	* in a batch.
	136	*
	137	* Must be called from within some kind of spinlock/non-preempt region...
	138	*/
1da177e4 LT	139	void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
1da177e4 LT	140	{
56aa4129	141	const struct cpumask *tmp;
a741e679	142	int i, local = 0;
1da177e4	143
1da177e4	144	i = batch->index;
56aa4129 RR	145	tmp = cpumask_of(smp_processor_id());
56aa4129 RR	146	if (cpumask_equal(mm_cpumask(batch->mm), tmp))
1da177e4	147	local = 1;
1da177e4	148	if (i == 1)
3c726f8d	149	flush_hash_page(batch->vaddr[0], batch->pte[0],
1189be65	150	batch->psize, batch->ssize, local);
1da177e4	151	else
61b1a942	152	flush_hash_range(i, local);
1da177e4	153	batch->index = 0;
1da177e4 LT	154	}
1da177e4 LT	155
c7cc58a1 BH	156	void tlb_flush(struct mmu_gather *tlb)
	157	{
	158	struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
	159
	160	/* If there's a TLB batch pending, then we must flush it because the
	161	* pages are going to be freed and we really don't want to have a CPU
	162	* access a freed page because it has a stale TLB
	163	*/
	164	if (tlbbatch->index)
	165	__flush_tlb_pending(tlbbatch);
	166
	167	/* Push out batch of freed page tables */
	168	pte_free_finish();
	169	}
	170
3d5134ee BH	171	/**
	172	* __flush_hash_table_range - Flush all HPTEs for a given address range
	173	* from the hash table (and the TLB). But keeps
	174	* the linux PTEs intact.
	175	*
	176	* @mm : mm_struct of the target address space (generally init_mm)
	177	* @start : starting address
	178	* @end : ending address (not included in the flush)
	179	*
	180	* This function is mostly to be used by some IO hotplug code in order
	181	* to remove all hash entries from a given address range used to map IO
	182	* space on a removed PCI-PCI bidge without tearing down the full mapping
	183	* since 64K pages may overlap with other bridges when using 64K pages
	184	* with 4K HW pages on IO space.
	185	*
	186	* Because of that usage pattern, it's only available with CONFIG_HOTPLUG
	187	* and is implemented for small size rather than speed.
	188	*/
	189	#ifdef CONFIG_HOTPLUG
	190
	191	void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
	192	unsigned long end)
	193	{
	194	unsigned long flags;
	195
	196	start = _ALIGN_DOWN(start, PAGE_SIZE);
	197	end = _ALIGN_UP(end, PAGE_SIZE);
	198
	199	BUG_ON(!mm->pgd);
	200
	201	/* Note: Normally, we should only ever use a batch within a
	202	* PTE locked section. This violates the rule, but will work
	203	* since we don't actually modify the PTEs, we just flush the
	204	* hash while leaving the PTEs intact (including their reference
	205	* to being hashed). This is not the most performance oriented
	206	* way to do things but is fine for our needs here.
	207	*/
	208	local_irq_save(flags);
	209	arch_enter_lazy_mmu_mode();
	210	for (; start < end; start += PAGE_SIZE) {
	211	pte_t *ptep = find_linux_pte(mm->pgd, start);
	212	unsigned long pte;
	213
	214	if (ptep == NULL)
	215	continue;
	216	pte = pte_val(*ptep);
	217	if (!(pte & _PAGE_HASHPTE))
	218	continue;
	219	hpte_need_flush(mm, start, ptep, pte, 0);
	220	}
	221	arch_leave_lazy_mmu_mode();
	222	local_irq_restore(flags);
	223	}
	224
	225	#endif /* CONFIG_HOTPLUG */