Commit | Line | Data |
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f048aace BH |
1 | /* |
2 | * This file contains the routines for TLB flushing. | |
3 | * On machines where the MMU does not use a hash table to store virtual to | |
4 | * physical translations (ie, SW loaded TLBs or Book3E compilant processors, | |
5 | * this does -not- include 603 however which shares the implementation with | |
6 | * hash based processors) | |
7 | * | |
8 | * -- BenH | |
9 | * | |
25d21ad6 BH |
10 | * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org> |
11 | * IBM Corp. | |
f048aace BH |
12 | * |
13 | * Derived from arch/ppc/mm/init.c: | |
14 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
15 | * | |
16 | * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) | |
17 | * and Cort Dougan (PReP) (cort@cs.nmt.edu) | |
18 | * Copyright (C) 1996 Paul Mackerras | |
19 | * | |
20 | * Derived from "arch/i386/mm/init.c" | |
21 | * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds | |
22 | * | |
23 | * This program is free software; you can redistribute it and/or | |
24 | * modify it under the terms of the GNU General Public License | |
25 | * as published by the Free Software Foundation; either version | |
26 | * 2 of the License, or (at your option) any later version. | |
27 | * | |
28 | */ | |
29 | ||
30 | #include <linux/kernel.h> | |
93087948 | 31 | #include <linux/export.h> |
f048aace BH |
32 | #include <linux/mm.h> |
33 | #include <linux/init.h> | |
34 | #include <linux/highmem.h> | |
35 | #include <linux/pagemap.h> | |
36 | #include <linux/preempt.h> | |
37 | #include <linux/spinlock.h> | |
95f72d1e | 38 | #include <linux/memblock.h> |
91b191c7 | 39 | #include <linux/of_fdt.h> |
41151e77 | 40 | #include <linux/hugetlb.h> |
f048aace BH |
41 | |
42 | #include <asm/tlbflush.h> | |
43 | #include <asm/tlb.h> | |
25d21ad6 | 44 | #include <asm/code-patching.h> |
d9e1831a | 45 | #include <asm/cputhreads.h> |
41151e77 | 46 | #include <asm/hugetlb.h> |
28efc35f | 47 | #include <asm/paca.h> |
f048aace BH |
48 | |
49 | #include "mmu_decl.h" | |
50 | ||
41151e77 BB |
51 | /* |
52 | * This struct lists the sw-supported page sizes. The hardawre MMU may support | |
53 | * other sizes not listed here. The .ind field is only used on MMUs that have | |
54 | * indirect page table entries. | |
55 | */ | |
56 | #ifdef CONFIG_PPC_BOOK3E_MMU | |
881fde1d | 57 | #ifdef CONFIG_PPC_FSL_BOOK3E |
41151e77 BB |
58 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { |
59 | [MMU_PAGE_4K] = { | |
60 | .shift = 12, | |
61 | .enc = BOOK3E_PAGESZ_4K, | |
62 | }, | |
28efc35f SW |
63 | [MMU_PAGE_2M] = { |
64 | .shift = 21, | |
65 | .enc = BOOK3E_PAGESZ_2M, | |
66 | }, | |
41151e77 BB |
67 | [MMU_PAGE_4M] = { |
68 | .shift = 22, | |
69 | .enc = BOOK3E_PAGESZ_4M, | |
70 | }, | |
71 | [MMU_PAGE_16M] = { | |
72 | .shift = 24, | |
73 | .enc = BOOK3E_PAGESZ_16M, | |
74 | }, | |
75 | [MMU_PAGE_64M] = { | |
76 | .shift = 26, | |
77 | .enc = BOOK3E_PAGESZ_64M, | |
78 | }, | |
79 | [MMU_PAGE_256M] = { | |
80 | .shift = 28, | |
81 | .enc = BOOK3E_PAGESZ_256M, | |
82 | }, | |
83 | [MMU_PAGE_1G] = { | |
84 | .shift = 30, | |
85 | .enc = BOOK3E_PAGESZ_1GB, | |
86 | }, | |
87 | }; | |
88 | #else | |
25d21ad6 BH |
89 | struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = { |
90 | [MMU_PAGE_4K] = { | |
91 | .shift = 12, | |
f2b26c92 | 92 | .ind = 20, |
25d21ad6 BH |
93 | .enc = BOOK3E_PAGESZ_4K, |
94 | }, | |
95 | [MMU_PAGE_16K] = { | |
96 | .shift = 14, | |
97 | .enc = BOOK3E_PAGESZ_16K, | |
98 | }, | |
99 | [MMU_PAGE_64K] = { | |
100 | .shift = 16, | |
f2b26c92 | 101 | .ind = 28, |
25d21ad6 BH |
102 | .enc = BOOK3E_PAGESZ_64K, |
103 | }, | |
104 | [MMU_PAGE_1M] = { | |
105 | .shift = 20, | |
106 | .enc = BOOK3E_PAGESZ_1M, | |
107 | }, | |
108 | [MMU_PAGE_16M] = { | |
109 | .shift = 24, | |
f2b26c92 | 110 | .ind = 36, |
25d21ad6 BH |
111 | .enc = BOOK3E_PAGESZ_16M, |
112 | }, | |
113 | [MMU_PAGE_256M] = { | |
114 | .shift = 28, | |
115 | .enc = BOOK3E_PAGESZ_256M, | |
116 | }, | |
117 | [MMU_PAGE_1G] = { | |
118 | .shift = 30, | |
119 | .enc = BOOK3E_PAGESZ_1GB, | |
120 | }, | |
121 | }; | |
41151e77 BB |
122 | #endif /* CONFIG_FSL_BOOKE */ |
123 | ||
25d21ad6 BH |
124 | static inline int mmu_get_tsize(int psize) |
125 | { | |
126 | return mmu_psize_defs[psize].enc; | |
127 | } | |
128 | #else | |
129 | static inline int mmu_get_tsize(int psize) | |
130 | { | |
131 | /* This isn't used on !Book3E for now */ | |
132 | return 0; | |
133 | } | |
41151e77 | 134 | #endif /* CONFIG_PPC_BOOK3E_MMU */ |
25d21ad6 BH |
135 | |
136 | /* The variables below are currently only used on 64-bit Book3E | |
137 | * though this will probably be made common with other nohash | |
138 | * implementations at some point | |
139 | */ | |
140 | #ifdef CONFIG_PPC64 | |
141 | ||
142 | int mmu_linear_psize; /* Page size used for the linear mapping */ | |
143 | int mmu_pte_psize; /* Page size used for PTE pages */ | |
32a74949 | 144 | int mmu_vmemmap_psize; /* Page size used for the virtual mem map */ |
28efc35f | 145 | int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */ |
25d21ad6 BH |
146 | unsigned long linear_map_top; /* Top of linear mapping */ |
147 | ||
609af38f SW |
148 | |
149 | /* | |
150 | * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug | |
151 | * exceptions. This is used for bolted and e6500 TLB miss handlers which | |
152 | * do not modify this SPRG in the TLB miss code; for other TLB miss handlers, | |
153 | * this is set to zero. | |
154 | */ | |
155 | int extlb_level_exc; | |
156 | ||
25d21ad6 BH |
157 | #endif /* CONFIG_PPC64 */ |
158 | ||
3160b097 BB |
159 | #ifdef CONFIG_PPC_FSL_BOOK3E |
160 | /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */ | |
161 | DEFINE_PER_CPU(int, next_tlbcam_idx); | |
162 | EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx); | |
163 | #endif | |
164 | ||
f048aace BH |
165 | /* |
166 | * Base TLB flushing operations: | |
167 | * | |
168 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
169 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
170 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
171 | * - flush_tlb_kernel_range(start, end) flushes kernel pages | |
172 | * | |
173 | * - local_* variants of page and mm only apply to the current | |
174 | * processor | |
175 | */ | |
176 | ||
177 | /* | |
178 | * These are the base non-SMP variants of page and mm flushing | |
179 | */ | |
180 | void local_flush_tlb_mm(struct mm_struct *mm) | |
181 | { | |
182 | unsigned int pid; | |
183 | ||
184 | preempt_disable(); | |
185 | pid = mm->context.id; | |
186 | if (pid != MMU_NO_CONTEXT) | |
187 | _tlbil_pid(pid); | |
188 | preempt_enable(); | |
189 | } | |
190 | EXPORT_SYMBOL(local_flush_tlb_mm); | |
191 | ||
d4e167da BH |
192 | void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, |
193 | int tsize, int ind) | |
f048aace BH |
194 | { |
195 | unsigned int pid; | |
196 | ||
197 | preempt_disable(); | |
d4e167da | 198 | pid = mm ? mm->context.id : 0; |
f048aace | 199 | if (pid != MMU_NO_CONTEXT) |
d4e167da | 200 | _tlbil_va(vmaddr, pid, tsize, ind); |
f048aace BH |
201 | preempt_enable(); |
202 | } | |
f048aace | 203 | |
d4e167da BH |
204 | void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) |
205 | { | |
206 | __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, | |
25d21ad6 | 207 | mmu_get_tsize(mmu_virtual_psize), 0); |
d4e167da BH |
208 | } |
209 | EXPORT_SYMBOL(local_flush_tlb_page); | |
f048aace BH |
210 | |
211 | /* | |
212 | * And here are the SMP non-local implementations | |
213 | */ | |
214 | #ifdef CONFIG_SMP | |
215 | ||
3eb93c55 | 216 | static DEFINE_RAW_SPINLOCK(tlbivax_lock); |
f048aace BH |
217 | |
218 | struct tlb_flush_param { | |
219 | unsigned long addr; | |
220 | unsigned int pid; | |
d4e167da BH |
221 | unsigned int tsize; |
222 | unsigned int ind; | |
f048aace BH |
223 | }; |
224 | ||
225 | static void do_flush_tlb_mm_ipi(void *param) | |
226 | { | |
227 | struct tlb_flush_param *p = param; | |
228 | ||
229 | _tlbil_pid(p ? p->pid : 0); | |
230 | } | |
231 | ||
232 | static void do_flush_tlb_page_ipi(void *param) | |
233 | { | |
234 | struct tlb_flush_param *p = param; | |
235 | ||
d4e167da | 236 | _tlbil_va(p->addr, p->pid, p->tsize, p->ind); |
f048aace BH |
237 | } |
238 | ||
239 | ||
240 | /* Note on invalidations and PID: | |
241 | * | |
242 | * We snapshot the PID with preempt disabled. At this point, it can still | |
243 | * change either because: | |
244 | * - our context is being stolen (PID -> NO_CONTEXT) on another CPU | |
245 | * - we are invaliating some target that isn't currently running here | |
246 | * and is concurrently acquiring a new PID on another CPU | |
247 | * - some other CPU is re-acquiring a lost PID for this mm | |
248 | * etc... | |
249 | * | |
250 | * However, this shouldn't be a problem as we only guarantee | |
251 | * invalidation of TLB entries present prior to this call, so we | |
252 | * don't care about the PID changing, and invalidating a stale PID | |
253 | * is generally harmless. | |
254 | */ | |
255 | ||
256 | void flush_tlb_mm(struct mm_struct *mm) | |
257 | { | |
f048aace BH |
258 | unsigned int pid; |
259 | ||
260 | preempt_disable(); | |
261 | pid = mm->context.id; | |
262 | if (unlikely(pid == MMU_NO_CONTEXT)) | |
263 | goto no_context; | |
fcce8109 | 264 | if (!mm_is_core_local(mm)) { |
f048aace | 265 | struct tlb_flush_param p = { .pid = pid }; |
56aa4129 RR |
266 | /* Ignores smp_processor_id() even if set. */ |
267 | smp_call_function_many(mm_cpumask(mm), | |
268 | do_flush_tlb_mm_ipi, &p, 1); | |
f048aace BH |
269 | } |
270 | _tlbil_pid(pid); | |
271 | no_context: | |
272 | preempt_enable(); | |
273 | } | |
274 | EXPORT_SYMBOL(flush_tlb_mm); | |
275 | ||
d4e167da BH |
276 | void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, |
277 | int tsize, int ind) | |
f048aace | 278 | { |
56aa4129 | 279 | struct cpumask *cpu_mask; |
f048aace BH |
280 | unsigned int pid; |
281 | ||
c2c896be AS |
282 | /* |
283 | * This function as well as __local_flush_tlb_page() must only be called | |
284 | * for user contexts. | |
285 | */ | |
286 | if (unlikely(WARN_ON(!mm))) | |
0dc294f7 AS |
287 | return; |
288 | ||
f048aace | 289 | preempt_disable(); |
0dc294f7 | 290 | pid = mm->context.id; |
f048aace BH |
291 | if (unlikely(pid == MMU_NO_CONTEXT)) |
292 | goto bail; | |
d4e167da | 293 | cpu_mask = mm_cpumask(mm); |
fcce8109 | 294 | if (!mm_is_core_local(mm)) { |
f048aace BH |
295 | /* If broadcast tlbivax is supported, use it */ |
296 | if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) { | |
297 | int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL); | |
298 | if (lock) | |
3eb93c55 | 299 | raw_spin_lock(&tlbivax_lock); |
d4e167da | 300 | _tlbivax_bcast(vmaddr, pid, tsize, ind); |
f048aace | 301 | if (lock) |
3eb93c55 | 302 | raw_spin_unlock(&tlbivax_lock); |
f048aace BH |
303 | goto bail; |
304 | } else { | |
d4e167da BH |
305 | struct tlb_flush_param p = { |
306 | .pid = pid, | |
307 | .addr = vmaddr, | |
308 | .tsize = tsize, | |
309 | .ind = ind, | |
310 | }; | |
56aa4129 RR |
311 | /* Ignores smp_processor_id() even if set in cpu_mask */ |
312 | smp_call_function_many(cpu_mask, | |
f048aace BH |
313 | do_flush_tlb_page_ipi, &p, 1); |
314 | } | |
315 | } | |
d4e167da | 316 | _tlbil_va(vmaddr, pid, tsize, ind); |
f048aace BH |
317 | bail: |
318 | preempt_enable(); | |
319 | } | |
d4e167da BH |
320 | |
321 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |
322 | { | |
41151e77 | 323 | #ifdef CONFIG_HUGETLB_PAGE |
d742aa15 | 324 | if (vma && is_vm_hugetlb_page(vma)) |
41151e77 BB |
325 | flush_hugetlb_page(vma, vmaddr); |
326 | #endif | |
327 | ||
d4e167da | 328 | __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, |
25d21ad6 | 329 | mmu_get_tsize(mmu_virtual_psize), 0); |
d4e167da | 330 | } |
f048aace BH |
331 | EXPORT_SYMBOL(flush_tlb_page); |
332 | ||
333 | #endif /* CONFIG_SMP */ | |
334 | ||
91b191c7 DK |
335 | #ifdef CONFIG_PPC_47x |
336 | void __init early_init_mmu_47x(void) | |
337 | { | |
338 | #ifdef CONFIG_SMP | |
339 | unsigned long root = of_get_flat_dt_root(); | |
340 | if (of_get_flat_dt_prop(root, "cooperative-partition", NULL)) | |
341 | mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST); | |
342 | #endif /* CONFIG_SMP */ | |
343 | } | |
344 | #endif /* CONFIG_PPC_47x */ | |
345 | ||
f048aace BH |
346 | /* |
347 | * Flush kernel TLB entries in the given range | |
348 | */ | |
349 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
350 | { | |
351 | #ifdef CONFIG_SMP | |
352 | preempt_disable(); | |
353 | smp_call_function(do_flush_tlb_mm_ipi, NULL, 1); | |
354 | _tlbil_pid(0); | |
355 | preempt_enable(); | |
d6a09e0c | 356 | #else |
f048aace | 357 | _tlbil_pid(0); |
d6a09e0c | 358 | #endif |
f048aace BH |
359 | } |
360 | EXPORT_SYMBOL(flush_tlb_kernel_range); | |
361 | ||
362 | /* | |
363 | * Currently, for range flushing, we just do a full mm flush. This should | |
364 | * be optimized based on a threshold on the size of the range, since | |
365 | * some implementation can stack multiple tlbivax before a tlbsync but | |
366 | * for now, we keep it that way | |
367 | */ | |
368 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
369 | unsigned long end) | |
370 | ||
371 | { | |
372 | flush_tlb_mm(vma->vm_mm); | |
373 | } | |
374 | EXPORT_SYMBOL(flush_tlb_range); | |
c7cc58a1 BH |
375 | |
376 | void tlb_flush(struct mmu_gather *tlb) | |
377 | { | |
378 | flush_tlb_mm(tlb->mm); | |
c7cc58a1 | 379 | } |
25d21ad6 BH |
380 | |
381 | /* | |
382 | * Below are functions specific to the 64-bit variant of Book3E though that | |
383 | * may change in the future | |
384 | */ | |
385 | ||
386 | #ifdef CONFIG_PPC64 | |
387 | ||
388 | /* | |
389 | * Handling of virtual linear page tables or indirect TLB entries | |
390 | * flushing when PTE pages are freed | |
391 | */ | |
392 | void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address) | |
393 | { | |
394 | int tsize = mmu_psize_defs[mmu_pte_psize].enc; | |
395 | ||
28efc35f | 396 | if (book3e_htw_mode != PPC_HTW_NONE) { |
25d21ad6 BH |
397 | unsigned long start = address & PMD_MASK; |
398 | unsigned long end = address + PMD_SIZE; | |
399 | unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift; | |
400 | ||
401 | /* This isn't the most optimal, ideally we would factor out the | |
402 | * while preempt & CPU mask mucking around, or even the IPI but | |
403 | * it will do for now | |
404 | */ | |
405 | while (start < end) { | |
406 | __flush_tlb_page(tlb->mm, start, tsize, 1); | |
407 | start += size; | |
408 | } | |
409 | } else { | |
410 | unsigned long rmask = 0xf000000000000000ul; | |
411 | unsigned long rid = (address & rmask) | 0x1000000000000000ul; | |
412 | unsigned long vpte = address & ~rmask; | |
413 | ||
414 | #ifdef CONFIG_PPC_64K_PAGES | |
415 | vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful; | |
416 | #else | |
417 | vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful; | |
418 | #endif | |
419 | vpte |= rid; | |
420 | __flush_tlb_page(tlb->mm, vpte, tsize, 0); | |
421 | } | |
422 | } | |
423 | ||
f2b26c92 BH |
424 | static void setup_page_sizes(void) |
425 | { | |
988cf86d KG |
426 | unsigned int tlb0cfg; |
427 | unsigned int tlb0ps; | |
428 | unsigned int eptcfg; | |
f2b26c92 BH |
429 | int i, psize; |
430 | ||
988cf86d KG |
431 | #ifdef CONFIG_PPC_FSL_BOOK3E |
432 | unsigned int mmucfg = mfspr(SPRN_MMUCFG); | |
1b291873 | 433 | int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E); |
988cf86d | 434 | |
1b291873 | 435 | if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { |
988cf86d KG |
436 | unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG); |
437 | unsigned int min_pg, max_pg; | |
438 | ||
439 | min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; | |
440 | max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; | |
441 | ||
442 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { | |
443 | struct mmu_psize_def *def; | |
444 | unsigned int shift; | |
445 | ||
446 | def = &mmu_psize_defs[psize]; | |
447 | shift = def->shift; | |
448 | ||
28efc35f | 449 | if (shift == 0 || shift & 1) |
988cf86d KG |
450 | continue; |
451 | ||
452 | /* adjust to be in terms of 4^shift Kb */ | |
453 | shift = (shift - 10) >> 1; | |
454 | ||
455 | if ((shift >= min_pg) && (shift <= max_pg)) | |
456 | def->flags |= MMU_PAGE_SIZE_DIRECT; | |
457 | } | |
458 | ||
28efc35f | 459 | goto out; |
988cf86d | 460 | } |
1b291873 KG |
461 | |
462 | if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { | |
28efc35f SW |
463 | u32 tlb1cfg, tlb1ps; |
464 | ||
465 | tlb0cfg = mfspr(SPRN_TLB0CFG); | |
466 | tlb1cfg = mfspr(SPRN_TLB1CFG); | |
467 | tlb1ps = mfspr(SPRN_TLB1PS); | |
468 | eptcfg = mfspr(SPRN_EPTCFG); | |
469 | ||
470 | if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT)) | |
471 | book3e_htw_mode = PPC_HTW_E6500; | |
472 | ||
473 | /* | |
474 | * We expect 4K subpage size and unrestricted indirect size. | |
475 | * The lack of a restriction on indirect size is a Freescale | |
476 | * extension, indicated by PSn = 0 but SPSn != 0. | |
477 | */ | |
478 | if (eptcfg != 2) | |
479 | book3e_htw_mode = PPC_HTW_NONE; | |
1b291873 KG |
480 | |
481 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { | |
482 | struct mmu_psize_def *def = &mmu_psize_defs[psize]; | |
483 | ||
484 | if (tlb1ps & (1U << (def->shift - 10))) { | |
485 | def->flags |= MMU_PAGE_SIZE_DIRECT; | |
28efc35f SW |
486 | |
487 | if (book3e_htw_mode && psize == MMU_PAGE_2M) | |
488 | def->flags |= MMU_PAGE_SIZE_INDIRECT; | |
1b291873 KG |
489 | } |
490 | } | |
491 | ||
28efc35f | 492 | goto out; |
1b291873 | 493 | } |
988cf86d KG |
494 | #endif |
495 | ||
496 | tlb0cfg = mfspr(SPRN_TLB0CFG); | |
497 | tlb0ps = mfspr(SPRN_TLB0PS); | |
498 | eptcfg = mfspr(SPRN_EPTCFG); | |
499 | ||
f2b26c92 BH |
500 | /* Look for supported direct sizes */ |
501 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { | |
502 | struct mmu_psize_def *def = &mmu_psize_defs[psize]; | |
503 | ||
504 | if (tlb0ps & (1U << (def->shift - 10))) | |
505 | def->flags |= MMU_PAGE_SIZE_DIRECT; | |
506 | } | |
507 | ||
508 | /* Indirect page sizes supported ? */ | |
28efc35f SW |
509 | if ((tlb0cfg & TLBnCFG_IND) == 0 || |
510 | (tlb0cfg & TLBnCFG_PT) == 0) | |
511 | goto out; | |
512 | ||
513 | book3e_htw_mode = PPC_HTW_IBM; | |
f2b26c92 BH |
514 | |
515 | /* Now, we only deal with one IND page size for each | |
516 | * direct size. Hopefully all implementations today are | |
517 | * unambiguous, but we might want to be careful in the | |
518 | * future. | |
519 | */ | |
520 | for (i = 0; i < 3; i++) { | |
521 | unsigned int ps, sps; | |
522 | ||
523 | sps = eptcfg & 0x1f; | |
524 | eptcfg >>= 5; | |
525 | ps = eptcfg & 0x1f; | |
526 | eptcfg >>= 5; | |
527 | if (!ps || !sps) | |
528 | continue; | |
529 | for (psize = 0; psize < MMU_PAGE_COUNT; psize++) { | |
530 | struct mmu_psize_def *def = &mmu_psize_defs[psize]; | |
531 | ||
532 | if (ps == (def->shift - 10)) | |
533 | def->flags |= MMU_PAGE_SIZE_INDIRECT; | |
534 | if (sps == (def->shift - 10)) | |
535 | def->ind = ps + 10; | |
536 | } | |
537 | } | |
f2b26c92 | 538 | |
28efc35f | 539 | out: |
f2b26c92 BH |
540 | /* Cleanup array and print summary */ |
541 | pr_info("MMU: Supported page sizes\n"); | |
542 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { | |
543 | struct mmu_psize_def *def = &mmu_psize_defs[psize]; | |
544 | const char *__page_type_names[] = { | |
545 | "unsupported", | |
546 | "direct", | |
547 | "indirect", | |
548 | "direct & indirect" | |
549 | }; | |
550 | if (def->flags == 0) { | |
551 | def->shift = 0; | |
552 | continue; | |
553 | } | |
554 | pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10), | |
555 | __page_type_names[def->flags & 0x3]); | |
556 | } | |
557 | } | |
558 | ||
f67f4ef5 SW |
559 | static void setup_mmu_htw(void) |
560 | { | |
28efc35f SW |
561 | /* |
562 | * If we want to use HW tablewalk, enable it by patching the TLB miss | |
563 | * handlers to branch to the one dedicated to it. | |
564 | */ | |
565 | ||
566 | switch (book3e_htw_mode) { | |
567 | case PPC_HTW_IBM: | |
f67f4ef5 SW |
568 | patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e); |
569 | patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e); | |
28efc35f | 570 | break; |
9841c79c | 571 | #ifdef CONFIG_PPC_FSL_BOOK3E |
28efc35f | 572 | case PPC_HTW_E6500: |
609af38f | 573 | extlb_level_exc = EX_TLB_SIZE; |
28efc35f SW |
574 | patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e); |
575 | patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e); | |
576 | break; | |
9841c79c | 577 | #endif |
f2b26c92 | 578 | } |
32d206eb | 579 | pr_info("MMU: Book3E HW tablewalk %s\n", |
28efc35f | 580 | book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported"); |
f2b26c92 BH |
581 | } |
582 | ||
583 | /* | |
584 | * Early initialization of the MMU TLB code | |
585 | */ | |
5d61a217 | 586 | static void early_init_this_mmu(void) |
f2b26c92 | 587 | { |
25d21ad6 BH |
588 | unsigned int mas4; |
589 | ||
25d21ad6 BH |
590 | /* Set MAS4 based on page table setting */ |
591 | ||
592 | mas4 = 0x4 << MAS4_WIMGED_SHIFT; | |
28efc35f SW |
593 | switch (book3e_htw_mode) { |
594 | case PPC_HTW_E6500: | |
595 | mas4 |= MAS4_INDD; | |
596 | mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT; | |
597 | mas4 |= MAS4_TLBSELD(1); | |
598 | mmu_pte_psize = MMU_PAGE_2M; | |
599 | break; | |
600 | ||
601 | case PPC_HTW_IBM: | |
602 | mas4 |= MAS4_INDD; | |
25d21ad6 BH |
603 | #ifdef CONFIG_PPC_64K_PAGES |
604 | mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT; | |
605 | mmu_pte_psize = MMU_PAGE_256M; | |
606 | #else | |
607 | mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT; | |
608 | mmu_pte_psize = MMU_PAGE_1M; | |
609 | #endif | |
28efc35f SW |
610 | break; |
611 | ||
612 | case PPC_HTW_NONE: | |
25d21ad6 BH |
613 | #ifdef CONFIG_PPC_64K_PAGES |
614 | mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT; | |
615 | #else | |
616 | mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT; | |
617 | #endif | |
618 | mmu_pte_psize = mmu_virtual_psize; | |
28efc35f | 619 | break; |
25d21ad6 BH |
620 | } |
621 | mtspr(SPRN_MAS4, mas4); | |
622 | ||
55fd766b KG |
623 | #ifdef CONFIG_PPC_FSL_BOOK3E |
624 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { | |
625 | unsigned int num_cams; | |
d9e1831a SW |
626 | int __maybe_unused cpu = smp_processor_id(); |
627 | bool map = true; | |
55fd766b KG |
628 | |
629 | /* use a quarter of the TLBCAM for bolted linear map */ | |
630 | num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4; | |
d9e1831a SW |
631 | |
632 | /* | |
633 | * Only do the mapping once per core, or else the | |
634 | * transient mapping would cause problems. | |
635 | */ | |
636 | #ifdef CONFIG_SMP | |
ebb9d30a | 637 | if (hweight32(get_tensr()) > 1) |
d9e1831a SW |
638 | map = false; |
639 | #endif | |
640 | ||
641 | if (map) | |
642 | linear_map_top = map_mem_in_cams(linear_map_top, | |
eba5de8d | 643 | num_cams, false); |
5d61a217 SW |
644 | } |
645 | #endif | |
55fd766b | 646 | |
5d61a217 SW |
647 | /* A sync won't hurt us after mucking around with |
648 | * the MMU configuration | |
649 | */ | |
650 | mb(); | |
651 | } | |
f67f4ef5 | 652 | |
5d61a217 SW |
653 | static void __init early_init_mmu_global(void) |
654 | { | |
655 | /* XXX This will have to be decided at runtime, but right | |
656 | * now our boot and TLB miss code hard wires it. Ideally | |
657 | * we should find out a suitable page size and patch the | |
658 | * TLB miss code (either that or use the PACA to store | |
659 | * the value we want) | |
660 | */ | |
661 | mmu_linear_psize = MMU_PAGE_1G; | |
662 | ||
663 | /* XXX This should be decided at runtime based on supported | |
664 | * page sizes in the TLB, but for now let's assume 16M is | |
665 | * always there and a good fit (which it probably is) | |
666 | * | |
667 | * Freescale booke only supports 4K pages in TLB0, so use that. | |
668 | */ | |
669 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
670 | mmu_vmemmap_psize = MMU_PAGE_4K; | |
671 | else | |
672 | mmu_vmemmap_psize = MMU_PAGE_16M; | |
673 | ||
674 | /* XXX This code only checks for TLB 0 capabilities and doesn't | |
675 | * check what page size combos are supported by the HW. It | |
676 | * also doesn't handle the case where a separate array holds | |
677 | * the IND entries from the array loaded by the PT. | |
678 | */ | |
679 | /* Look for supported page sizes */ | |
680 | setup_page_sizes(); | |
681 | ||
682 | /* Look for HW tablewalk support */ | |
683 | setup_mmu_htw(); | |
684 | ||
685 | #ifdef CONFIG_PPC_FSL_BOOK3E | |
686 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { | |
28efc35f | 687 | if (book3e_htw_mode == PPC_HTW_NONE) { |
609af38f | 688 | extlb_level_exc = EX_TLB_SIZE; |
28efc35f SW |
689 | patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e); |
690 | patch_exception(0x1e0, | |
691 | exc_instruction_tlb_miss_bolted_book3e); | |
692 | } | |
55fd766b KG |
693 | } |
694 | #endif | |
695 | ||
5d61a217 SW |
696 | /* Set the global containing the top of the linear mapping |
697 | * for use by the TLB miss code | |
25d21ad6 | 698 | */ |
5d61a217 SW |
699 | linear_map_top = memblock_end_of_DRAM(); |
700 | } | |
701 | ||
702 | static void __init early_mmu_set_memory_limit(void) | |
703 | { | |
704 | #ifdef CONFIG_PPC_FSL_BOOK3E | |
705 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { | |
706 | /* | |
707 | * Limit memory so we dont have linear faults. | |
708 | * Unlike memblock_set_current_limit, which limits | |
709 | * memory available during early boot, this permanently | |
710 | * reduces the memory available to Linux. We need to | |
711 | * do this because highmem is not supported on 64-bit. | |
712 | */ | |
713 | memblock_enforce_memory_limit(linear_map_top); | |
714 | } | |
715 | #endif | |
e63075a3 BH |
716 | |
717 | memblock_set_current_limit(linear_map_top); | |
25d21ad6 BH |
718 | } |
719 | ||
5d61a217 | 720 | /* boot cpu only */ |
25d21ad6 BH |
721 | void __init early_init_mmu(void) |
722 | { | |
5d61a217 SW |
723 | early_init_mmu_global(); |
724 | early_init_this_mmu(); | |
725 | early_mmu_set_memory_limit(); | |
25d21ad6 BH |
726 | } |
727 | ||
061d19f2 | 728 | void early_init_mmu_secondary(void) |
25d21ad6 | 729 | { |
5d61a217 | 730 | early_init_this_mmu(); |
25d21ad6 BH |
731 | } |
732 | ||
cd3db0c4 BH |
733 | void setup_initial_memory_limit(phys_addr_t first_memblock_base, |
734 | phys_addr_t first_memblock_size) | |
735 | { | |
1dc91c3e | 736 | /* On non-FSL Embedded 64-bit, we adjust the RMA size to match |
cd3db0c4 BH |
737 | * the bolted TLB entry. We know for now that only 1G |
738 | * entries are supported though that may eventually | |
1dc91c3e KG |
739 | * change. |
740 | * | |
eba5de8d SW |
741 | * on FSL Embedded 64-bit, usually all RAM is bolted, but with |
742 | * unusual memory sizes it's possible for some RAM to not be mapped | |
743 | * (such RAM is not used at all by Linux, since we don't support | |
744 | * highmem on 64-bit). We limit ppc64_rma_size to what would be | |
745 | * mappable if this memblock is the only one. Additional memblocks | |
746 | * can only increase, not decrease, the amount that ends up getting | |
747 | * mapped. We still limit max to 1G even if we'll eventually map | |
748 | * more. This is due to what the early init code is set up to do. | |
1dc91c3e KG |
749 | * |
750 | * We crop it to the size of the first MEMBLOCK to | |
cd3db0c4 BH |
751 | * avoid going over total available memory just in case... |
752 | */ | |
1dc91c3e KG |
753 | #ifdef CONFIG_PPC_FSL_BOOK3E |
754 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) { | |
755 | unsigned long linear_sz; | |
eba5de8d SW |
756 | unsigned int num_cams; |
757 | ||
758 | /* use a quarter of the TLBCAM for bolted linear map */ | |
759 | num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4; | |
760 | ||
761 | linear_sz = map_mem_in_cams(first_memblock_size, num_cams, | |
762 | true); | |
763 | ||
1dc91c3e KG |
764 | ppc64_rma_size = min_t(u64, linear_sz, 0x40000000); |
765 | } else | |
766 | #endif | |
767 | ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000); | |
cd3db0c4 BH |
768 | |
769 | /* Finally limit subsequent allocations */ | |
4a89261b | 770 | memblock_set_current_limit(first_memblock_base + ppc64_rma_size); |
cd3db0c4 | 771 | } |
91b191c7 DK |
772 | #else /* ! CONFIG_PPC64 */ |
773 | void __init early_init_mmu(void) | |
774 | { | |
775 | #ifdef CONFIG_PPC_47x | |
776 | early_init_mmu_47x(); | |
777 | #endif | |
778 | } | |
25d21ad6 | 779 | #endif /* CONFIG_PPC64 */ |