[deliverable/linux.git] / arch / powerpc / oprofile / op_model_power4.c

/*
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/firmware.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/rtas.h>
#include <asm/oprofile_impl.h>
#include <asm/reg.h>

#define dbg(args...)

static unsigned long reset_value[OP_MAX_COUNTER];

static int oprofile_running;

/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
static u32 mmcr0_val;
static u64 mmcr1_val;
static u64 mmcra_val;

static void power4_reg_setup(struct op_counter_config *ctr,
			     struct op_system_config *sys,
			     int num_ctrs)
{
	int i;

	/*
	 * The performance counter event settings are given in the mmcr0,
	 * mmcr1 and mmcra values passed from the user in the
	 * op_system_config structure (sys variable).
	 */
	mmcr0_val = sys->mmcr0;
	mmcr1_val = sys->mmcr1;
	mmcra_val = sys->mmcra;

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
		reset_value[i] = 0x80000000UL - ctr[i].count;

	/* setup user and kernel profiling */
	if (sys->enable_kernel)
		mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
	else
		mmcr0_val |= MMCR0_KERNEL_DISABLE;

	if (sys->enable_user)
		mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
	else
		mmcr0_val |= MMCR0_PROBLEM_DISABLE;
}

extern void ppc64_enable_pmcs(void);

/*
 * Older CPUs require the MMCRA sample bit to be always set, but newer 
 * CPUs only want it set for some groups. Eventually we will remove all
 * knowledge of this bit in the kernel, oprofile userspace should be
 * setting it when required.
 *
 * In order to keep current installations working we force the bit for
 * those older CPUs. Once everyone has updated their oprofile userspace we
 * can remove this hack.
 */
static inline int mmcra_must_set_sample(void)
{
	if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
	    __is_processor(PV_970) || __is_processor(PV_970FX) ||
	    __is_processor(PV_970MP))
		return 1;

	return 0;
}

static void power4_cpu_setup(void *unused)
{
	unsigned int mmcr0 = mmcr0_val;
	unsigned long mmcra = mmcra_val;

	ppc64_enable_pmcs();

	/* set the freeze bit */
	mmcr0 |= MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
	mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
	mtspr(SPRN_MMCR0, mmcr0);

	mtspr(SPRN_MMCR1, mmcr1_val);

	if (mmcra_must_set_sample())
		mmcra |= MMCRA_SAMPLE_ENABLE;
	mtspr(SPRN_MMCRA, mmcra);

	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCR0));
	dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCR1));
	dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCRA));
}

static void power4_start(struct op_counter_config *ctr)
{
	int i;
	unsigned int mmcr0;

	/* set the PMM bit (see comment below) */
	mtmsrd(mfmsr() | MSR_PMM);

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
		if (ctr[i].enabled) {
			ctr_write(i, reset_value[i]);
		} else {
			ctr_write(i, 0);
		}
	}

	mmcr0 = mfspr(SPRN_MMCR0);

	/*
	 * We must clear the PMAO bit on some (GQ) chips. Just do it
	 * all the time
	 */
	mmcr0 &= ~MMCR0_PMAO;

	/*
	 * now clear the freeze bit, counting will not start until we
	 * rfid from this excetion, because only at that point will
	 * the PMM bit be cleared
	 */
	mmcr0 &= ~MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	oprofile_running = 1;

	dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
}

static void power4_stop(void)
{
	unsigned int mmcr0;

	/* freeze counters */
	mmcr0 = mfspr(SPRN_MMCR0);
	mmcr0 |= MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	oprofile_running = 0;

	dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);

	mb();
}

/* Fake functions used by canonicalize_pc */
static void __attribute_used__ hypervisor_bucket(void)
{
}

static void __attribute_used__ rtas_bucket(void)
{
}

static void __attribute_used__ kernel_unknown_bucket(void)
{
}

/*
 * On GQ and newer the MMCRA stores the HV and PR bits at the time
 * the SIAR was sampled. We use that to work out if the SIAR was sampled in
 * the hypervisor, our exception vectors or RTAS.
 */
static unsigned long get_pc(struct pt_regs *regs)
{
	unsigned long pc = mfspr(SPRN_SIAR);
	unsigned long mmcra;

	/* Cant do much about it */
	if (!cur_cpu_spec->oprofile_mmcra_sihv)
		return pc;

	mmcra = mfspr(SPRN_MMCRA);

	/* Were we in the hypervisor? */
	if (firmware_has_feature(FW_FEATURE_LPAR) &&
	    (mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
		/* function descriptor madness */
		return *((unsigned long *)hypervisor_bucket);

	/* We were in userspace, nothing to do */
	if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
		return pc;

#ifdef CONFIG_PPC_RTAS
	/* Were we in RTAS? */
	if (pc >= rtas.base && pc < (rtas.base + rtas.size))
		/* function descriptor madness */
		return *((unsigned long *)rtas_bucket);
#endif

	/* Were we in our exception vectors or SLB real mode miss handler? */
	if (pc < 0x1000000UL)
		return (unsigned long)__va(pc);

	/* Not sure where we were */
	if (!is_kernel_addr(pc))
		/* function descriptor madness */
		return *((unsigned long *)kernel_unknown_bucket);

	return pc;
}

static int get_kernel(unsigned long pc, unsigned long mmcra)
{
	int is_kernel;

	if (!cur_cpu_spec->oprofile_mmcra_sihv) {
		is_kernel = is_kernel_addr(pc);
	} else {
		is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
	}

	return is_kernel;
}

static void power4_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;
	unsigned int mmcr0;
	unsigned long mmcra;

	mmcra = mfspr(SPRN_MMCRA);

	pc = get_pc(regs);
	is_kernel = get_kernel(pc, mmcra);

	/* set the PMM bit (see comment below) */
	mtmsrd(mfmsr() | MSR_PMM);

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
		val = ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_ext_sample(pc, regs, i, is_kernel);
				ctr_write(i, reset_value[i]);
			} else {
				ctr_write(i, 0);
			}
		}
	}

	mmcr0 = mfspr(SPRN_MMCR0);

	/* reset the perfmon trigger */
	mmcr0 |= MMCR0_PMXE;

	/*
	 * We must clear the PMAO bit on some (GQ) chips. Just do it
	 * all the time
	 */
	mmcr0 &= ~MMCR0_PMAO;

	/* Clear the appropriate bits in the MMCRA */
	mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
	mtspr(SPRN_MMCRA, mmcra);

	/*
	 * now clear the freeze bit, counting will not start until we
	 * rfid from this exception, because only at that point will
	 * the PMM bit be cleared
	 */
	mmcr0 &= ~MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);
}

struct op_powerpc_model op_model_power4 = {
	.reg_setup		= power4_reg_setup,
	.cpu_setup		= power4_cpu_setup,
	.start			= power4_start,
	.stop			= power4_stop,
	.handle_interrupt	= power4_handle_interrupt,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#include <linux/oprofile.h>
	11	#include <linux/init.h>
	12	#include <linux/smp.h>
57cfb814	13	#include <asm/firmware.h>
1da177e4 LT	14	#include <asm/ptrace.h>
	15	#include <asm/system.h>
	16	#include <asm/processor.h>
	17	#include <asm/cputable.h>
1da177e4	18	#include <asm/rtas.h>
dca85932	19	#include <asm/oprofile_impl.h>
cb09cff3	20	#include <asm/reg.h>
1da177e4 LT	21
	22	#define dbg(args...)
	23
1da177e4 LT	24	static unsigned long reset_value[OP_MAX_COUNTER];
1da177e4 LT	25
1da177e4	26	static int oprofile_running;
1da177e4 LT	27
	28	/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
	29	static u32 mmcr0_val;
	30	static u64 mmcr1_val;
15e812ad	31	static u64 mmcra_val;
1da177e4 LT	32
	33	static void power4_reg_setup(struct op_counter_config *ctr,
	34	struct op_system_config *sys,
	35	int num_ctrs)
	36	{
	37	int i;
	38
1da177e4 LT	39	/*
	40	* The performance counter event settings are given in the mmcr0,
	41	* mmcr1 and mmcra values passed from the user in the
	42	* op_system_config structure (sys variable).
	43	*/
	44	mmcr0_val = sys->mmcr0;
	45	mmcr1_val = sys->mmcr1;
	46	mmcra_val = sys->mmcra;
	47
a6908cd0	48	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
1da177e4 LT	49	reset_value[i] = 0x80000000UL - ctr[i].count;
	50
	51	/* setup user and kernel profiling */
	52	if (sys->enable_kernel)
	53	mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
	54	else
	55	mmcr0_val \|= MMCR0_KERNEL_DISABLE;
	56
	57	if (sys->enable_user)
	58	mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
	59	else
	60	mmcr0_val \|= MMCR0_PROBLEM_DISABLE;
	61	}
	62
	63	extern void ppc64_enable_pmcs(void);
	64
cb09cff3 AB	65	/*
	66	* Older CPUs require the MMCRA sample bit to be always set, but newer
	67	* CPUs only want it set for some groups. Eventually we will remove all
	68	* knowledge of this bit in the kernel, oprofile userspace should be
	69	* setting it when required.
	70	*
	71	* In order to keep current installations working we force the bit for
	72	* those older CPUs. Once everyone has updated their oprofile userspace we
	73	* can remove this hack.
	74	*/
	75	static inline int mmcra_must_set_sample(void)
	76	{
	77	if (__is_processor(PV_POWER4) \|\| __is_processor(PV_POWER4p) \|\|
	78	__is_processor(PV_970) \|\| __is_processor(PV_970FX) \|\|
	79	__is_processor(PV_970MP))
	80	return 1;
	81
	82	return 0;
	83	}
	84
1da177e4 LT	85	static void power4_cpu_setup(void *unused)
	86	{
	87	unsigned int mmcr0 = mmcr0_val;
	88	unsigned long mmcra = mmcra_val;
	89
	90	ppc64_enable_pmcs();
	91
	92	/* set the freeze bit */
	93	mmcr0 \|= MMCR0_FC;
	94	mtspr(SPRN_MMCR0, mmcr0);
	95
	96	mmcr0 \|= MMCR0_FCM1\|MMCR0_PMXE\|MMCR0_FCECE;
	97	mmcr0 \|= MMCR0_PMC1CE\|MMCR0_PMCjCE;
	98	mtspr(SPRN_MMCR0, mmcr0);
	99
	100	mtspr(SPRN_MMCR1, mmcr1_val);
	101
cb09cff3 AB	102	if (mmcra_must_set_sample())
cb09cff3 AB	103	mmcra \|= MMCRA_SAMPLE_ENABLE;
1da177e4 LT	104	mtspr(SPRN_MMCRA, mmcra);
	105
	106	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
	107	mfspr(SPRN_MMCR0));
	108	dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
	109	mfspr(SPRN_MMCR1));
	110	dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
	111	mfspr(SPRN_MMCRA));
	112	}
	113
	114	static void power4_start(struct op_counter_config *ctr)
	115	{
	116	int i;
	117	unsigned int mmcr0;
	118
	119	/* set the PMM bit (see comment below) */
	120	mtmsrd(mfmsr() \| MSR_PMM);
	121
a6908cd0	122	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
1da177e4 LT	123	if (ctr[i].enabled) {
	124	ctr_write(i, reset_value[i]);
	125	} else {
	126	ctr_write(i, 0);
	127	}
	128	}
	129
	130	mmcr0 = mfspr(SPRN_MMCR0);
	131
	132	/*
	133	* We must clear the PMAO bit on some (GQ) chips. Just do it
	134	* all the time
	135	*/
	136	mmcr0 &= ~MMCR0_PMAO;
	137
	138	/*
	139	* now clear the freeze bit, counting will not start until we
	140	* rfid from this excetion, because only at that point will
	141	* the PMM bit be cleared
	142	*/
	143	mmcr0 &= ~MMCR0_FC;
	144	mtspr(SPRN_MMCR0, mmcr0);
	145
	146	oprofile_running = 1;
	147
	148	dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
	149	}
	150
	151	static void power4_stop(void)
	152	{
	153	unsigned int mmcr0;
	154
	155	/* freeze counters */
	156	mmcr0 = mfspr(SPRN_MMCR0);
	157	mmcr0 \|= MMCR0_FC;
	158	mtspr(SPRN_MMCR0, mmcr0);
	159
	160	oprofile_running = 0;
	161
	162	dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
	163
	164	mb();
	165	}
	166
	167	/* Fake functions used by canonicalize_pc */
	168	static void __attribute_used__ hypervisor_bucket(void)
	169	{
	170	}
	171
	172	static void __attribute_used__ rtas_bucket(void)
	173	{
	174	}
	175
	176	static void __attribute_used__ kernel_unknown_bucket(void)
	177	{
	178	}
	179
1da177e4 LT	180	/*
	181	* On GQ and newer the MMCRA stores the HV and PR bits at the time
	182	* the SIAR was sampled. We use that to work out if the SIAR was sampled in
	183	* the hypervisor, our exception vectors or RTAS.
	184	*/
	185	static unsigned long get_pc(struct pt_regs *regs)
	186	{
	187	unsigned long pc = mfspr(SPRN_SIAR);
	188	unsigned long mmcra;
	189
	190	/* Cant do much about it */
e78dbc80	191	if (!cur_cpu_spec->oprofile_mmcra_sihv)
15e812ad	192	return pc;
1da177e4 LT	193
	194	mmcra = mfspr(SPRN_MMCRA);
	195
	196	/* Were we in the hypervisor? */
e78dbc80 MN	197	if (firmware_has_feature(FW_FEATURE_LPAR) &&
e78dbc80 MN	198	(mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
1da177e4 LT	199	/* function descriptor madness */
	200	return ((unsigned long )hypervisor_bucket);
	201
	202	/* We were in userspace, nothing to do */
e78dbc80	203	if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
1da177e4 LT	204	return pc;
	205
	206	#ifdef CONFIG_PPC_RTAS
	207	/* Were we in RTAS? */
	208	if (pc >= rtas.base && pc < (rtas.base + rtas.size))
	209	/* function descriptor madness */
	210	return ((unsigned long )rtas_bucket);
	211	#endif
	212
	213	/* Were we in our exception vectors or SLB real mode miss handler? */
	214	if (pc < 0x1000000UL)
	215	return (unsigned long)__va(pc);
	216
	217	/* Not sure where we were */
51fae6de	218	if (!is_kernel_addr(pc))
1da177e4 LT	219	/* function descriptor madness */
	220	return ((unsigned long )kernel_unknown_bucket);
	221
15e812ad	222	return pc;
1da177e4 LT	223	}
1da177e4 LT	224
e78dbc80	225	static int get_kernel(unsigned long pc, unsigned long mmcra)
1da177e4 LT	226	{
	227	int is_kernel;
	228
e78dbc80	229	if (!cur_cpu_spec->oprofile_mmcra_sihv) {
51fae6de	230	is_kernel = is_kernel_addr(pc);
1da177e4	231	} else {
e78dbc80	232	is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
1da177e4 LT	233	}
	234
	235	return is_kernel;
	236	}
	237
	238	static void power4_handle_interrupt(struct pt_regs *regs,
	239	struct op_counter_config *ctr)
	240	{
	241	unsigned long pc;
	242	int is_kernel;
	243	int val;
	244	int i;
	245	unsigned int mmcr0;
e78dbc80 MN	246	unsigned long mmcra;
	247
	248	mmcra = mfspr(SPRN_MMCRA);
1da177e4 LT	249
1da177e4 LT	250	pc = get_pc(regs);
e78dbc80	251	is_kernel = get_kernel(pc, mmcra);
1da177e4 LT	252
	253	/* set the PMM bit (see comment below) */
	254	mtmsrd(mfmsr() \| MSR_PMM);
	255
a6908cd0	256	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
1da177e4 LT	257	val = ctr_read(i);
	258	if (val < 0) {
	259	if (oprofile_running && ctr[i].enabled) {
6c6bd754	260	oprofile_add_ext_sample(pc, regs, i, is_kernel);
1da177e4 LT	261	ctr_write(i, reset_value[i]);
	262	} else {
	263	ctr_write(i, 0);
	264	}
	265	}
	266	}
	267
	268	mmcr0 = mfspr(SPRN_MMCR0);
	269
	270	/* reset the perfmon trigger */
	271	mmcr0 \|= MMCR0_PMXE;
	272
	273	/*
	274	* We must clear the PMAO bit on some (GQ) chips. Just do it
	275	* all the time
	276	*/
	277	mmcr0 &= ~MMCR0_PMAO;
	278
e78dbc80 MN	279	/* Clear the appropriate bits in the MMCRA */
	280	mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
	281	mtspr(SPRN_MMCRA, mmcra);
	282
1da177e4 LT	283	/*
	284	* now clear the freeze bit, counting will not start until we
	285	* rfid from this exception, because only at that point will
	286	* the PMM bit be cleared
	287	*/
	288	mmcr0 &= ~MMCR0_FC;
	289	mtspr(SPRN_MMCR0, mmcr0);
	290	}
	291
a3e48c10	292	struct op_powerpc_model op_model_power4 = {
1da177e4 LT	293	.reg_setup = power4_reg_setup,
	294	.cpu_setup = power4_cpu_setup,
	295	.start = power4_start,
	296	.stop = power4_stop,
	297	.handle_interrupt = power4_handle_interrupt,
	298	};