[deliverable/linux.git] / arch / powerpc / oprofile / op_model_power4.c

/*
 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/oprofile.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/cputable.h>
#include <asm/rtas.h>
#include <asm/oprofile_impl.h>
#include <asm/reg.h>

#define dbg(args...)

static unsigned long reset_value[OP_MAX_COUNTER];

static int oprofile_running;
static int mmcra_has_sihv;

/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
static u32 mmcr0_val;
static u64 mmcr1_val;
static u32 mmcra_val;

/*
 * Since we do not have an NMI, backtracing through spinlocks is
 * only a best guess. In light of this, allow it to be disabled at
 * runtime.
 */
static int backtrace_spinlocks;

static void power4_reg_setup(struct op_counter_config *ctr,
			     struct op_system_config *sys,
			     int num_ctrs)
{
	int i;

	/*
	 * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
	 * However we disable it on all POWER4 until we verify it works
	 * (I was seeing some strange behaviour last time I tried).
	 *
	 * It has been verified to work on POWER5 so we enable it there.
	 */
	if (cpu_has_feature(CPU_FTR_MMCRA_SIHV))
		mmcra_has_sihv = 1;

	/*
	 * The performance counter event settings are given in the mmcr0,
	 * mmcr1 and mmcra values passed from the user in the
	 * op_system_config structure (sys variable).
	 */
	mmcr0_val = sys->mmcr0;
	mmcr1_val = sys->mmcr1;
	mmcra_val = sys->mmcra;

	backtrace_spinlocks = sys->backtrace_spinlocks;

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
		reset_value[i] = 0x80000000UL - ctr[i].count;

	/* setup user and kernel profiling */
	if (sys->enable_kernel)
		mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
	else
		mmcr0_val |= MMCR0_KERNEL_DISABLE;

	if (sys->enable_user)
		mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
	else
		mmcr0_val |= MMCR0_PROBLEM_DISABLE;
}

extern void ppc64_enable_pmcs(void);

/*
 * Older CPUs require the MMCRA sample bit to be always set, but newer 
 * CPUs only want it set for some groups. Eventually we will remove all
 * knowledge of this bit in the kernel, oprofile userspace should be
 * setting it when required.
 *
 * In order to keep current installations working we force the bit for
 * those older CPUs. Once everyone has updated their oprofile userspace we
 * can remove this hack.
 */
static inline int mmcra_must_set_sample(void)
{
	if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
	    __is_processor(PV_970) || __is_processor(PV_970FX) ||
	    __is_processor(PV_970MP))
		return 1;

	return 0;
}

static void power4_cpu_setup(void *unused)
{
	unsigned int mmcr0 = mmcr0_val;
	unsigned long mmcra = mmcra_val;

	ppc64_enable_pmcs();

	/* set the freeze bit */
	mmcr0 |= MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
	mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
	mtspr(SPRN_MMCR0, mmcr0);

	mtspr(SPRN_MMCR1, mmcr1_val);

	if (mmcra_must_set_sample())
		mmcra |= MMCRA_SAMPLE_ENABLE;
	mtspr(SPRN_MMCRA, mmcra);

	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCR0));
	dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCR1));
	dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
	    mfspr(SPRN_MMCRA));
}

static void power4_start(struct op_counter_config *ctr)
{
	int i;
	unsigned int mmcr0;

	/* set the PMM bit (see comment below) */
	mtmsrd(mfmsr() | MSR_PMM);

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
		if (ctr[i].enabled) {
			ctr_write(i, reset_value[i]);
		} else {
			ctr_write(i, 0);
		}
	}

	mmcr0 = mfspr(SPRN_MMCR0);

	/*
	 * We must clear the PMAO bit on some (GQ) chips. Just do it
	 * all the time
	 */
	mmcr0 &= ~MMCR0_PMAO;

	/*
	 * now clear the freeze bit, counting will not start until we
	 * rfid from this excetion, because only at that point will
	 * the PMM bit be cleared
	 */
	mmcr0 &= ~MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	oprofile_running = 1;

	dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
}

static void power4_stop(void)
{
	unsigned int mmcr0;

	/* freeze counters */
	mmcr0 = mfspr(SPRN_MMCR0);
	mmcr0 |= MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);

	oprofile_running = 0;

	dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);

	mb();
}

/* Fake functions used by canonicalize_pc */
static void __attribute_used__ hypervisor_bucket(void)
{
}

static void __attribute_used__ rtas_bucket(void)
{
}

static void __attribute_used__ kernel_unknown_bucket(void)
{
}

static unsigned long check_spinlock_pc(struct pt_regs *regs,
				       unsigned long profile_pc)
{
	unsigned long pc = instruction_pointer(regs);

	/*
	 * If both the SIAR (sampled instruction) and the perfmon exception
	 * occurred in a spinlock region then we account the sample to the
	 * calling function. This isnt 100% correct, we really need soft
	 * IRQ disable so we always get the perfmon exception at the
	 * point at which the SIAR is set.
	 */
	if (backtrace_spinlocks && in_lock_functions(pc) &&
			in_lock_functions(profile_pc))
		return regs->link;
	else
		return profile_pc;
}

/*
 * On GQ and newer the MMCRA stores the HV and PR bits at the time
 * the SIAR was sampled. We use that to work out if the SIAR was sampled in
 * the hypervisor, our exception vectors or RTAS.
 */
static unsigned long get_pc(struct pt_regs *regs)
{
	unsigned long pc = mfspr(SPRN_SIAR);
	unsigned long mmcra;

	/* Cant do much about it */
	if (!mmcra_has_sihv)
		return check_spinlock_pc(regs, pc);

	mmcra = mfspr(SPRN_MMCRA);

	/* Were we in the hypervisor? */
	if (platform_is_lpar() && (mmcra & MMCRA_SIHV))
		/* function descriptor madness */
		return *((unsigned long *)hypervisor_bucket);

	/* We were in userspace, nothing to do */
	if (mmcra & MMCRA_SIPR)
		return pc;

#ifdef CONFIG_PPC_RTAS
	/* Were we in RTAS? */
	if (pc >= rtas.base && pc < (rtas.base + rtas.size))
		/* function descriptor madness */
		return *((unsigned long *)rtas_bucket);
#endif

	/* Were we in our exception vectors or SLB real mode miss handler? */
	if (pc < 0x1000000UL)
		return (unsigned long)__va(pc);

	/* Not sure where we were */
	if (pc < KERNELBASE)
		/* function descriptor madness */
		return *((unsigned long *)kernel_unknown_bucket);

	return check_spinlock_pc(regs, pc);
}

static int get_kernel(unsigned long pc)
{
	int is_kernel;

	if (!mmcra_has_sihv) {
		is_kernel = (pc >= KERNELBASE);
	} else {
		unsigned long mmcra = mfspr(SPRN_MMCRA);
		is_kernel = ((mmcra & MMCRA_SIPR) == 0);
	}

	return is_kernel;
}

static void power4_handle_interrupt(struct pt_regs *regs,
				    struct op_counter_config *ctr)
{
	unsigned long pc;
	int is_kernel;
	int val;
	int i;
	unsigned int mmcr0;

	pc = get_pc(regs);
	is_kernel = get_kernel(pc);

	/* set the PMM bit (see comment below) */
	mtmsrd(mfmsr() | MSR_PMM);

	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
		val = ctr_read(i);
		if (val < 0) {
			if (oprofile_running && ctr[i].enabled) {
				oprofile_add_pc(pc, is_kernel, i);
				ctr_write(i, reset_value[i]);
			} else {
				ctr_write(i, 0);
			}
		}
	}

	mmcr0 = mfspr(SPRN_MMCR0);

	/* reset the perfmon trigger */
	mmcr0 |= MMCR0_PMXE;

	/*
	 * We must clear the PMAO bit on some (GQ) chips. Just do it
	 * all the time
	 */
	mmcr0 &= ~MMCR0_PMAO;

	/*
	 * now clear the freeze bit, counting will not start until we
	 * rfid from this exception, because only at that point will
	 * the PMM bit be cleared
	 */
	mmcr0 &= ~MMCR0_FC;
	mtspr(SPRN_MMCR0, mmcr0);
}

struct op_powerpc_model op_model_power4 = {
	.reg_setup		= power4_reg_setup,
	.cpu_setup		= power4_cpu_setup,
	.start			= power4_start,
	.stop			= power4_stop,
	.handle_interrupt	= power4_handle_interrupt,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*/
	9
	10	#include <linux/oprofile.h>
	11	#include <linux/init.h>
	12	#include <linux/smp.h>
	13	#include <asm/ptrace.h>
	14	#include <asm/system.h>
	15	#include <asm/processor.h>
	16	#include <asm/cputable.h>
1da177e4	17	#include <asm/rtas.h>
dca85932	18	#include <asm/oprofile_impl.h>
cb09cff3	19	#include <asm/reg.h>
1da177e4 LT	20
	21	#define dbg(args...)
	22
1da177e4 LT	23	static unsigned long reset_value[OP_MAX_COUNTER];
1da177e4 LT	24
1da177e4 LT	25	static int oprofile_running;
	26	static int mmcra_has_sihv;
	27
	28	/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
	29	static u32 mmcr0_val;
	30	static u64 mmcr1_val;
	31	static u32 mmcra_val;
	32
	33	/*
	34	* Since we do not have an NMI, backtracing through spinlocks is
	35	* only a best guess. In light of this, allow it to be disabled at
	36	* runtime.
	37	*/
	38	static int backtrace_spinlocks;
	39
	40	static void power4_reg_setup(struct op_counter_config *ctr,
	41	struct op_system_config *sys,
	42	int num_ctrs)
	43	{
	44	int i;
	45
1da177e4 LT	46	/*
	47	* SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above.
	48	* However we disable it on all POWER4 until we verify it works
	49	* (I was seeing some strange behaviour last time I tried).
	50	*
	51	* It has been verified to work on POWER5 so we enable it there.
	52	*/
	53	if (cpu_has_feature(CPU_FTR_MMCRA_SIHV))
	54	mmcra_has_sihv = 1;
	55
	56	/*
	57	* The performance counter event settings are given in the mmcr0,
	58	* mmcr1 and mmcra values passed from the user in the
	59	* op_system_config structure (sys variable).
	60	*/
	61	mmcr0_val = sys->mmcr0;
	62	mmcr1_val = sys->mmcr1;
	63	mmcra_val = sys->mmcra;
	64
	65	backtrace_spinlocks = sys->backtrace_spinlocks;
	66
a6908cd0	67	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
1da177e4 LT	68	reset_value[i] = 0x80000000UL - ctr[i].count;
	69
	70	/* setup user and kernel profiling */
	71	if (sys->enable_kernel)
	72	mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
	73	else
	74	mmcr0_val \|= MMCR0_KERNEL_DISABLE;
	75
	76	if (sys->enable_user)
	77	mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
	78	else
	79	mmcr0_val \|= MMCR0_PROBLEM_DISABLE;
	80	}
	81
	82	extern void ppc64_enable_pmcs(void);
	83
cb09cff3 AB	84	/*
	85	* Older CPUs require the MMCRA sample bit to be always set, but newer
	86	* CPUs only want it set for some groups. Eventually we will remove all
	87	* knowledge of this bit in the kernel, oprofile userspace should be
	88	* setting it when required.
	89	*
	90	* In order to keep current installations working we force the bit for
	91	* those older CPUs. Once everyone has updated their oprofile userspace we
	92	* can remove this hack.
	93	*/
	94	static inline int mmcra_must_set_sample(void)
	95	{
	96	if (__is_processor(PV_POWER4) \|\| __is_processor(PV_POWER4p) \|\|
	97	__is_processor(PV_970) \|\| __is_processor(PV_970FX) \|\|
	98	__is_processor(PV_970MP))
	99	return 1;
	100
	101	return 0;
	102	}
	103
1da177e4 LT	104	static void power4_cpu_setup(void *unused)
	105	{
	106	unsigned int mmcr0 = mmcr0_val;
	107	unsigned long mmcra = mmcra_val;
	108
	109	ppc64_enable_pmcs();
	110
	111	/* set the freeze bit */
	112	mmcr0 \|= MMCR0_FC;
	113	mtspr(SPRN_MMCR0, mmcr0);
	114
	115	mmcr0 \|= MMCR0_FCM1\|MMCR0_PMXE\|MMCR0_FCECE;
	116	mmcr0 \|= MMCR0_PMC1CE\|MMCR0_PMCjCE;
	117	mtspr(SPRN_MMCR0, mmcr0);
	118
	119	mtspr(SPRN_MMCR1, mmcr1_val);
	120
cb09cff3 AB	121	if (mmcra_must_set_sample())
cb09cff3 AB	122	mmcra \|= MMCRA_SAMPLE_ENABLE;
1da177e4 LT	123	mtspr(SPRN_MMCRA, mmcra);
	124
	125	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
	126	mfspr(SPRN_MMCR0));
	127	dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
	128	mfspr(SPRN_MMCR1));
	129	dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
	130	mfspr(SPRN_MMCRA));
	131	}
	132
	133	static void power4_start(struct op_counter_config *ctr)
	134	{
	135	int i;
	136	unsigned int mmcr0;
	137
	138	/* set the PMM bit (see comment below) */
	139	mtmsrd(mfmsr() \| MSR_PMM);
	140
a6908cd0	141	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
1da177e4 LT	142	if (ctr[i].enabled) {
	143	ctr_write(i, reset_value[i]);
	144	} else {
	145	ctr_write(i, 0);
	146	}
	147	}
	148
	149	mmcr0 = mfspr(SPRN_MMCR0);
	150
	151	/*
	152	* We must clear the PMAO bit on some (GQ) chips. Just do it
	153	* all the time
	154	*/
	155	mmcr0 &= ~MMCR0_PMAO;
	156
	157	/*
	158	* now clear the freeze bit, counting will not start until we
	159	* rfid from this excetion, because only at that point will
	160	* the PMM bit be cleared
	161	*/
	162	mmcr0 &= ~MMCR0_FC;
	163	mtspr(SPRN_MMCR0, mmcr0);
	164
	165	oprofile_running = 1;
	166
	167	dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
	168	}
	169
	170	static void power4_stop(void)
	171	{
	172	unsigned int mmcr0;
	173
	174	/* freeze counters */
	175	mmcr0 = mfspr(SPRN_MMCR0);
	176	mmcr0 \|= MMCR0_FC;
	177	mtspr(SPRN_MMCR0, mmcr0);
	178
	179	oprofile_running = 0;
	180
	181	dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
	182
	183	mb();
	184	}
	185
	186	/* Fake functions used by canonicalize_pc */
	187	static void __attribute_used__ hypervisor_bucket(void)
	188	{
	189	}
	190
	191	static void __attribute_used__ rtas_bucket(void)
	192	{
	193	}
	194
	195	static void __attribute_used__ kernel_unknown_bucket(void)
	196	{
	197	}
	198
	199	static unsigned long check_spinlock_pc(struct pt_regs *regs,
	200	unsigned long profile_pc)
	201	{
	202	unsigned long pc = instruction_pointer(regs);
	203
	204	/*
	205	* If both the SIAR (sampled instruction) and the perfmon exception
206	* occurred in a spinlock region then we account the sample to the
207	* calling function. This isnt 100% correct, we really need soft
208	* IRQ disable so we always get the perfmon exception at the
209	* point at which the SIAR is set.
210	*/
211	if (backtrace_spinlocks && in_lock_functions(pc) &&
212	in_lock_functions(profile_pc))
213	return regs->link;
214	else
215	return profile_pc;
216	}
217
218	/*
219	* On GQ and newer the MMCRA stores the HV and PR bits at the time
220	* the SIAR was sampled. We use that to work out if the SIAR was sampled in
221	* the hypervisor, our exception vectors or RTAS.
222	*/
223	static unsigned long get_pc(struct pt_regs *regs)
224	{
225	unsigned long pc = mfspr(SPRN_SIAR);
226	unsigned long mmcra;
227
228	/* Cant do much about it */
229	if (!mmcra_has_sihv)
230	return check_spinlock_pc(regs, pc);
231
232	mmcra = mfspr(SPRN_MMCRA);
233
234	/* Were we in the hypervisor? */
799d6046	235	if (platform_is_lpar() && (mmcra & MMCRA_SIHV))
1da177e4 LT	236	/* function descriptor madness */
	237	return ((unsigned long )hypervisor_bucket);
	238
	239	/* We were in userspace, nothing to do */
	240	if (mmcra & MMCRA_SIPR)
	241	return pc;
	242
	243	#ifdef CONFIG_PPC_RTAS
	244	/* Were we in RTAS? */
	245	if (pc >= rtas.base && pc < (rtas.base + rtas.size))
	246	/* function descriptor madness */
	247	return ((unsigned long )rtas_bucket);
	248	#endif
	249
	250	/* Were we in our exception vectors or SLB real mode miss handler? */
	251	if (pc < 0x1000000UL)
	252	return (unsigned long)__va(pc);
	253
	254	/* Not sure where we were */
	255	if (pc < KERNELBASE)
	256	/* function descriptor madness */
	257	return ((unsigned long )kernel_unknown_bucket);
	258
	259	return check_spinlock_pc(regs, pc);
	260	}
	261
	262	static int get_kernel(unsigned long pc)
	263	{
	264	int is_kernel;
	265
	266	if (!mmcra_has_sihv) {
	267	is_kernel = (pc >= KERNELBASE);
	268	} else {
	269	unsigned long mmcra = mfspr(SPRN_MMCRA);
	270	is_kernel = ((mmcra & MMCRA_SIPR) == 0);
	271	}
	272
	273	return is_kernel;
	274	}
	275
	276	static void power4_handle_interrupt(struct pt_regs *regs,
	277	struct op_counter_config *ctr)
	278	{
	279	unsigned long pc;
	280	int is_kernel;
	281	int val;
	282	int i;
	283	unsigned int mmcr0;
	284
	285	pc = get_pc(regs);
	286	is_kernel = get_kernel(pc);
	287
	288	/* set the PMM bit (see comment below) */
	289	mtmsrd(mfmsr() \| MSR_PMM);
	290
a6908cd0	291	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
1da177e4 LT	292	val = ctr_read(i);
	293	if (val < 0) {
	294	if (oprofile_running && ctr[i].enabled) {
	295	oprofile_add_pc(pc, is_kernel, i);
	296	ctr_write(i, reset_value[i]);
	297	} else {
	298	ctr_write(i, 0);
	299	}
	300	}
	301	}
	302
	303	mmcr0 = mfspr(SPRN_MMCR0);
	304
	305	/* reset the perfmon trigger */
	306	mmcr0 \|= MMCR0_PMXE;
	307
	308	/*
	309	* We must clear the PMAO bit on some (GQ) chips. Just do it
	310	* all the time
	311	*/
	312	mmcr0 &= ~MMCR0_PMAO;
	313
	314	/*
	315	* now clear the freeze bit, counting will not start until we
	316	* rfid from this exception, because only at that point will
	317	* the PMM bit be cleared
	318	*/
	319	mmcr0 &= ~MMCR0_FC;
	320	mtspr(SPRN_MMCR0, mmcr0);
	321	}
	322
a3e48c10	323	struct op_powerpc_model op_model_power4 = {
1da177e4 LT	324	.reg_setup = power4_reg_setup,
	325	.cpu_setup = power4_cpu_setup,
	326	.start = power4_start,
	327	.stop = power4_stop,
	328	.handle_interrupt = power4_handle_interrupt,
	329	};