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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/oprofile.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/smp.h> | |
57cfb814 | 13 | #include <asm/firmware.h> |
1da177e4 LT |
14 | #include <asm/ptrace.h> |
15 | #include <asm/system.h> | |
16 | #include <asm/processor.h> | |
17 | #include <asm/cputable.h> | |
1da177e4 | 18 | #include <asm/rtas.h> |
dca85932 | 19 | #include <asm/oprofile_impl.h> |
cb09cff3 | 20 | #include <asm/reg.h> |
1da177e4 LT |
21 | |
22 | #define dbg(args...) | |
23 | ||
1da177e4 LT |
24 | static unsigned long reset_value[OP_MAX_COUNTER]; |
25 | ||
1da177e4 LT |
26 | static int oprofile_running; |
27 | static int mmcra_has_sihv; | |
28 | ||
29 | /* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */ | |
30 | static u32 mmcr0_val; | |
31 | static u64 mmcr1_val; | |
32 | static u32 mmcra_val; | |
33 | ||
34 | /* | |
35 | * Since we do not have an NMI, backtracing through spinlocks is | |
36 | * only a best guess. In light of this, allow it to be disabled at | |
37 | * runtime. | |
38 | */ | |
39 | static int backtrace_spinlocks; | |
40 | ||
41 | static void power4_reg_setup(struct op_counter_config *ctr, | |
42 | struct op_system_config *sys, | |
43 | int num_ctrs) | |
44 | { | |
45 | int i; | |
46 | ||
1da177e4 LT |
47 | /* |
48 | * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above. | |
49 | * However we disable it on all POWER4 until we verify it works | |
50 | * (I was seeing some strange behaviour last time I tried). | |
51 | * | |
52 | * It has been verified to work on POWER5 so we enable it there. | |
53 | */ | |
54 | if (cpu_has_feature(CPU_FTR_MMCRA_SIHV)) | |
55 | mmcra_has_sihv = 1; | |
56 | ||
57 | /* | |
58 | * The performance counter event settings are given in the mmcr0, | |
59 | * mmcr1 and mmcra values passed from the user in the | |
60 | * op_system_config structure (sys variable). | |
61 | */ | |
62 | mmcr0_val = sys->mmcr0; | |
63 | mmcr1_val = sys->mmcr1; | |
64 | mmcra_val = sys->mmcra; | |
65 | ||
66 | backtrace_spinlocks = sys->backtrace_spinlocks; | |
67 | ||
a6908cd0 | 68 | for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) |
1da177e4 LT |
69 | reset_value[i] = 0x80000000UL - ctr[i].count; |
70 | ||
71 | /* setup user and kernel profiling */ | |
72 | if (sys->enable_kernel) | |
73 | mmcr0_val &= ~MMCR0_KERNEL_DISABLE; | |
74 | else | |
75 | mmcr0_val |= MMCR0_KERNEL_DISABLE; | |
76 | ||
77 | if (sys->enable_user) | |
78 | mmcr0_val &= ~MMCR0_PROBLEM_DISABLE; | |
79 | else | |
80 | mmcr0_val |= MMCR0_PROBLEM_DISABLE; | |
81 | } | |
82 | ||
83 | extern void ppc64_enable_pmcs(void); | |
84 | ||
cb09cff3 AB |
85 | /* |
86 | * Older CPUs require the MMCRA sample bit to be always set, but newer | |
87 | * CPUs only want it set for some groups. Eventually we will remove all | |
88 | * knowledge of this bit in the kernel, oprofile userspace should be | |
89 | * setting it when required. | |
90 | * | |
91 | * In order to keep current installations working we force the bit for | |
92 | * those older CPUs. Once everyone has updated their oprofile userspace we | |
93 | * can remove this hack. | |
94 | */ | |
95 | static inline int mmcra_must_set_sample(void) | |
96 | { | |
97 | if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) || | |
98 | __is_processor(PV_970) || __is_processor(PV_970FX) || | |
99 | __is_processor(PV_970MP)) | |
100 | return 1; | |
101 | ||
102 | return 0; | |
103 | } | |
104 | ||
1da177e4 LT |
105 | static void power4_cpu_setup(void *unused) |
106 | { | |
107 | unsigned int mmcr0 = mmcr0_val; | |
108 | unsigned long mmcra = mmcra_val; | |
109 | ||
110 | ppc64_enable_pmcs(); | |
111 | ||
112 | /* set the freeze bit */ | |
113 | mmcr0 |= MMCR0_FC; | |
114 | mtspr(SPRN_MMCR0, mmcr0); | |
115 | ||
116 | mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE; | |
117 | mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE; | |
118 | mtspr(SPRN_MMCR0, mmcr0); | |
119 | ||
120 | mtspr(SPRN_MMCR1, mmcr1_val); | |
121 | ||
cb09cff3 AB |
122 | if (mmcra_must_set_sample()) |
123 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
1da177e4 LT |
124 | mtspr(SPRN_MMCRA, mmcra); |
125 | ||
126 | dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(), | |
127 | mfspr(SPRN_MMCR0)); | |
128 | dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(), | |
129 | mfspr(SPRN_MMCR1)); | |
130 | dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(), | |
131 | mfspr(SPRN_MMCRA)); | |
132 | } | |
133 | ||
134 | static void power4_start(struct op_counter_config *ctr) | |
135 | { | |
136 | int i; | |
137 | unsigned int mmcr0; | |
138 | ||
139 | /* set the PMM bit (see comment below) */ | |
140 | mtmsrd(mfmsr() | MSR_PMM); | |
141 | ||
a6908cd0 | 142 | for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { |
1da177e4 LT |
143 | if (ctr[i].enabled) { |
144 | ctr_write(i, reset_value[i]); | |
145 | } else { | |
146 | ctr_write(i, 0); | |
147 | } | |
148 | } | |
149 | ||
150 | mmcr0 = mfspr(SPRN_MMCR0); | |
151 | ||
152 | /* | |
153 | * We must clear the PMAO bit on some (GQ) chips. Just do it | |
154 | * all the time | |
155 | */ | |
156 | mmcr0 &= ~MMCR0_PMAO; | |
157 | ||
158 | /* | |
159 | * now clear the freeze bit, counting will not start until we | |
160 | * rfid from this excetion, because only at that point will | |
161 | * the PMM bit be cleared | |
162 | */ | |
163 | mmcr0 &= ~MMCR0_FC; | |
164 | mtspr(SPRN_MMCR0, mmcr0); | |
165 | ||
166 | oprofile_running = 1; | |
167 | ||
168 | dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); | |
169 | } | |
170 | ||
171 | static void power4_stop(void) | |
172 | { | |
173 | unsigned int mmcr0; | |
174 | ||
175 | /* freeze counters */ | |
176 | mmcr0 = mfspr(SPRN_MMCR0); | |
177 | mmcr0 |= MMCR0_FC; | |
178 | mtspr(SPRN_MMCR0, mmcr0); | |
179 | ||
180 | oprofile_running = 0; | |
181 | ||
182 | dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0); | |
183 | ||
184 | mb(); | |
185 | } | |
186 | ||
187 | /* Fake functions used by canonicalize_pc */ | |
188 | static void __attribute_used__ hypervisor_bucket(void) | |
189 | { | |
190 | } | |
191 | ||
192 | static void __attribute_used__ rtas_bucket(void) | |
193 | { | |
194 | } | |
195 | ||
196 | static void __attribute_used__ kernel_unknown_bucket(void) | |
197 | { | |
198 | } | |
199 | ||
200 | static unsigned long check_spinlock_pc(struct pt_regs *regs, | |
201 | unsigned long profile_pc) | |
202 | { | |
203 | unsigned long pc = instruction_pointer(regs); | |
204 | ||
205 | /* | |
206 | * If both the SIAR (sampled instruction) and the perfmon exception | |
207 | * occurred in a spinlock region then we account the sample to the | |
208 | * calling function. This isnt 100% correct, we really need soft | |
209 | * IRQ disable so we always get the perfmon exception at the | |
210 | * point at which the SIAR is set. | |
211 | */ | |
212 | if (backtrace_spinlocks && in_lock_functions(pc) && | |
213 | in_lock_functions(profile_pc)) | |
214 | return regs->link; | |
215 | else | |
216 | return profile_pc; | |
217 | } | |
218 | ||
219 | /* | |
220 | * On GQ and newer the MMCRA stores the HV and PR bits at the time | |
221 | * the SIAR was sampled. We use that to work out if the SIAR was sampled in | |
222 | * the hypervisor, our exception vectors or RTAS. | |
223 | */ | |
224 | static unsigned long get_pc(struct pt_regs *regs) | |
225 | { | |
226 | unsigned long pc = mfspr(SPRN_SIAR); | |
227 | unsigned long mmcra; | |
228 | ||
229 | /* Cant do much about it */ | |
230 | if (!mmcra_has_sihv) | |
231 | return check_spinlock_pc(regs, pc); | |
232 | ||
233 | mmcra = mfspr(SPRN_MMCRA); | |
234 | ||
235 | /* Were we in the hypervisor? */ | |
57cfb814 | 236 | if (firmware_has_feature(FW_FEATURE_LPAR) && (mmcra & MMCRA_SIHV)) |
1da177e4 LT |
237 | /* function descriptor madness */ |
238 | return *((unsigned long *)hypervisor_bucket); | |
239 | ||
240 | /* We were in userspace, nothing to do */ | |
241 | if (mmcra & MMCRA_SIPR) | |
242 | return pc; | |
243 | ||
244 | #ifdef CONFIG_PPC_RTAS | |
245 | /* Were we in RTAS? */ | |
246 | if (pc >= rtas.base && pc < (rtas.base + rtas.size)) | |
247 | /* function descriptor madness */ | |
248 | return *((unsigned long *)rtas_bucket); | |
249 | #endif | |
250 | ||
251 | /* Were we in our exception vectors or SLB real mode miss handler? */ | |
252 | if (pc < 0x1000000UL) | |
253 | return (unsigned long)__va(pc); | |
254 | ||
255 | /* Not sure where we were */ | |
51fae6de | 256 | if (!is_kernel_addr(pc)) |
1da177e4 LT |
257 | /* function descriptor madness */ |
258 | return *((unsigned long *)kernel_unknown_bucket); | |
259 | ||
260 | return check_spinlock_pc(regs, pc); | |
261 | } | |
262 | ||
263 | static int get_kernel(unsigned long pc) | |
264 | { | |
265 | int is_kernel; | |
266 | ||
267 | if (!mmcra_has_sihv) { | |
51fae6de | 268 | is_kernel = is_kernel_addr(pc); |
1da177e4 LT |
269 | } else { |
270 | unsigned long mmcra = mfspr(SPRN_MMCRA); | |
271 | is_kernel = ((mmcra & MMCRA_SIPR) == 0); | |
272 | } | |
273 | ||
274 | return is_kernel; | |
275 | } | |
276 | ||
277 | static void power4_handle_interrupt(struct pt_regs *regs, | |
278 | struct op_counter_config *ctr) | |
279 | { | |
280 | unsigned long pc; | |
281 | int is_kernel; | |
282 | int val; | |
283 | int i; | |
284 | unsigned int mmcr0; | |
285 | ||
286 | pc = get_pc(regs); | |
287 | is_kernel = get_kernel(pc); | |
288 | ||
289 | /* set the PMM bit (see comment below) */ | |
290 | mtmsrd(mfmsr() | MSR_PMM); | |
291 | ||
a6908cd0 | 292 | for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { |
1da177e4 LT |
293 | val = ctr_read(i); |
294 | if (val < 0) { | |
295 | if (oprofile_running && ctr[i].enabled) { | |
6c6bd754 | 296 | oprofile_add_ext_sample(pc, regs, i, is_kernel); |
1da177e4 LT |
297 | ctr_write(i, reset_value[i]); |
298 | } else { | |
299 | ctr_write(i, 0); | |
300 | } | |
301 | } | |
302 | } | |
303 | ||
304 | mmcr0 = mfspr(SPRN_MMCR0); | |
305 | ||
306 | /* reset the perfmon trigger */ | |
307 | mmcr0 |= MMCR0_PMXE; | |
308 | ||
309 | /* | |
310 | * We must clear the PMAO bit on some (GQ) chips. Just do it | |
311 | * all the time | |
312 | */ | |
313 | mmcr0 &= ~MMCR0_PMAO; | |
314 | ||
315 | /* | |
316 | * now clear the freeze bit, counting will not start until we | |
317 | * rfid from this exception, because only at that point will | |
318 | * the PMM bit be cleared | |
319 | */ | |
320 | mmcr0 &= ~MMCR0_FC; | |
321 | mtspr(SPRN_MMCR0, mmcr0); | |
322 | } | |
323 | ||
a3e48c10 | 324 | struct op_powerpc_model op_model_power4 = { |
1da177e4 LT |
325 | .reg_setup = power4_reg_setup, |
326 | .cpu_setup = power4_cpu_setup, | |
327 | .start = power4_start, | |
328 | .stop = power4_stop, | |
329 | .handle_interrupt = power4_handle_interrupt, | |
330 | }; |