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4574910e | 1 | /* |
cdd6c482 | 2 | * Performance event support - powerpc architecture code |
4574910e PM |
3 | * |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
cdd6c482 | 13 | #include <linux/perf_event.h> |
4574910e PM |
14 | #include <linux/percpu.h> |
15 | #include <linux/hardirq.h> | |
69123184 | 16 | #include <linux/uaccess.h> |
4574910e PM |
17 | #include <asm/reg.h> |
18 | #include <asm/pmc.h> | |
01d0287f | 19 | #include <asm/machdep.h> |
0475f9ea | 20 | #include <asm/firmware.h> |
0bbd0d4b | 21 | #include <asm/ptrace.h> |
69123184 | 22 | #include <asm/code-patching.h> |
4574910e | 23 | |
3925f46b AK |
24 | #define BHRB_MAX_ENTRIES 32 |
25 | #define BHRB_TARGET 0x0000000000000002 | |
26 | #define BHRB_PREDICTION 0x0000000000000001 | |
b0d436c7 | 27 | #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL |
3925f46b | 28 | |
cdd6c482 IM |
29 | struct cpu_hw_events { |
30 | int n_events; | |
4574910e PM |
31 | int n_percpu; |
32 | int disabled; | |
33 | int n_added; | |
ab7ef2e5 PM |
34 | int n_limited; |
35 | u8 pmcs_enabled; | |
cdd6c482 IM |
36 | struct perf_event *event[MAX_HWEVENTS]; |
37 | u64 events[MAX_HWEVENTS]; | |
38 | unsigned int flags[MAX_HWEVENTS]; | |
448d64f8 | 39 | unsigned long mmcr[3]; |
a8f90e90 PM |
40 | struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; |
41 | u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; | |
cdd6c482 IM |
42 | u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; |
43 | unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
44 | unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; | |
8e6d5573 LM |
45 | |
46 | unsigned int group_flag; | |
47 | int n_txn_start; | |
3925f46b AK |
48 | |
49 | /* BHRB bits */ | |
50 | u64 bhrb_filter; /* BHRB HW branch filter */ | |
51 | int bhrb_users; | |
52 | void *bhrb_context; | |
53 | struct perf_branch_stack bhrb_stack; | |
54 | struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; | |
4574910e | 55 | }; |
3925f46b | 56 | |
cdd6c482 | 57 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
4574910e PM |
58 | |
59 | struct power_pmu *ppmu; | |
60 | ||
d095cd46 | 61 | /* |
57c0c15b | 62 | * Normally, to ignore kernel events we set the FCS (freeze counters |
d095cd46 PM |
63 | * in supervisor mode) bit in MMCR0, but if the kernel runs with the |
64 | * hypervisor bit set in the MSR, or if we are running on a processor | |
65 | * where the hypervisor bit is forced to 1 (as on Apple G5 processors), | |
66 | * then we need to use the FCHV bit to ignore kernel events. | |
67 | */ | |
cdd6c482 | 68 | static unsigned int freeze_events_kernel = MMCR0_FCS; |
d095cd46 | 69 | |
98fb1807 PM |
70 | /* |
71 | * 32-bit doesn't have MMCRA but does have an MMCR2, | |
72 | * and a few other names are different. | |
73 | */ | |
74 | #ifdef CONFIG_PPC32 | |
75 | ||
76 | #define MMCR0_FCHV 0 | |
77 | #define MMCR0_PMCjCE MMCR0_PMCnCE | |
7a7a41f9 | 78 | #define MMCR0_FC56 0 |
378a6ee9 | 79 | #define MMCR0_PMAO 0 |
330a1eb7 | 80 | #define MMCR0_EBE 0 |
76cb8a78 | 81 | #define MMCR0_BHRBA 0 |
330a1eb7 ME |
82 | #define MMCR0_PMCC 0 |
83 | #define MMCR0_PMCC_U6 0 | |
98fb1807 PM |
84 | |
85 | #define SPRN_MMCRA SPRN_MMCR2 | |
86 | #define MMCRA_SAMPLE_ENABLE 0 | |
87 | ||
88 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
89 | { | |
90 | return 0; | |
91 | } | |
98fb1807 PM |
92 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } |
93 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) | |
94 | { | |
95 | return 0; | |
96 | } | |
75382aa7 AB |
97 | static inline void perf_read_regs(struct pt_regs *regs) |
98 | { | |
99 | regs->result = 0; | |
100 | } | |
98fb1807 PM |
101 | static inline int perf_intr_is_nmi(struct pt_regs *regs) |
102 | { | |
103 | return 0; | |
104 | } | |
105 | ||
e6878835 | 106 | static inline int siar_valid(struct pt_regs *regs) |
107 | { | |
108 | return 1; | |
109 | } | |
110 | ||
330a1eb7 ME |
111 | static bool is_ebb_event(struct perf_event *event) { return false; } |
112 | static int ebb_event_check(struct perf_event *event) { return 0; } | |
113 | static void ebb_event_add(struct perf_event *event) { } | |
114 | static void ebb_switch_out(unsigned long mmcr0) { } | |
115 | static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) | |
116 | { | |
117 | return mmcr0; | |
118 | } | |
119 | ||
d52f2dc4 MN |
120 | static inline void power_pmu_bhrb_enable(struct perf_event *event) {} |
121 | static inline void power_pmu_bhrb_disable(struct perf_event *event) {} | |
122 | void power_pmu_flush_branch_stack(void) {} | |
123 | static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} | |
c2e37a26 | 124 | static void pmao_restore_workaround(bool ebb) { } |
98fb1807 PM |
125 | #endif /* CONFIG_PPC32 */ |
126 | ||
33904054 ME |
127 | static bool regs_use_siar(struct pt_regs *regs) |
128 | { | |
cbda6aa1 | 129 | return !!regs->result; |
33904054 ME |
130 | } |
131 | ||
98fb1807 PM |
132 | /* |
133 | * Things that are specific to 64-bit implementations. | |
134 | */ | |
135 | #ifdef CONFIG_PPC64 | |
136 | ||
137 | static inline unsigned long perf_ip_adjust(struct pt_regs *regs) | |
138 | { | |
139 | unsigned long mmcra = regs->dsisr; | |
140 | ||
7a786832 | 141 | if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { |
98fb1807 PM |
142 | unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; |
143 | if (slot > 1) | |
144 | return 4 * (slot - 1); | |
145 | } | |
7a786832 | 146 | |
98fb1807 PM |
147 | return 0; |
148 | } | |
149 | ||
98fb1807 PM |
150 | /* |
151 | * The user wants a data address recorded. | |
152 | * If we're not doing instruction sampling, give them the SDAR | |
153 | * (sampled data address). If we are doing instruction sampling, then | |
154 | * only give them the SDAR if it corresponds to the instruction | |
58a032c3 ME |
155 | * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the |
156 | * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. | |
98fb1807 PM |
157 | */ |
158 | static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) | |
159 | { | |
160 | unsigned long mmcra = regs->dsisr; | |
58a032c3 | 161 | bool sdar_valid; |
e6878835 | 162 | |
58a032c3 ME |
163 | if (ppmu->flags & PPMU_HAS_SIER) |
164 | sdar_valid = regs->dar & SIER_SDAR_VALID; | |
165 | else { | |
166 | unsigned long sdsync; | |
167 | ||
168 | if (ppmu->flags & PPMU_SIAR_VALID) | |
169 | sdsync = POWER7P_MMCRA_SDAR_VALID; | |
170 | else if (ppmu->flags & PPMU_ALT_SIPR) | |
171 | sdsync = POWER6_MMCRA_SDSYNC; | |
172 | else | |
173 | sdsync = MMCRA_SDSYNC; | |
174 | ||
175 | sdar_valid = mmcra & sdsync; | |
176 | } | |
98fb1807 | 177 | |
58a032c3 | 178 | if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) |
98fb1807 PM |
179 | *addrp = mfspr(SPRN_SDAR); |
180 | } | |
181 | ||
5682c460 | 182 | static bool regs_sihv(struct pt_regs *regs) |
68b30bb9 AB |
183 | { |
184 | unsigned long sihv = MMCRA_SIHV; | |
185 | ||
8f61aa32 ME |
186 | if (ppmu->flags & PPMU_HAS_SIER) |
187 | return !!(regs->dar & SIER_SIHV); | |
188 | ||
68b30bb9 AB |
189 | if (ppmu->flags & PPMU_ALT_SIPR) |
190 | sihv = POWER6_MMCRA_SIHV; | |
191 | ||
5682c460 | 192 | return !!(regs->dsisr & sihv); |
68b30bb9 AB |
193 | } |
194 | ||
5682c460 | 195 | static bool regs_sipr(struct pt_regs *regs) |
68b30bb9 AB |
196 | { |
197 | unsigned long sipr = MMCRA_SIPR; | |
198 | ||
8f61aa32 ME |
199 | if (ppmu->flags & PPMU_HAS_SIER) |
200 | return !!(regs->dar & SIER_SIPR); | |
201 | ||
68b30bb9 AB |
202 | if (ppmu->flags & PPMU_ALT_SIPR) |
203 | sipr = POWER6_MMCRA_SIPR; | |
204 | ||
5682c460 | 205 | return !!(regs->dsisr & sipr); |
68b30bb9 AB |
206 | } |
207 | ||
1ce447b9 BH |
208 | static inline u32 perf_flags_from_msr(struct pt_regs *regs) |
209 | { | |
210 | if (regs->msr & MSR_PR) | |
211 | return PERF_RECORD_MISC_USER; | |
212 | if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) | |
213 | return PERF_RECORD_MISC_HYPERVISOR; | |
214 | return PERF_RECORD_MISC_KERNEL; | |
215 | } | |
216 | ||
98fb1807 PM |
217 | static inline u32 perf_get_misc_flags(struct pt_regs *regs) |
218 | { | |
33904054 | 219 | bool use_siar = regs_use_siar(regs); |
98fb1807 | 220 | |
75382aa7 | 221 | if (!use_siar) |
1ce447b9 BH |
222 | return perf_flags_from_msr(regs); |
223 | ||
224 | /* | |
225 | * If we don't have flags in MMCRA, rather than using | |
226 | * the MSR, we intuit the flags from the address in | |
227 | * SIAR which should give slightly more reliable | |
228 | * results | |
229 | */ | |
cbda6aa1 | 230 | if (ppmu->flags & PPMU_NO_SIPR) { |
1ce447b9 BH |
231 | unsigned long siar = mfspr(SPRN_SIAR); |
232 | if (siar >= PAGE_OFFSET) | |
233 | return PERF_RECORD_MISC_KERNEL; | |
234 | return PERF_RECORD_MISC_USER; | |
235 | } | |
98fb1807 | 236 | |
7abb840b | 237 | /* PR has priority over HV, so order below is important */ |
5682c460 | 238 | if (regs_sipr(regs)) |
7abb840b | 239 | return PERF_RECORD_MISC_USER; |
5682c460 ME |
240 | |
241 | if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) | |
cdd6c482 | 242 | return PERF_RECORD_MISC_HYPERVISOR; |
5682c460 | 243 | |
7abb840b | 244 | return PERF_RECORD_MISC_KERNEL; |
98fb1807 PM |
245 | } |
246 | ||
247 | /* | |
248 | * Overload regs->dsisr to store MMCRA so we only need to read it once | |
249 | * on each interrupt. | |
8f61aa32 | 250 | * Overload regs->dar to store SIER if we have it. |
75382aa7 AB |
251 | * Overload regs->result to specify whether we should use the MSR (result |
252 | * is zero) or the SIAR (result is non zero). | |
98fb1807 PM |
253 | */ |
254 | static inline void perf_read_regs(struct pt_regs *regs) | |
255 | { | |
75382aa7 AB |
256 | unsigned long mmcra = mfspr(SPRN_MMCRA); |
257 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
258 | int use_siar; | |
259 | ||
5682c460 | 260 | regs->dsisr = mmcra; |
8f61aa32 | 261 | |
cbda6aa1 ME |
262 | if (ppmu->flags & PPMU_HAS_SIER) |
263 | regs->dar = mfspr(SPRN_SIER); | |
8f61aa32 | 264 | |
5c093efa AB |
265 | /* |
266 | * If this isn't a PMU exception (eg a software event) the SIAR is | |
267 | * not valid. Use pt_regs. | |
268 | * | |
269 | * If it is a marked event use the SIAR. | |
270 | * | |
271 | * If the PMU doesn't update the SIAR for non marked events use | |
272 | * pt_regs. | |
273 | * | |
274 | * If the PMU has HV/PR flags then check to see if they | |
275 | * place the exception in userspace. If so, use pt_regs. In | |
276 | * continuous sampling mode the SIAR and the PMU exception are | |
277 | * not synchronised, so they may be many instructions apart. | |
278 | * This can result in confusing backtraces. We still want | |
279 | * hypervisor samples as well as samples in the kernel with | |
280 | * interrupts off hence the userspace check. | |
281 | */ | |
75382aa7 AB |
282 | if (TRAP(regs) != 0xf00) |
283 | use_siar = 0; | |
5c093efa AB |
284 | else if (marked) |
285 | use_siar = 1; | |
286 | else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) | |
287 | use_siar = 0; | |
cbda6aa1 | 288 | else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) |
75382aa7 AB |
289 | use_siar = 0; |
290 | else | |
291 | use_siar = 1; | |
292 | ||
cbda6aa1 | 293 | regs->result = use_siar; |
98fb1807 PM |
294 | } |
295 | ||
296 | /* | |
297 | * If interrupts were soft-disabled when a PMU interrupt occurs, treat | |
298 | * it as an NMI. | |
299 | */ | |
300 | static inline int perf_intr_is_nmi(struct pt_regs *regs) | |
301 | { | |
302 | return !regs->softe; | |
303 | } | |
304 | ||
e6878835 | 305 | /* |
306 | * On processors like P7+ that have the SIAR-Valid bit, marked instructions | |
307 | * must be sampled only if the SIAR-valid bit is set. | |
308 | * | |
309 | * For unmarked instructions and for processors that don't have the SIAR-Valid | |
310 | * bit, assume that SIAR is valid. | |
311 | */ | |
312 | static inline int siar_valid(struct pt_regs *regs) | |
313 | { | |
314 | unsigned long mmcra = regs->dsisr; | |
315 | int marked = mmcra & MMCRA_SAMPLE_ENABLE; | |
316 | ||
58a032c3 ME |
317 | if (marked) { |
318 | if (ppmu->flags & PPMU_HAS_SIER) | |
319 | return regs->dar & SIER_SIAR_VALID; | |
320 | ||
321 | if (ppmu->flags & PPMU_SIAR_VALID) | |
322 | return mmcra & POWER7P_MMCRA_SIAR_VALID; | |
323 | } | |
e6878835 | 324 | |
325 | return 1; | |
326 | } | |
327 | ||
d52f2dc4 MN |
328 | |
329 | /* Reset all possible BHRB entries */ | |
330 | static void power_pmu_bhrb_reset(void) | |
331 | { | |
332 | asm volatile(PPC_CLRBHRB); | |
333 | } | |
334 | ||
335 | static void power_pmu_bhrb_enable(struct perf_event *event) | |
336 | { | |
337 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
338 | ||
339 | if (!ppmu->bhrb_nr) | |
340 | return; | |
341 | ||
342 | /* Clear BHRB if we changed task context to avoid data leaks */ | |
343 | if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { | |
344 | power_pmu_bhrb_reset(); | |
345 | cpuhw->bhrb_context = event->ctx; | |
346 | } | |
347 | cpuhw->bhrb_users++; | |
348 | } | |
349 | ||
350 | static void power_pmu_bhrb_disable(struct perf_event *event) | |
351 | { | |
352 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
353 | ||
354 | if (!ppmu->bhrb_nr) | |
355 | return; | |
356 | ||
357 | cpuhw->bhrb_users--; | |
358 | WARN_ON_ONCE(cpuhw->bhrb_users < 0); | |
359 | ||
360 | if (!cpuhw->disabled && !cpuhw->bhrb_users) { | |
361 | /* BHRB cannot be turned off when other | |
362 | * events are active on the PMU. | |
363 | */ | |
364 | ||
365 | /* avoid stale pointer */ | |
366 | cpuhw->bhrb_context = NULL; | |
367 | } | |
368 | } | |
369 | ||
370 | /* Called from ctxsw to prevent one process's branch entries to | |
371 | * mingle with the other process's entries during context switch. | |
372 | */ | |
373 | void power_pmu_flush_branch_stack(void) | |
374 | { | |
375 | if (ppmu->bhrb_nr) | |
376 | power_pmu_bhrb_reset(); | |
377 | } | |
69123184 MN |
378 | /* Calculate the to address for a branch */ |
379 | static __u64 power_pmu_bhrb_to(u64 addr) | |
380 | { | |
381 | unsigned int instr; | |
382 | int ret; | |
383 | __u64 target; | |
384 | ||
385 | if (is_kernel_addr(addr)) | |
386 | return branch_target((unsigned int *)addr); | |
387 | ||
388 | /* Userspace: need copy instruction here then translate it */ | |
389 | pagefault_disable(); | |
390 | ret = __get_user_inatomic(instr, (unsigned int __user *)addr); | |
391 | if (ret) { | |
392 | pagefault_enable(); | |
393 | return 0; | |
394 | } | |
395 | pagefault_enable(); | |
396 | ||
397 | target = branch_target(&instr); | |
398 | if ((!target) || (instr & BRANCH_ABSOLUTE)) | |
399 | return target; | |
400 | ||
401 | /* Translate relative branch target from kernel to user address */ | |
402 | return target - (unsigned long)&instr + addr; | |
403 | } | |
d52f2dc4 | 404 | |
d52f2dc4 | 405 | /* Processing BHRB entries */ |
506e70d1 | 406 | void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) |
d52f2dc4 MN |
407 | { |
408 | u64 val; | |
409 | u64 addr; | |
506e70d1 | 410 | int r_index, u_index, pred; |
d52f2dc4 MN |
411 | |
412 | r_index = 0; | |
413 | u_index = 0; | |
414 | while (r_index < ppmu->bhrb_nr) { | |
415 | /* Assembly read function */ | |
506e70d1 MN |
416 | val = read_bhrb(r_index++); |
417 | if (!val) | |
418 | /* Terminal marker: End of valid BHRB entries */ | |
d52f2dc4 | 419 | break; |
506e70d1 | 420 | else { |
d52f2dc4 MN |
421 | addr = val & BHRB_EA; |
422 | pred = val & BHRB_PREDICTION; | |
d52f2dc4 | 423 | |
506e70d1 MN |
424 | if (!addr) |
425 | /* invalid entry */ | |
d52f2dc4 | 426 | continue; |
d52f2dc4 | 427 | |
506e70d1 MN |
428 | /* Branches are read most recent first (ie. mfbhrb 0 is |
429 | * the most recent branch). | |
430 | * There are two types of valid entries: | |
431 | * 1) a target entry which is the to address of a | |
432 | * computed goto like a blr,bctr,btar. The next | |
433 | * entry read from the bhrb will be branch | |
434 | * corresponding to this target (ie. the actual | |
435 | * blr/bctr/btar instruction). | |
436 | * 2) a from address which is an actual branch. If a | |
437 | * target entry proceeds this, then this is the | |
438 | * matching branch for that target. If this is not | |
439 | * following a target entry, then this is a branch | |
440 | * where the target is given as an immediate field | |
441 | * in the instruction (ie. an i or b form branch). | |
442 | * In this case we need to read the instruction from | |
443 | * memory to determine the target/to address. | |
444 | */ | |
d52f2dc4 | 445 | |
d52f2dc4 | 446 | if (val & BHRB_TARGET) { |
506e70d1 MN |
447 | /* Target branches use two entries |
448 | * (ie. computed gotos/XL form) | |
449 | */ | |
450 | cpuhw->bhrb_entries[u_index].to = addr; | |
451 | cpuhw->bhrb_entries[u_index].mispred = pred; | |
452 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 453 | |
506e70d1 MN |
454 | /* Get from address in next entry */ |
455 | val = read_bhrb(r_index++); | |
456 | addr = val & BHRB_EA; | |
457 | if (val & BHRB_TARGET) { | |
458 | /* Shouldn't have two targets in a | |
459 | row.. Reset index and try again */ | |
460 | r_index--; | |
461 | addr = 0; | |
462 | } | |
463 | cpuhw->bhrb_entries[u_index].from = addr; | |
d52f2dc4 | 464 | } else { |
506e70d1 MN |
465 | /* Branches to immediate field |
466 | (ie I or B form) */ | |
d52f2dc4 | 467 | cpuhw->bhrb_entries[u_index].from = addr; |
69123184 MN |
468 | cpuhw->bhrb_entries[u_index].to = |
469 | power_pmu_bhrb_to(addr); | |
d52f2dc4 MN |
470 | cpuhw->bhrb_entries[u_index].mispred = pred; |
471 | cpuhw->bhrb_entries[u_index].predicted = ~pred; | |
d52f2dc4 | 472 | } |
506e70d1 MN |
473 | u_index++; |
474 | ||
d52f2dc4 MN |
475 | } |
476 | } | |
477 | cpuhw->bhrb_stack.nr = u_index; | |
478 | return; | |
479 | } | |
480 | ||
330a1eb7 ME |
481 | static bool is_ebb_event(struct perf_event *event) |
482 | { | |
483 | /* | |
484 | * This could be a per-PMU callback, but we'd rather avoid the cost. We | |
485 | * check that the PMU supports EBB, meaning those that don't can still | |
486 | * use bit 63 of the event code for something else if they wish. | |
487 | */ | |
4d9690dd | 488 | return (ppmu->flags & PPMU_ARCH_207S) && |
8d7c55d0 | 489 | ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); |
330a1eb7 ME |
490 | } |
491 | ||
492 | static int ebb_event_check(struct perf_event *event) | |
493 | { | |
494 | struct perf_event *leader = event->group_leader; | |
495 | ||
496 | /* Event and group leader must agree on EBB */ | |
497 | if (is_ebb_event(leader) != is_ebb_event(event)) | |
498 | return -EINVAL; | |
499 | ||
500 | if (is_ebb_event(event)) { | |
501 | if (!(event->attach_state & PERF_ATTACH_TASK)) | |
502 | return -EINVAL; | |
503 | ||
504 | if (!leader->attr.pinned || !leader->attr.exclusive) | |
505 | return -EINVAL; | |
506 | ||
58b5fb00 ME |
507 | if (event->attr.freq || |
508 | event->attr.inherit || | |
509 | event->attr.sample_type || | |
510 | event->attr.sample_period || | |
511 | event->attr.enable_on_exec) | |
330a1eb7 ME |
512 | return -EINVAL; |
513 | } | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static void ebb_event_add(struct perf_event *event) | |
519 | { | |
520 | if (!is_ebb_event(event) || current->thread.used_ebb) | |
521 | return; | |
522 | ||
523 | /* | |
524 | * IFF this is the first time we've added an EBB event, set | |
525 | * PMXE in the user MMCR0 so we can detect when it's cleared by | |
526 | * userspace. We need this so that we can context switch while | |
527 | * userspace is in the EBB handler (where PMXE is 0). | |
528 | */ | |
529 | current->thread.used_ebb = 1; | |
530 | current->thread.mmcr0 |= MMCR0_PMXE; | |
531 | } | |
532 | ||
533 | static void ebb_switch_out(unsigned long mmcr0) | |
534 | { | |
535 | if (!(mmcr0 & MMCR0_EBE)) | |
536 | return; | |
537 | ||
538 | current->thread.siar = mfspr(SPRN_SIAR); | |
539 | current->thread.sier = mfspr(SPRN_SIER); | |
540 | current->thread.sdar = mfspr(SPRN_SDAR); | |
541 | current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; | |
542 | current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; | |
543 | } | |
544 | ||
545 | static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) | |
546 | { | |
547 | if (!ebb) | |
548 | goto out; | |
549 | ||
76cb8a78 ME |
550 | /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ |
551 | mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; | |
330a1eb7 | 552 | |
c2e37a26 ME |
553 | /* |
554 | * Add any bits from the user MMCR0, FC or PMAO. This is compatible | |
555 | * with pmao_restore_workaround() because we may add PMAO but we never | |
556 | * clear it here. | |
557 | */ | |
330a1eb7 ME |
558 | mmcr0 |= current->thread.mmcr0; |
559 | ||
c2e37a26 ME |
560 | /* |
561 | * Be careful not to set PMXE if userspace had it cleared. This is also | |
562 | * compatible with pmao_restore_workaround() because it has already | |
563 | * cleared PMXE and we leave PMAO alone. | |
564 | */ | |
330a1eb7 ME |
565 | if (!(current->thread.mmcr0 & MMCR0_PMXE)) |
566 | mmcr0 &= ~MMCR0_PMXE; | |
567 | ||
568 | mtspr(SPRN_SIAR, current->thread.siar); | |
569 | mtspr(SPRN_SIER, current->thread.sier); | |
570 | mtspr(SPRN_SDAR, current->thread.sdar); | |
571 | mtspr(SPRN_MMCR2, current->thread.mmcr2); | |
572 | out: | |
573 | return mmcr0; | |
574 | } | |
c2e37a26 ME |
575 | |
576 | static void pmao_restore_workaround(bool ebb) | |
577 | { | |
578 | unsigned pmcs[6]; | |
579 | ||
580 | if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) | |
581 | return; | |
582 | ||
583 | /* | |
584 | * On POWER8E there is a hardware defect which affects the PMU context | |
585 | * switch logic, ie. power_pmu_disable/enable(). | |
586 | * | |
587 | * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 | |
588 | * by the hardware. Sometime later the actual PMU exception is | |
589 | * delivered. | |
590 | * | |
591 | * If we context switch, or simply disable/enable, the PMU prior to the | |
592 | * exception arriving, the exception will be lost when we clear PMAO. | |
593 | * | |
594 | * When we reenable the PMU, we will write the saved MMCR0 with PMAO | |
595 | * set, and this _should_ generate an exception. However because of the | |
596 | * defect no exception is generated when we write PMAO, and we get | |
597 | * stuck with no counters counting but no exception delivered. | |
598 | * | |
599 | * The workaround is to detect this case and tweak the hardware to | |
600 | * create another pending PMU exception. | |
601 | * | |
602 | * We do that by setting up PMC6 (cycles) for an imminent overflow and | |
603 | * enabling the PMU. That causes a new exception to be generated in the | |
604 | * chip, but we don't take it yet because we have interrupts hard | |
605 | * disabled. We then write back the PMU state as we want it to be seen | |
606 | * by the exception handler. When we reenable interrupts the exception | |
607 | * handler will be called and see the correct state. | |
608 | * | |
609 | * The logic is the same for EBB, except that the exception is gated by | |
610 | * us having interrupts hard disabled as well as the fact that we are | |
611 | * not in userspace. The exception is finally delivered when we return | |
612 | * to userspace. | |
613 | */ | |
614 | ||
615 | /* Only if PMAO is set and PMAO_SYNC is clear */ | |
616 | if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) | |
617 | return; | |
618 | ||
619 | /* If we're doing EBB, only if BESCR[GE] is set */ | |
620 | if (ebb && !(current->thread.bescr & BESCR_GE)) | |
621 | return; | |
622 | ||
623 | /* | |
624 | * We are already soft-disabled in power_pmu_enable(). We need to hard | |
625 | * enable to actually prevent the PMU exception from firing. | |
626 | */ | |
627 | hard_irq_disable(); | |
628 | ||
629 | /* | |
630 | * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. | |
631 | * Using read/write_pmc() in a for loop adds 12 function calls and | |
632 | * almost doubles our code size. | |
633 | */ | |
634 | pmcs[0] = mfspr(SPRN_PMC1); | |
635 | pmcs[1] = mfspr(SPRN_PMC2); | |
636 | pmcs[2] = mfspr(SPRN_PMC3); | |
637 | pmcs[3] = mfspr(SPRN_PMC4); | |
638 | pmcs[4] = mfspr(SPRN_PMC5); | |
639 | pmcs[5] = mfspr(SPRN_PMC6); | |
640 | ||
641 | /* Ensure all freeze bits are unset */ | |
642 | mtspr(SPRN_MMCR2, 0); | |
643 | ||
644 | /* Set up PMC6 to overflow in one cycle */ | |
645 | mtspr(SPRN_PMC6, 0x7FFFFFFE); | |
646 | ||
647 | /* Enable exceptions and unfreeze PMC6 */ | |
648 | mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); | |
649 | ||
650 | /* Now we need to refreeze and restore the PMCs */ | |
651 | mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); | |
652 | ||
653 | mtspr(SPRN_PMC1, pmcs[0]); | |
654 | mtspr(SPRN_PMC2, pmcs[1]); | |
655 | mtspr(SPRN_PMC3, pmcs[2]); | |
656 | mtspr(SPRN_PMC4, pmcs[3]); | |
657 | mtspr(SPRN_PMC5, pmcs[4]); | |
658 | mtspr(SPRN_PMC6, pmcs[5]); | |
659 | } | |
98fb1807 PM |
660 | #endif /* CONFIG_PPC64 */ |
661 | ||
cdd6c482 | 662 | static void perf_event_interrupt(struct pt_regs *regs); |
7595d63b | 663 | |
4574910e | 664 | /* |
57c0c15b | 665 | * Read one performance monitor counter (PMC). |
4574910e PM |
666 | */ |
667 | static unsigned long read_pmc(int idx) | |
668 | { | |
669 | unsigned long val; | |
670 | ||
671 | switch (idx) { | |
672 | case 1: | |
673 | val = mfspr(SPRN_PMC1); | |
674 | break; | |
675 | case 2: | |
676 | val = mfspr(SPRN_PMC2); | |
677 | break; | |
678 | case 3: | |
679 | val = mfspr(SPRN_PMC3); | |
680 | break; | |
681 | case 4: | |
682 | val = mfspr(SPRN_PMC4); | |
683 | break; | |
684 | case 5: | |
685 | val = mfspr(SPRN_PMC5); | |
686 | break; | |
687 | case 6: | |
688 | val = mfspr(SPRN_PMC6); | |
689 | break; | |
98fb1807 | 690 | #ifdef CONFIG_PPC64 |
4574910e PM |
691 | case 7: |
692 | val = mfspr(SPRN_PMC7); | |
693 | break; | |
694 | case 8: | |
695 | val = mfspr(SPRN_PMC8); | |
696 | break; | |
98fb1807 | 697 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
698 | default: |
699 | printk(KERN_ERR "oops trying to read PMC%d\n", idx); | |
700 | val = 0; | |
701 | } | |
702 | return val; | |
703 | } | |
704 | ||
705 | /* | |
706 | * Write one PMC. | |
707 | */ | |
708 | static void write_pmc(int idx, unsigned long val) | |
709 | { | |
710 | switch (idx) { | |
711 | case 1: | |
712 | mtspr(SPRN_PMC1, val); | |
713 | break; | |
714 | case 2: | |
715 | mtspr(SPRN_PMC2, val); | |
716 | break; | |
717 | case 3: | |
718 | mtspr(SPRN_PMC3, val); | |
719 | break; | |
720 | case 4: | |
721 | mtspr(SPRN_PMC4, val); | |
722 | break; | |
723 | case 5: | |
724 | mtspr(SPRN_PMC5, val); | |
725 | break; | |
726 | case 6: | |
727 | mtspr(SPRN_PMC6, val); | |
728 | break; | |
98fb1807 | 729 | #ifdef CONFIG_PPC64 |
4574910e PM |
730 | case 7: |
731 | mtspr(SPRN_PMC7, val); | |
732 | break; | |
733 | case 8: | |
734 | mtspr(SPRN_PMC8, val); | |
735 | break; | |
98fb1807 | 736 | #endif /* CONFIG_PPC64 */ |
4574910e PM |
737 | default: |
738 | printk(KERN_ERR "oops trying to write PMC%d\n", idx); | |
739 | } | |
740 | } | |
741 | ||
5f6d0380 AK |
742 | /* Called from sysrq_handle_showregs() */ |
743 | void perf_event_print_debug(void) | |
744 | { | |
745 | unsigned long sdar, sier, flags; | |
746 | u32 pmcs[MAX_HWEVENTS]; | |
747 | int i; | |
748 | ||
749 | if (!ppmu->n_counter) | |
750 | return; | |
751 | ||
752 | local_irq_save(flags); | |
753 | ||
754 | pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", | |
755 | smp_processor_id(), ppmu->name, ppmu->n_counter); | |
756 | ||
757 | for (i = 0; i < ppmu->n_counter; i++) | |
758 | pmcs[i] = read_pmc(i + 1); | |
759 | ||
760 | for (; i < MAX_HWEVENTS; i++) | |
761 | pmcs[i] = 0xdeadbeef; | |
762 | ||
763 | pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", | |
764 | pmcs[0], pmcs[1], pmcs[2], pmcs[3]); | |
765 | ||
766 | if (ppmu->n_counter > 4) | |
767 | pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", | |
768 | pmcs[4], pmcs[5], pmcs[6], pmcs[7]); | |
769 | ||
770 | pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", | |
771 | mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); | |
772 | ||
773 | sdar = sier = 0; | |
774 | #ifdef CONFIG_PPC64 | |
775 | sdar = mfspr(SPRN_SDAR); | |
776 | ||
777 | if (ppmu->flags & PPMU_HAS_SIER) | |
778 | sier = mfspr(SPRN_SIER); | |
779 | ||
4d9690dd | 780 | if (ppmu->flags & PPMU_ARCH_207S) { |
5f6d0380 AK |
781 | pr_info("MMCR2: %016lx EBBHR: %016lx\n", |
782 | mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); | |
783 | pr_info("EBBRR: %016lx BESCR: %016lx\n", | |
784 | mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); | |
785 | } | |
786 | #endif | |
787 | pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", | |
788 | mfspr(SPRN_SIAR), sdar, sier); | |
789 | ||
790 | local_irq_restore(flags); | |
791 | } | |
792 | ||
4574910e PM |
793 | /* |
794 | * Check if a set of events can all go on the PMU at once. | |
795 | * If they can't, this will look at alternative codes for the events | |
796 | * and see if any combination of alternative codes is feasible. | |
cdd6c482 | 797 | * The feasible set is returned in event_id[]. |
4574910e | 798 | */ |
cdd6c482 IM |
799 | static int power_check_constraints(struct cpu_hw_events *cpuhw, |
800 | u64 event_id[], unsigned int cflags[], | |
ab7ef2e5 | 801 | int n_ev) |
4574910e | 802 | { |
448d64f8 | 803 | unsigned long mask, value, nv; |
cdd6c482 IM |
804 | unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; |
805 | int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; | |
4574910e | 806 | int i, j; |
448d64f8 PM |
807 | unsigned long addf = ppmu->add_fields; |
808 | unsigned long tadd = ppmu->test_adder; | |
4574910e | 809 | |
a8f90e90 | 810 | if (n_ev > ppmu->n_counter) |
4574910e PM |
811 | return -1; |
812 | ||
813 | /* First see if the events will go on as-is */ | |
814 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 815 | if ((cflags[i] & PPMU_LIMITED_PMC_REQD) |
cdd6c482 IM |
816 | && !ppmu->limited_pmc_event(event_id[i])) { |
817 | ppmu->get_alternatives(event_id[i], cflags[i], | |
e51ee31e | 818 | cpuhw->alternatives[i]); |
cdd6c482 | 819 | event_id[i] = cpuhw->alternatives[i][0]; |
ab7ef2e5 | 820 | } |
cdd6c482 | 821 | if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], |
e51ee31e | 822 | &cpuhw->avalues[i][0])) |
4574910e | 823 | return -1; |
4574910e PM |
824 | } |
825 | value = mask = 0; | |
826 | for (i = 0; i < n_ev; ++i) { | |
e51ee31e PM |
827 | nv = (value | cpuhw->avalues[i][0]) + |
828 | (value & cpuhw->avalues[i][0] & addf); | |
4574910e | 829 | if ((((nv + tadd) ^ value) & mask) != 0 || |
e51ee31e PM |
830 | (((nv + tadd) ^ cpuhw->avalues[i][0]) & |
831 | cpuhw->amasks[i][0]) != 0) | |
4574910e PM |
832 | break; |
833 | value = nv; | |
e51ee31e | 834 | mask |= cpuhw->amasks[i][0]; |
4574910e PM |
835 | } |
836 | if (i == n_ev) | |
837 | return 0; /* all OK */ | |
838 | ||
839 | /* doesn't work, gather alternatives... */ | |
840 | if (!ppmu->get_alternatives) | |
841 | return -1; | |
842 | for (i = 0; i < n_ev; ++i) { | |
ab7ef2e5 | 843 | choice[i] = 0; |
cdd6c482 | 844 | n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], |
e51ee31e | 845 | cpuhw->alternatives[i]); |
4574910e | 846 | for (j = 1; j < n_alt[i]; ++j) |
e51ee31e PM |
847 | ppmu->get_constraint(cpuhw->alternatives[i][j], |
848 | &cpuhw->amasks[i][j], | |
849 | &cpuhw->avalues[i][j]); | |
4574910e PM |
850 | } |
851 | ||
852 | /* enumerate all possibilities and see if any will work */ | |
853 | i = 0; | |
854 | j = -1; | |
855 | value = mask = nv = 0; | |
856 | while (i < n_ev) { | |
857 | if (j >= 0) { | |
858 | /* we're backtracking, restore context */ | |
859 | value = svalues[i]; | |
860 | mask = smasks[i]; | |
861 | j = choice[i]; | |
862 | } | |
863 | /* | |
cdd6c482 | 864 | * See if any alternative k for event_id i, |
4574910e PM |
865 | * where k > j, will satisfy the constraints. |
866 | */ | |
867 | while (++j < n_alt[i]) { | |
e51ee31e PM |
868 | nv = (value | cpuhw->avalues[i][j]) + |
869 | (value & cpuhw->avalues[i][j] & addf); | |
4574910e | 870 | if ((((nv + tadd) ^ value) & mask) == 0 && |
e51ee31e PM |
871 | (((nv + tadd) ^ cpuhw->avalues[i][j]) |
872 | & cpuhw->amasks[i][j]) == 0) | |
4574910e PM |
873 | break; |
874 | } | |
875 | if (j >= n_alt[i]) { | |
876 | /* | |
877 | * No feasible alternative, backtrack | |
cdd6c482 | 878 | * to event_id i-1 and continue enumerating its |
4574910e PM |
879 | * alternatives from where we got up to. |
880 | */ | |
881 | if (--i < 0) | |
882 | return -1; | |
883 | } else { | |
884 | /* | |
cdd6c482 IM |
885 | * Found a feasible alternative for event_id i, |
886 | * remember where we got up to with this event_id, | |
887 | * go on to the next event_id, and start with | |
4574910e PM |
888 | * the first alternative for it. |
889 | */ | |
890 | choice[i] = j; | |
891 | svalues[i] = value; | |
892 | smasks[i] = mask; | |
893 | value = nv; | |
e51ee31e | 894 | mask |= cpuhw->amasks[i][j]; |
4574910e PM |
895 | ++i; |
896 | j = -1; | |
897 | } | |
898 | } | |
899 | ||
900 | /* OK, we have a feasible combination, tell the caller the solution */ | |
901 | for (i = 0; i < n_ev; ++i) | |
cdd6c482 | 902 | event_id[i] = cpuhw->alternatives[i][choice[i]]; |
4574910e PM |
903 | return 0; |
904 | } | |
905 | ||
0475f9ea | 906 | /* |
cdd6c482 | 907 | * Check if newly-added events have consistent settings for |
0475f9ea | 908 | * exclude_{user,kernel,hv} with each other and any previously |
cdd6c482 | 909 | * added events. |
0475f9ea | 910 | */ |
cdd6c482 | 911 | static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], |
ab7ef2e5 | 912 | int n_prev, int n_new) |
0475f9ea | 913 | { |
ab7ef2e5 PM |
914 | int eu = 0, ek = 0, eh = 0; |
915 | int i, n, first; | |
cdd6c482 | 916 | struct perf_event *event; |
0475f9ea PM |
917 | |
918 | n = n_prev + n_new; | |
919 | if (n <= 1) | |
920 | return 0; | |
921 | ||
ab7ef2e5 PM |
922 | first = 1; |
923 | for (i = 0; i < n; ++i) { | |
924 | if (cflags[i] & PPMU_LIMITED_PMC_OK) { | |
925 | cflags[i] &= ~PPMU_LIMITED_PMC_REQD; | |
926 | continue; | |
927 | } | |
cdd6c482 | 928 | event = ctrs[i]; |
ab7ef2e5 | 929 | if (first) { |
cdd6c482 IM |
930 | eu = event->attr.exclude_user; |
931 | ek = event->attr.exclude_kernel; | |
932 | eh = event->attr.exclude_hv; | |
ab7ef2e5 | 933 | first = 0; |
cdd6c482 IM |
934 | } else if (event->attr.exclude_user != eu || |
935 | event->attr.exclude_kernel != ek || | |
936 | event->attr.exclude_hv != eh) { | |
0475f9ea | 937 | return -EAGAIN; |
ab7ef2e5 | 938 | } |
0475f9ea | 939 | } |
ab7ef2e5 PM |
940 | |
941 | if (eu || ek || eh) | |
942 | for (i = 0; i < n; ++i) | |
943 | if (cflags[i] & PPMU_LIMITED_PMC_OK) | |
944 | cflags[i] |= PPMU_LIMITED_PMC_REQD; | |
945 | ||
0475f9ea PM |
946 | return 0; |
947 | } | |
948 | ||
86c74ab3 EM |
949 | static u64 check_and_compute_delta(u64 prev, u64 val) |
950 | { | |
951 | u64 delta = (val - prev) & 0xfffffffful; | |
952 | ||
953 | /* | |
954 | * POWER7 can roll back counter values, if the new value is smaller | |
955 | * than the previous value it will cause the delta and the counter to | |
956 | * have bogus values unless we rolled a counter over. If a coutner is | |
957 | * rolled back, it will be smaller, but within 256, which is the maximum | |
958 | * number of events to rollback at once. If we dectect a rollback | |
959 | * return 0. This can lead to a small lack of precision in the | |
960 | * counters. | |
961 | */ | |
962 | if (prev > val && (prev - val) < 256) | |
963 | delta = 0; | |
964 | ||
965 | return delta; | |
966 | } | |
967 | ||
cdd6c482 | 968 | static void power_pmu_read(struct perf_event *event) |
4574910e | 969 | { |
98fb1807 | 970 | s64 val, delta, prev; |
4574910e | 971 | |
a4eaf7f1 PZ |
972 | if (event->hw.state & PERF_HES_STOPPED) |
973 | return; | |
974 | ||
cdd6c482 | 975 | if (!event->hw.idx) |
4574910e | 976 | return; |
330a1eb7 ME |
977 | |
978 | if (is_ebb_event(event)) { | |
979 | val = read_pmc(event->hw.idx); | |
980 | local64_set(&event->hw.prev_count, val); | |
981 | return; | |
982 | } | |
983 | ||
4574910e PM |
984 | /* |
985 | * Performance monitor interrupts come even when interrupts | |
986 | * are soft-disabled, as long as interrupts are hard-enabled. | |
987 | * Therefore we treat them like NMIs. | |
988 | */ | |
989 | do { | |
e7850595 | 990 | prev = local64_read(&event->hw.prev_count); |
4574910e | 991 | barrier(); |
cdd6c482 | 992 | val = read_pmc(event->hw.idx); |
86c74ab3 EM |
993 | delta = check_and_compute_delta(prev, val); |
994 | if (!delta) | |
995 | return; | |
e7850595 | 996 | } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); |
4574910e | 997 | |
e7850595 | 998 | local64_add(delta, &event->count); |
f5602941 AB |
999 | |
1000 | /* | |
1001 | * A number of places program the PMC with (0x80000000 - period_left). | |
1002 | * We never want period_left to be less than 1 because we will program | |
1003 | * the PMC with a value >= 0x800000000 and an edge detected PMC will | |
1004 | * roll around to 0 before taking an exception. We have seen this | |
1005 | * on POWER8. | |
1006 | * | |
1007 | * To fix this, clamp the minimum value of period_left to 1. | |
1008 | */ | |
1009 | do { | |
1010 | prev = local64_read(&event->hw.period_left); | |
1011 | val = prev - delta; | |
1012 | if (val < 1) | |
1013 | val = 1; | |
1014 | } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); | |
4574910e PM |
1015 | } |
1016 | ||
ab7ef2e5 PM |
1017 | /* |
1018 | * On some machines, PMC5 and PMC6 can't be written, don't respect | |
1019 | * the freeze conditions, and don't generate interrupts. This tells | |
cdd6c482 | 1020 | * us if `event' is using such a PMC. |
ab7ef2e5 PM |
1021 | */ |
1022 | static int is_limited_pmc(int pmcnum) | |
1023 | { | |
0bbd0d4b PM |
1024 | return (ppmu->flags & PPMU_LIMITED_PMC5_6) |
1025 | && (pmcnum == 5 || pmcnum == 6); | |
ab7ef2e5 PM |
1026 | } |
1027 | ||
a8f90e90 | 1028 | static void freeze_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1029 | unsigned long pmc5, unsigned long pmc6) |
1030 | { | |
cdd6c482 | 1031 | struct perf_event *event; |
ab7ef2e5 PM |
1032 | u64 val, prev, delta; |
1033 | int i; | |
1034 | ||
1035 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1036 | event = cpuhw->limited_counter[i]; |
cdd6c482 | 1037 | if (!event->hw.idx) |
ab7ef2e5 | 1038 | continue; |
cdd6c482 | 1039 | val = (event->hw.idx == 5) ? pmc5 : pmc6; |
e7850595 | 1040 | prev = local64_read(&event->hw.prev_count); |
cdd6c482 | 1041 | event->hw.idx = 0; |
86c74ab3 EM |
1042 | delta = check_and_compute_delta(prev, val); |
1043 | if (delta) | |
1044 | local64_add(delta, &event->count); | |
ab7ef2e5 PM |
1045 | } |
1046 | } | |
1047 | ||
a8f90e90 | 1048 | static void thaw_limited_counters(struct cpu_hw_events *cpuhw, |
ab7ef2e5 PM |
1049 | unsigned long pmc5, unsigned long pmc6) |
1050 | { | |
cdd6c482 | 1051 | struct perf_event *event; |
86c74ab3 | 1052 | u64 val, prev; |
ab7ef2e5 PM |
1053 | int i; |
1054 | ||
1055 | for (i = 0; i < cpuhw->n_limited; ++i) { | |
a8f90e90 | 1056 | event = cpuhw->limited_counter[i]; |
cdd6c482 IM |
1057 | event->hw.idx = cpuhw->limited_hwidx[i]; |
1058 | val = (event->hw.idx == 5) ? pmc5 : pmc6; | |
86c74ab3 EM |
1059 | prev = local64_read(&event->hw.prev_count); |
1060 | if (check_and_compute_delta(prev, val)) | |
1061 | local64_set(&event->hw.prev_count, val); | |
cdd6c482 | 1062 | perf_event_update_userpage(event); |
ab7ef2e5 PM |
1063 | } |
1064 | } | |
1065 | ||
1066 | /* | |
cdd6c482 | 1067 | * Since limited events don't respect the freeze conditions, we |
ab7ef2e5 | 1068 | * have to read them immediately after freezing or unfreezing the |
cdd6c482 IM |
1069 | * other events. We try to keep the values from the limited |
1070 | * events as consistent as possible by keeping the delay (in | |
ab7ef2e5 | 1071 | * cycles and instructions) between freezing/unfreezing and reading |
cdd6c482 IM |
1072 | * the limited events as small and consistent as possible. |
1073 | * Therefore, if any limited events are in use, we read them | |
ab7ef2e5 PM |
1074 | * both, and always in the same order, to minimize variability, |
1075 | * and do it inside the same asm that writes MMCR0. | |
1076 | */ | |
cdd6c482 | 1077 | static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) |
ab7ef2e5 PM |
1078 | { |
1079 | unsigned long pmc5, pmc6; | |
1080 | ||
1081 | if (!cpuhw->n_limited) { | |
1082 | mtspr(SPRN_MMCR0, mmcr0); | |
1083 | return; | |
1084 | } | |
1085 | ||
1086 | /* | |
1087 | * Write MMCR0, then read PMC5 and PMC6 immediately. | |
dcd945e0 PM |
1088 | * To ensure we don't get a performance monitor interrupt |
1089 | * between writing MMCR0 and freezing/thawing the limited | |
cdd6c482 | 1090 | * events, we first write MMCR0 with the event overflow |
dcd945e0 | 1091 | * interrupt enable bits turned off. |
ab7ef2e5 PM |
1092 | */ |
1093 | asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" | |
1094 | : "=&r" (pmc5), "=&r" (pmc6) | |
dcd945e0 PM |
1095 | : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), |
1096 | "i" (SPRN_MMCR0), | |
ab7ef2e5 PM |
1097 | "i" (SPRN_PMC5), "i" (SPRN_PMC6)); |
1098 | ||
1099 | if (mmcr0 & MMCR0_FC) | |
a8f90e90 | 1100 | freeze_limited_counters(cpuhw, pmc5, pmc6); |
ab7ef2e5 | 1101 | else |
a8f90e90 | 1102 | thaw_limited_counters(cpuhw, pmc5, pmc6); |
dcd945e0 PM |
1103 | |
1104 | /* | |
cdd6c482 | 1105 | * Write the full MMCR0 including the event overflow interrupt |
dcd945e0 PM |
1106 | * enable bits, if necessary. |
1107 | */ | |
1108 | if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1109 | mtspr(SPRN_MMCR0, mmcr0); | |
ab7ef2e5 PM |
1110 | } |
1111 | ||
4574910e | 1112 | /* |
cdd6c482 IM |
1113 | * Disable all events to prevent PMU interrupts and to allow |
1114 | * events to be added or removed. | |
4574910e | 1115 | */ |
a4eaf7f1 | 1116 | static void power_pmu_disable(struct pmu *pmu) |
4574910e | 1117 | { |
cdd6c482 | 1118 | struct cpu_hw_events *cpuhw; |
330a1eb7 | 1119 | unsigned long flags, mmcr0, val; |
4574910e | 1120 | |
f36a1a13 PM |
1121 | if (!ppmu) |
1122 | return; | |
4574910e | 1123 | local_irq_save(flags); |
cdd6c482 | 1124 | cpuhw = &__get_cpu_var(cpu_hw_events); |
4574910e | 1125 | |
448d64f8 | 1126 | if (!cpuhw->disabled) { |
01d0287f PM |
1127 | /* |
1128 | * Check if we ever enabled the PMU on this cpu. | |
1129 | */ | |
1130 | if (!cpuhw->pmcs_enabled) { | |
a6dbf93a | 1131 | ppc_enable_pmcs(); |
01d0287f PM |
1132 | cpuhw->pmcs_enabled = 1; |
1133 | } | |
1134 | ||
378a6ee9 | 1135 | /* |
76cb8a78 | 1136 | * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 |
378a6ee9 | 1137 | */ |
330a1eb7 | 1138 | val = mmcr0 = mfspr(SPRN_MMCR0); |
378a6ee9 | 1139 | val |= MMCR0_FC; |
76cb8a78 ME |
1140 | val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | |
1141 | MMCR0_FC56); | |
378a6ee9 ME |
1142 | |
1143 | /* | |
1144 | * The barrier is to make sure the mtspr has been | |
1145 | * executed and the PMU has frozen the events etc. | |
1146 | * before we return. | |
1147 | */ | |
1148 | write_mmcr0(cpuhw, val); | |
1149 | mb(); | |
1150 | ||
f708223d PM |
1151 | /* |
1152 | * Disable instruction sampling if it was enabled | |
1153 | */ | |
1154 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1155 | mtspr(SPRN_MMCRA, | |
1156 | cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); | |
1157 | mb(); | |
1158 | } | |
1159 | ||
378a6ee9 ME |
1160 | cpuhw->disabled = 1; |
1161 | cpuhw->n_added = 0; | |
330a1eb7 ME |
1162 | |
1163 | ebb_switch_out(mmcr0); | |
4574910e | 1164 | } |
330a1eb7 | 1165 | |
4574910e | 1166 | local_irq_restore(flags); |
4574910e PM |
1167 | } |
1168 | ||
1169 | /* | |
cdd6c482 IM |
1170 | * Re-enable all events if disable == 0. |
1171 | * If we were previously disabled and events were added, then | |
4574910e PM |
1172 | * put the new config on the PMU. |
1173 | */ | |
a4eaf7f1 | 1174 | static void power_pmu_enable(struct pmu *pmu) |
4574910e | 1175 | { |
cdd6c482 IM |
1176 | struct perf_event *event; |
1177 | struct cpu_hw_events *cpuhw; | |
4574910e PM |
1178 | unsigned long flags; |
1179 | long i; | |
330a1eb7 | 1180 | unsigned long val, mmcr0; |
4574910e | 1181 | s64 left; |
cdd6c482 | 1182 | unsigned int hwc_index[MAX_HWEVENTS]; |
ab7ef2e5 PM |
1183 | int n_lim; |
1184 | int idx; | |
330a1eb7 | 1185 | bool ebb; |
4574910e | 1186 | |
f36a1a13 PM |
1187 | if (!ppmu) |
1188 | return; | |
4574910e | 1189 | local_irq_save(flags); |
0a48843d | 1190 | |
cdd6c482 | 1191 | cpuhw = &__get_cpu_var(cpu_hw_events); |
0a48843d ME |
1192 | if (!cpuhw->disabled) |
1193 | goto out; | |
1194 | ||
4ea355b5 ME |
1195 | if (cpuhw->n_events == 0) { |
1196 | ppc_set_pmu_inuse(0); | |
1197 | goto out; | |
1198 | } | |
1199 | ||
4574910e PM |
1200 | cpuhw->disabled = 0; |
1201 | ||
330a1eb7 ME |
1202 | /* |
1203 | * EBB requires an exclusive group and all events must have the EBB | |
1204 | * flag set, or not set, so we can just check a single event. Also we | |
1205 | * know we have at least one event. | |
1206 | */ | |
1207 | ebb = is_ebb_event(cpuhw->event[0]); | |
1208 | ||
4574910e | 1209 | /* |
cdd6c482 | 1210 | * If we didn't change anything, or only removed events, |
4574910e PM |
1211 | * no need to recalculate MMCR* settings and reset the PMCs. |
1212 | * Just reenable the PMU with the current MMCR* settings | |
cdd6c482 | 1213 | * (possibly updated for removal of events). |
4574910e PM |
1214 | */ |
1215 | if (!cpuhw->n_added) { | |
f708223d | 1216 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e | 1217 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
f708223d | 1218 | goto out_enable; |
4574910e PM |
1219 | } |
1220 | ||
1221 | /* | |
cdd6c482 | 1222 | * Compute MMCR* values for the new set of events |
4574910e | 1223 | */ |
cdd6c482 | 1224 | if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, |
4574910e PM |
1225 | cpuhw->mmcr)) { |
1226 | /* shouldn't ever get here */ | |
1227 | printk(KERN_ERR "oops compute_mmcr failed\n"); | |
1228 | goto out; | |
1229 | } | |
1230 | ||
0475f9ea PM |
1231 | /* |
1232 | * Add in MMCR0 freeze bits corresponding to the | |
cdd6c482 IM |
1233 | * attr.exclude_* bits for the first event. |
1234 | * We have already checked that all events have the | |
1235 | * same values for these bits as the first event. | |
0475f9ea | 1236 | */ |
cdd6c482 IM |
1237 | event = cpuhw->event[0]; |
1238 | if (event->attr.exclude_user) | |
0475f9ea | 1239 | cpuhw->mmcr[0] |= MMCR0_FCP; |
cdd6c482 IM |
1240 | if (event->attr.exclude_kernel) |
1241 | cpuhw->mmcr[0] |= freeze_events_kernel; | |
1242 | if (event->attr.exclude_hv) | |
0475f9ea PM |
1243 | cpuhw->mmcr[0] |= MMCR0_FCHV; |
1244 | ||
4574910e PM |
1245 | /* |
1246 | * Write the new configuration to MMCR* with the freeze | |
cdd6c482 IM |
1247 | * bit set and set the hardware events to their initial values. |
1248 | * Then unfreeze the events. | |
4574910e | 1249 | */ |
a6dbf93a | 1250 | ppc_set_pmu_inuse(1); |
f708223d | 1251 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); |
4574910e PM |
1252 | mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); |
1253 | mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) | |
1254 | | MMCR0_FC); | |
1255 | ||
1256 | /* | |
cdd6c482 | 1257 | * Read off any pre-existing events that need to move |
4574910e PM |
1258 | * to another PMC. |
1259 | */ | |
cdd6c482 IM |
1260 | for (i = 0; i < cpuhw->n_events; ++i) { |
1261 | event = cpuhw->event[i]; | |
1262 | if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { | |
1263 | power_pmu_read(event); | |
1264 | write_pmc(event->hw.idx, 0); | |
1265 | event->hw.idx = 0; | |
4574910e PM |
1266 | } |
1267 | } | |
1268 | ||
1269 | /* | |
cdd6c482 | 1270 | * Initialize the PMCs for all the new and moved events. |
4574910e | 1271 | */ |
ab7ef2e5 | 1272 | cpuhw->n_limited = n_lim = 0; |
cdd6c482 IM |
1273 | for (i = 0; i < cpuhw->n_events; ++i) { |
1274 | event = cpuhw->event[i]; | |
1275 | if (event->hw.idx) | |
4574910e | 1276 | continue; |
ab7ef2e5 PM |
1277 | idx = hwc_index[i] + 1; |
1278 | if (is_limited_pmc(idx)) { | |
a8f90e90 | 1279 | cpuhw->limited_counter[n_lim] = event; |
ab7ef2e5 PM |
1280 | cpuhw->limited_hwidx[n_lim] = idx; |
1281 | ++n_lim; | |
1282 | continue; | |
1283 | } | |
330a1eb7 ME |
1284 | |
1285 | if (ebb) | |
1286 | val = local64_read(&event->hw.prev_count); | |
1287 | else { | |
1288 | val = 0; | |
1289 | if (event->hw.sample_period) { | |
1290 | left = local64_read(&event->hw.period_left); | |
1291 | if (left < 0x80000000L) | |
1292 | val = 0x80000000L - left; | |
1293 | } | |
1294 | local64_set(&event->hw.prev_count, val); | |
4574910e | 1295 | } |
330a1eb7 | 1296 | |
cdd6c482 | 1297 | event->hw.idx = idx; |
a4eaf7f1 PZ |
1298 | if (event->hw.state & PERF_HES_STOPPED) |
1299 | val = 0; | |
ab7ef2e5 | 1300 | write_pmc(idx, val); |
330a1eb7 | 1301 | |
cdd6c482 | 1302 | perf_event_update_userpage(event); |
4574910e | 1303 | } |
ab7ef2e5 | 1304 | cpuhw->n_limited = n_lim; |
4574910e | 1305 | cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; |
f708223d PM |
1306 | |
1307 | out_enable: | |
c2e37a26 ME |
1308 | pmao_restore_workaround(ebb); |
1309 | ||
8903461c ME |
1310 | if (ppmu->flags & PPMU_ARCH_207S) |
1311 | mtspr(SPRN_MMCR2, 0); | |
1312 | ||
330a1eb7 ME |
1313 | mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]); |
1314 | ||
f708223d | 1315 | mb(); |
b4d6c06c AK |
1316 | if (cpuhw->bhrb_users) |
1317 | ppmu->config_bhrb(cpuhw->bhrb_filter); | |
1318 | ||
330a1eb7 | 1319 | write_mmcr0(cpuhw, mmcr0); |
4574910e | 1320 | |
f708223d PM |
1321 | /* |
1322 | * Enable instruction sampling if necessary | |
1323 | */ | |
1324 | if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { | |
1325 | mb(); | |
1326 | mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); | |
1327 | } | |
1328 | ||
4574910e | 1329 | out: |
3925f46b | 1330 | |
4574910e PM |
1331 | local_irq_restore(flags); |
1332 | } | |
1333 | ||
cdd6c482 IM |
1334 | static int collect_events(struct perf_event *group, int max_count, |
1335 | struct perf_event *ctrs[], u64 *events, | |
ab7ef2e5 | 1336 | unsigned int *flags) |
4574910e PM |
1337 | { |
1338 | int n = 0; | |
cdd6c482 | 1339 | struct perf_event *event; |
4574910e | 1340 | |
cdd6c482 | 1341 | if (!is_software_event(group)) { |
4574910e PM |
1342 | if (n >= max_count) |
1343 | return -1; | |
1344 | ctrs[n] = group; | |
cdd6c482 | 1345 | flags[n] = group->hw.event_base; |
4574910e PM |
1346 | events[n++] = group->hw.config; |
1347 | } | |
a8f90e90 | 1348 | list_for_each_entry(event, &group->sibling_list, group_entry) { |
cdd6c482 IM |
1349 | if (!is_software_event(event) && |
1350 | event->state != PERF_EVENT_STATE_OFF) { | |
4574910e PM |
1351 | if (n >= max_count) |
1352 | return -1; | |
cdd6c482 IM |
1353 | ctrs[n] = event; |
1354 | flags[n] = event->hw.event_base; | |
1355 | events[n++] = event->hw.config; | |
4574910e PM |
1356 | } |
1357 | } | |
1358 | return n; | |
1359 | } | |
1360 | ||
4574910e | 1361 | /* |
cdd6c482 IM |
1362 | * Add a event to the PMU. |
1363 | * If all events are not already frozen, then we disable and | |
9e35ad38 | 1364 | * re-enable the PMU in order to get hw_perf_enable to do the |
4574910e PM |
1365 | * actual work of reconfiguring the PMU. |
1366 | */ | |
a4eaf7f1 | 1367 | static int power_pmu_add(struct perf_event *event, int ef_flags) |
4574910e | 1368 | { |
cdd6c482 | 1369 | struct cpu_hw_events *cpuhw; |
4574910e | 1370 | unsigned long flags; |
4574910e PM |
1371 | int n0; |
1372 | int ret = -EAGAIN; | |
1373 | ||
1374 | local_irq_save(flags); | |
33696fc0 | 1375 | perf_pmu_disable(event->pmu); |
4574910e PM |
1376 | |
1377 | /* | |
cdd6c482 | 1378 | * Add the event to the list (if there is room) |
4574910e PM |
1379 | * and check whether the total set is still feasible. |
1380 | */ | |
cdd6c482 IM |
1381 | cpuhw = &__get_cpu_var(cpu_hw_events); |
1382 | n0 = cpuhw->n_events; | |
a8f90e90 | 1383 | if (n0 >= ppmu->n_counter) |
4574910e | 1384 | goto out; |
cdd6c482 IM |
1385 | cpuhw->event[n0] = event; |
1386 | cpuhw->events[n0] = event->hw.config; | |
1387 | cpuhw->flags[n0] = event->hw.event_base; | |
8e6d5573 | 1388 | |
f53d168c | 1389 | /* |
1390 | * This event may have been disabled/stopped in record_and_restart() | |
1391 | * because we exceeded the ->event_limit. If re-starting the event, | |
1392 | * clear the ->hw.state (STOPPED and UPTODATE flags), so the user | |
1393 | * notification is re-enabled. | |
1394 | */ | |
a4eaf7f1 PZ |
1395 | if (!(ef_flags & PERF_EF_START)) |
1396 | event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
f53d168c | 1397 | else |
1398 | event->hw.state = 0; | |
a4eaf7f1 | 1399 | |
8e6d5573 LM |
1400 | /* |
1401 | * If group events scheduling transaction was started, | |
25985edc | 1402 | * skip the schedulability test here, it will be performed |
8e6d5573 LM |
1403 | * at commit time(->commit_txn) as a whole |
1404 | */ | |
8d2cacbb | 1405 | if (cpuhw->group_flag & PERF_EVENT_TXN) |
8e6d5573 LM |
1406 | goto nocheck; |
1407 | ||
cdd6c482 | 1408 | if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) |
0475f9ea | 1409 | goto out; |
e51ee31e | 1410 | if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) |
4574910e | 1411 | goto out; |
cdd6c482 | 1412 | event->hw.config = cpuhw->events[n0]; |
8e6d5573 LM |
1413 | |
1414 | nocheck: | |
330a1eb7 ME |
1415 | ebb_event_add(event); |
1416 | ||
cdd6c482 | 1417 | ++cpuhw->n_events; |
4574910e PM |
1418 | ++cpuhw->n_added; |
1419 | ||
1420 | ret = 0; | |
1421 | out: | |
ff3d79dc | 1422 | if (has_branch_stack(event)) { |
3925f46b | 1423 | power_pmu_bhrb_enable(event); |
ff3d79dc AK |
1424 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( |
1425 | event->attr.branch_sample_type); | |
1426 | } | |
3925f46b | 1427 | |
33696fc0 | 1428 | perf_pmu_enable(event->pmu); |
4574910e PM |
1429 | local_irq_restore(flags); |
1430 | return ret; | |
1431 | } | |
1432 | ||
1433 | /* | |
cdd6c482 | 1434 | * Remove a event from the PMU. |
4574910e | 1435 | */ |
a4eaf7f1 | 1436 | static void power_pmu_del(struct perf_event *event, int ef_flags) |
4574910e | 1437 | { |
cdd6c482 | 1438 | struct cpu_hw_events *cpuhw; |
4574910e | 1439 | long i; |
4574910e PM |
1440 | unsigned long flags; |
1441 | ||
1442 | local_irq_save(flags); | |
33696fc0 | 1443 | perf_pmu_disable(event->pmu); |
4574910e | 1444 | |
cdd6c482 IM |
1445 | power_pmu_read(event); |
1446 | ||
1447 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1448 | for (i = 0; i < cpuhw->n_events; ++i) { | |
1449 | if (event == cpuhw->event[i]) { | |
219a92a4 | 1450 | while (++i < cpuhw->n_events) { |
cdd6c482 | 1451 | cpuhw->event[i-1] = cpuhw->event[i]; |
219a92a4 ME |
1452 | cpuhw->events[i-1] = cpuhw->events[i]; |
1453 | cpuhw->flags[i-1] = cpuhw->flags[i]; | |
1454 | } | |
cdd6c482 IM |
1455 | --cpuhw->n_events; |
1456 | ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); | |
1457 | if (event->hw.idx) { | |
1458 | write_pmc(event->hw.idx, 0); | |
1459 | event->hw.idx = 0; | |
ab7ef2e5 | 1460 | } |
cdd6c482 | 1461 | perf_event_update_userpage(event); |
4574910e PM |
1462 | break; |
1463 | } | |
1464 | } | |
ab7ef2e5 | 1465 | for (i = 0; i < cpuhw->n_limited; ++i) |
a8f90e90 | 1466 | if (event == cpuhw->limited_counter[i]) |
ab7ef2e5 PM |
1467 | break; |
1468 | if (i < cpuhw->n_limited) { | |
1469 | while (++i < cpuhw->n_limited) { | |
a8f90e90 | 1470 | cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; |
ab7ef2e5 PM |
1471 | cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; |
1472 | } | |
1473 | --cpuhw->n_limited; | |
1474 | } | |
cdd6c482 IM |
1475 | if (cpuhw->n_events == 0) { |
1476 | /* disable exceptions if no events are running */ | |
4574910e PM |
1477 | cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); |
1478 | } | |
1479 | ||
3925f46b AK |
1480 | if (has_branch_stack(event)) |
1481 | power_pmu_bhrb_disable(event); | |
1482 | ||
33696fc0 | 1483 | perf_pmu_enable(event->pmu); |
4574910e PM |
1484 | local_irq_restore(flags); |
1485 | } | |
1486 | ||
8a7b8cb9 | 1487 | /* |
a4eaf7f1 PZ |
1488 | * POWER-PMU does not support disabling individual counters, hence |
1489 | * program their cycle counter to their max value and ignore the interrupts. | |
8a7b8cb9 | 1490 | */ |
a4eaf7f1 PZ |
1491 | |
1492 | static void power_pmu_start(struct perf_event *event, int ef_flags) | |
8a7b8cb9 | 1493 | { |
8a7b8cb9 | 1494 | unsigned long flags; |
a4eaf7f1 | 1495 | s64 left; |
9a45a940 | 1496 | unsigned long val; |
8a7b8cb9 | 1497 | |
cdd6c482 | 1498 | if (!event->hw.idx || !event->hw.sample_period) |
8a7b8cb9 | 1499 | return; |
a4eaf7f1 PZ |
1500 | |
1501 | if (!(event->hw.state & PERF_HES_STOPPED)) | |
1502 | return; | |
1503 | ||
1504 | if (ef_flags & PERF_EF_RELOAD) | |
1505 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1506 | ||
1507 | local_irq_save(flags); | |
1508 | perf_pmu_disable(event->pmu); | |
1509 | ||
1510 | event->hw.state = 0; | |
1511 | left = local64_read(&event->hw.period_left); | |
9a45a940 AB |
1512 | |
1513 | val = 0; | |
1514 | if (left < 0x80000000L) | |
1515 | val = 0x80000000L - left; | |
1516 | ||
1517 | write_pmc(event->hw.idx, val); | |
a4eaf7f1 PZ |
1518 | |
1519 | perf_event_update_userpage(event); | |
1520 | perf_pmu_enable(event->pmu); | |
1521 | local_irq_restore(flags); | |
1522 | } | |
1523 | ||
1524 | static void power_pmu_stop(struct perf_event *event, int ef_flags) | |
1525 | { | |
1526 | unsigned long flags; | |
1527 | ||
1528 | if (!event->hw.idx || !event->hw.sample_period) | |
1529 | return; | |
1530 | ||
1531 | if (event->hw.state & PERF_HES_STOPPED) | |
1532 | return; | |
1533 | ||
8a7b8cb9 | 1534 | local_irq_save(flags); |
33696fc0 | 1535 | perf_pmu_disable(event->pmu); |
a4eaf7f1 | 1536 | |
cdd6c482 | 1537 | power_pmu_read(event); |
a4eaf7f1 PZ |
1538 | event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
1539 | write_pmc(event->hw.idx, 0); | |
1540 | ||
cdd6c482 | 1541 | perf_event_update_userpage(event); |
33696fc0 | 1542 | perf_pmu_enable(event->pmu); |
8a7b8cb9 PM |
1543 | local_irq_restore(flags); |
1544 | } | |
1545 | ||
8e6d5573 LM |
1546 | /* |
1547 | * Start group events scheduling transaction | |
1548 | * Set the flag to make pmu::enable() not perform the | |
1549 | * schedulability test, it will be performed at commit time | |
1550 | */ | |
51b0fe39 | 1551 | void power_pmu_start_txn(struct pmu *pmu) |
8e6d5573 LM |
1552 | { |
1553 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1554 | ||
33696fc0 | 1555 | perf_pmu_disable(pmu); |
8d2cacbb | 1556 | cpuhw->group_flag |= PERF_EVENT_TXN; |
8e6d5573 LM |
1557 | cpuhw->n_txn_start = cpuhw->n_events; |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * Stop group events scheduling transaction | |
1562 | * Clear the flag and pmu::enable() will perform the | |
1563 | * schedulability test. | |
1564 | */ | |
51b0fe39 | 1565 | void power_pmu_cancel_txn(struct pmu *pmu) |
8e6d5573 LM |
1566 | { |
1567 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1568 | ||
8d2cacbb | 1569 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1570 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1571 | } |
1572 | ||
1573 | /* | |
1574 | * Commit group events scheduling transaction | |
1575 | * Perform the group schedulability test as a whole | |
1576 | * Return 0 if success | |
1577 | */ | |
51b0fe39 | 1578 | int power_pmu_commit_txn(struct pmu *pmu) |
8e6d5573 LM |
1579 | { |
1580 | struct cpu_hw_events *cpuhw; | |
1581 | long i, n; | |
1582 | ||
1583 | if (!ppmu) | |
1584 | return -EAGAIN; | |
1585 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1586 | n = cpuhw->n_events; | |
1587 | if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) | |
1588 | return -EAGAIN; | |
1589 | i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); | |
1590 | if (i < 0) | |
1591 | return -EAGAIN; | |
1592 | ||
1593 | for (i = cpuhw->n_txn_start; i < n; ++i) | |
1594 | cpuhw->event[i]->hw.config = cpuhw->events[i]; | |
1595 | ||
8d2cacbb | 1596 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1597 | perf_pmu_enable(pmu); |
8e6d5573 LM |
1598 | return 0; |
1599 | } | |
1600 | ||
ab7ef2e5 | 1601 | /* |
cdd6c482 | 1602 | * Return 1 if we might be able to put event on a limited PMC, |
ab7ef2e5 | 1603 | * or 0 if not. |
cdd6c482 | 1604 | * A event can only go on a limited PMC if it counts something |
ab7ef2e5 PM |
1605 | * that a limited PMC can count, doesn't require interrupts, and |
1606 | * doesn't exclude any processor mode. | |
1607 | */ | |
cdd6c482 | 1608 | static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, |
ab7ef2e5 PM |
1609 | unsigned int flags) |
1610 | { | |
1611 | int n; | |
ef923214 | 1612 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 | 1613 | |
cdd6c482 IM |
1614 | if (event->attr.exclude_user |
1615 | || event->attr.exclude_kernel | |
1616 | || event->attr.exclude_hv | |
1617 | || event->attr.sample_period) | |
ab7ef2e5 PM |
1618 | return 0; |
1619 | ||
1620 | if (ppmu->limited_pmc_event(ev)) | |
1621 | return 1; | |
1622 | ||
1623 | /* | |
cdd6c482 | 1624 | * The requested event_id isn't on a limited PMC already; |
ab7ef2e5 PM |
1625 | * see if any alternative code goes on a limited PMC. |
1626 | */ | |
1627 | if (!ppmu->get_alternatives) | |
1628 | return 0; | |
1629 | ||
1630 | flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; | |
1631 | n = ppmu->get_alternatives(ev, flags, alt); | |
ab7ef2e5 | 1632 | |
ef923214 | 1633 | return n > 0; |
ab7ef2e5 PM |
1634 | } |
1635 | ||
1636 | /* | |
cdd6c482 IM |
1637 | * Find an alternative event_id that goes on a normal PMC, if possible, |
1638 | * and return the event_id code, or 0 if there is no such alternative. | |
1639 | * (Note: event_id code 0 is "don't count" on all machines.) | |
ab7ef2e5 | 1640 | */ |
ef923214 | 1641 | static u64 normal_pmc_alternative(u64 ev, unsigned long flags) |
ab7ef2e5 | 1642 | { |
ef923214 | 1643 | u64 alt[MAX_EVENT_ALTERNATIVES]; |
ab7ef2e5 PM |
1644 | int n; |
1645 | ||
1646 | flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); | |
1647 | n = ppmu->get_alternatives(ev, flags, alt); | |
1648 | if (!n) | |
1649 | return 0; | |
1650 | return alt[0]; | |
1651 | } | |
1652 | ||
cdd6c482 IM |
1653 | /* Number of perf_events counting hardware events */ |
1654 | static atomic_t num_events; | |
7595d63b PM |
1655 | /* Used to avoid races in calling reserve/release_pmc_hardware */ |
1656 | static DEFINE_MUTEX(pmc_reserve_mutex); | |
1657 | ||
1658 | /* | |
cdd6c482 | 1659 | * Release the PMU if this is the last perf_event. |
7595d63b | 1660 | */ |
cdd6c482 | 1661 | static void hw_perf_event_destroy(struct perf_event *event) |
7595d63b | 1662 | { |
cdd6c482 | 1663 | if (!atomic_add_unless(&num_events, -1, 1)) { |
7595d63b | 1664 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 1665 | if (atomic_dec_return(&num_events) == 0) |
7595d63b PM |
1666 | release_pmc_hardware(); |
1667 | mutex_unlock(&pmc_reserve_mutex); | |
1668 | } | |
1669 | } | |
1670 | ||
106b506c | 1671 | /* |
cdd6c482 | 1672 | * Translate a generic cache event_id config to a raw event_id code. |
106b506c PM |
1673 | */ |
1674 | static int hw_perf_cache_event(u64 config, u64 *eventp) | |
1675 | { | |
1676 | unsigned long type, op, result; | |
1677 | int ev; | |
1678 | ||
1679 | if (!ppmu->cache_events) | |
1680 | return -EINVAL; | |
1681 | ||
1682 | /* unpack config */ | |
1683 | type = config & 0xff; | |
1684 | op = (config >> 8) & 0xff; | |
1685 | result = (config >> 16) & 0xff; | |
1686 | ||
1687 | if (type >= PERF_COUNT_HW_CACHE_MAX || | |
1688 | op >= PERF_COUNT_HW_CACHE_OP_MAX || | |
1689 | result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
1690 | return -EINVAL; | |
1691 | ||
1692 | ev = (*ppmu->cache_events)[type][op][result]; | |
1693 | if (ev == 0) | |
1694 | return -EOPNOTSUPP; | |
1695 | if (ev == -1) | |
1696 | return -EINVAL; | |
1697 | *eventp = ev; | |
1698 | return 0; | |
1699 | } | |
1700 | ||
b0a873eb | 1701 | static int power_pmu_event_init(struct perf_event *event) |
4574910e | 1702 | { |
ef923214 PM |
1703 | u64 ev; |
1704 | unsigned long flags; | |
cdd6c482 IM |
1705 | struct perf_event *ctrs[MAX_HWEVENTS]; |
1706 | u64 events[MAX_HWEVENTS]; | |
1707 | unsigned int cflags[MAX_HWEVENTS]; | |
4574910e | 1708 | int n; |
7595d63b | 1709 | int err; |
cdd6c482 | 1710 | struct cpu_hw_events *cpuhw; |
4574910e PM |
1711 | |
1712 | if (!ppmu) | |
b0a873eb PZ |
1713 | return -ENOENT; |
1714 | ||
3925f46b AK |
1715 | if (has_branch_stack(event)) { |
1716 | /* PMU has BHRB enabled */ | |
4d9690dd | 1717 | if (!(ppmu->flags & PPMU_ARCH_207S)) |
3925f46b AK |
1718 | return -EOPNOTSUPP; |
1719 | } | |
2481c5fa | 1720 | |
cdd6c482 | 1721 | switch (event->attr.type) { |
106b506c | 1722 | case PERF_TYPE_HARDWARE: |
cdd6c482 | 1723 | ev = event->attr.config; |
9aaa131a | 1724 | if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) |
b0a873eb | 1725 | return -EOPNOTSUPP; |
4574910e | 1726 | ev = ppmu->generic_events[ev]; |
106b506c PM |
1727 | break; |
1728 | case PERF_TYPE_HW_CACHE: | |
cdd6c482 | 1729 | err = hw_perf_cache_event(event->attr.config, &ev); |
106b506c | 1730 | if (err) |
b0a873eb | 1731 | return err; |
106b506c PM |
1732 | break; |
1733 | case PERF_TYPE_RAW: | |
cdd6c482 | 1734 | ev = event->attr.config; |
106b506c | 1735 | break; |
90c8f954 | 1736 | default: |
b0a873eb | 1737 | return -ENOENT; |
4574910e | 1738 | } |
b0a873eb | 1739 | |
cdd6c482 IM |
1740 | event->hw.config_base = ev; |
1741 | event->hw.idx = 0; | |
4574910e | 1742 | |
0475f9ea PM |
1743 | /* |
1744 | * If we are not running on a hypervisor, force the | |
1745 | * exclude_hv bit to 0 so that we don't care what | |
d095cd46 | 1746 | * the user set it to. |
0475f9ea PM |
1747 | */ |
1748 | if (!firmware_has_feature(FW_FEATURE_LPAR)) | |
cdd6c482 | 1749 | event->attr.exclude_hv = 0; |
ab7ef2e5 PM |
1750 | |
1751 | /* | |
cdd6c482 | 1752 | * If this is a per-task event, then we can use |
ab7ef2e5 PM |
1753 | * PM_RUN_* events interchangeably with their non RUN_* |
1754 | * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. | |
1755 | * XXX we should check if the task is an idle task. | |
1756 | */ | |
1757 | flags = 0; | |
57fa7214 | 1758 | if (event->attach_state & PERF_ATTACH_TASK) |
ab7ef2e5 PM |
1759 | flags |= PPMU_ONLY_COUNT_RUN; |
1760 | ||
1761 | /* | |
cdd6c482 IM |
1762 | * If this machine has limited events, check whether this |
1763 | * event_id could go on a limited event. | |
ab7ef2e5 | 1764 | */ |
0bbd0d4b | 1765 | if (ppmu->flags & PPMU_LIMITED_PMC5_6) { |
cdd6c482 | 1766 | if (can_go_on_limited_pmc(event, ev, flags)) { |
ab7ef2e5 PM |
1767 | flags |= PPMU_LIMITED_PMC_OK; |
1768 | } else if (ppmu->limited_pmc_event(ev)) { | |
1769 | /* | |
cdd6c482 | 1770 | * The requested event_id is on a limited PMC, |
ab7ef2e5 PM |
1771 | * but we can't use a limited PMC; see if any |
1772 | * alternative goes on a normal PMC. | |
1773 | */ | |
1774 | ev = normal_pmc_alternative(ev, flags); | |
1775 | if (!ev) | |
b0a873eb | 1776 | return -EINVAL; |
ab7ef2e5 PM |
1777 | } |
1778 | } | |
1779 | ||
330a1eb7 ME |
1780 | /* Extra checks for EBB */ |
1781 | err = ebb_event_check(event); | |
1782 | if (err) | |
1783 | return err; | |
1784 | ||
4574910e PM |
1785 | /* |
1786 | * If this is in a group, check if it can go on with all the | |
cdd6c482 | 1787 | * other hardware events in the group. We assume the event |
4574910e PM |
1788 | * hasn't been linked into its leader's sibling list at this point. |
1789 | */ | |
1790 | n = 0; | |
cdd6c482 | 1791 | if (event->group_leader != event) { |
a8f90e90 | 1792 | n = collect_events(event->group_leader, ppmu->n_counter - 1, |
ab7ef2e5 | 1793 | ctrs, events, cflags); |
4574910e | 1794 | if (n < 0) |
b0a873eb | 1795 | return -EINVAL; |
4574910e | 1796 | } |
0475f9ea | 1797 | events[n] = ev; |
cdd6c482 | 1798 | ctrs[n] = event; |
ab7ef2e5 PM |
1799 | cflags[n] = flags; |
1800 | if (check_excludes(ctrs, cflags, n, 1)) | |
b0a873eb | 1801 | return -EINVAL; |
e51ee31e | 1802 | |
cdd6c482 | 1803 | cpuhw = &get_cpu_var(cpu_hw_events); |
e51ee31e | 1804 | err = power_check_constraints(cpuhw, events, cflags, n + 1); |
3925f46b AK |
1805 | |
1806 | if (has_branch_stack(event)) { | |
1807 | cpuhw->bhrb_filter = ppmu->bhrb_filter_map( | |
1808 | event->attr.branch_sample_type); | |
1809 | ||
1810 | if(cpuhw->bhrb_filter == -1) | |
1811 | return -EOPNOTSUPP; | |
1812 | } | |
1813 | ||
cdd6c482 | 1814 | put_cpu_var(cpu_hw_events); |
e51ee31e | 1815 | if (err) |
b0a873eb | 1816 | return -EINVAL; |
4574910e | 1817 | |
cdd6c482 IM |
1818 | event->hw.config = events[n]; |
1819 | event->hw.event_base = cflags[n]; | |
1820 | event->hw.last_period = event->hw.sample_period; | |
e7850595 | 1821 | local64_set(&event->hw.period_left, event->hw.last_period); |
7595d63b | 1822 | |
330a1eb7 ME |
1823 | /* |
1824 | * For EBB events we just context switch the PMC value, we don't do any | |
1825 | * of the sample_period logic. We use hw.prev_count for this. | |
1826 | */ | |
1827 | if (is_ebb_event(event)) | |
1828 | local64_set(&event->hw.prev_count, 0); | |
1829 | ||
7595d63b PM |
1830 | /* |
1831 | * See if we need to reserve the PMU. | |
cdd6c482 | 1832 | * If no events are currently in use, then we have to take a |
7595d63b PM |
1833 | * mutex to ensure that we don't race with another task doing |
1834 | * reserve_pmc_hardware or release_pmc_hardware. | |
1835 | */ | |
1836 | err = 0; | |
cdd6c482 | 1837 | if (!atomic_inc_not_zero(&num_events)) { |
7595d63b | 1838 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 IM |
1839 | if (atomic_read(&num_events) == 0 && |
1840 | reserve_pmc_hardware(perf_event_interrupt)) | |
7595d63b PM |
1841 | err = -EBUSY; |
1842 | else | |
cdd6c482 | 1843 | atomic_inc(&num_events); |
7595d63b PM |
1844 | mutex_unlock(&pmc_reserve_mutex); |
1845 | } | |
cdd6c482 | 1846 | event->destroy = hw_perf_event_destroy; |
7595d63b | 1847 | |
b0a873eb | 1848 | return err; |
4574910e PM |
1849 | } |
1850 | ||
35edc2a5 PZ |
1851 | static int power_pmu_event_idx(struct perf_event *event) |
1852 | { | |
1853 | return event->hw.idx; | |
1854 | } | |
1855 | ||
1c53a270 SB |
1856 | ssize_t power_events_sysfs_show(struct device *dev, |
1857 | struct device_attribute *attr, char *page) | |
1858 | { | |
1859 | struct perf_pmu_events_attr *pmu_attr; | |
1860 | ||
1861 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); | |
1862 | ||
1863 | return sprintf(page, "event=0x%02llx\n", pmu_attr->id); | |
1864 | } | |
1865 | ||
b0a873eb | 1866 | struct pmu power_pmu = { |
a4eaf7f1 PZ |
1867 | .pmu_enable = power_pmu_enable, |
1868 | .pmu_disable = power_pmu_disable, | |
b0a873eb | 1869 | .event_init = power_pmu_event_init, |
a4eaf7f1 PZ |
1870 | .add = power_pmu_add, |
1871 | .del = power_pmu_del, | |
1872 | .start = power_pmu_start, | |
1873 | .stop = power_pmu_stop, | |
b0a873eb | 1874 | .read = power_pmu_read, |
b0a873eb PZ |
1875 | .start_txn = power_pmu_start_txn, |
1876 | .cancel_txn = power_pmu_cancel_txn, | |
1877 | .commit_txn = power_pmu_commit_txn, | |
35edc2a5 | 1878 | .event_idx = power_pmu_event_idx, |
3925f46b | 1879 | .flush_branch_stack = power_pmu_flush_branch_stack, |
b0a873eb PZ |
1880 | }; |
1881 | ||
4574910e | 1882 | /* |
57c0c15b | 1883 | * A counter has overflowed; update its count and record |
4574910e PM |
1884 | * things if requested. Note that interrupts are hard-disabled |
1885 | * here so there is no possibility of being interrupted. | |
1886 | */ | |
cdd6c482 | 1887 | static void record_and_restart(struct perf_event *event, unsigned long val, |
a8b0ca17 | 1888 | struct pt_regs *regs) |
4574910e | 1889 | { |
cdd6c482 | 1890 | u64 period = event->hw.sample_period; |
4574910e PM |
1891 | s64 prev, delta, left; |
1892 | int record = 0; | |
1893 | ||
a4eaf7f1 PZ |
1894 | if (event->hw.state & PERF_HES_STOPPED) { |
1895 | write_pmc(event->hw.idx, 0); | |
1896 | return; | |
1897 | } | |
1898 | ||
4574910e | 1899 | /* we don't have to worry about interrupts here */ |
e7850595 | 1900 | prev = local64_read(&event->hw.prev_count); |
86c74ab3 | 1901 | delta = check_and_compute_delta(prev, val); |
e7850595 | 1902 | local64_add(delta, &event->count); |
4574910e PM |
1903 | |
1904 | /* | |
cdd6c482 | 1905 | * See if the total period for this event has expired, |
4574910e PM |
1906 | * and update for the next period. |
1907 | */ | |
1908 | val = 0; | |
e7850595 | 1909 | left = local64_read(&event->hw.period_left) - delta; |
e13e895f MN |
1910 | if (delta == 0) |
1911 | left++; | |
60db5e09 | 1912 | if (period) { |
4574910e | 1913 | if (left <= 0) { |
60db5e09 | 1914 | left += period; |
4574910e | 1915 | if (left <= 0) |
60db5e09 | 1916 | left = period; |
e6878835 | 1917 | record = siar_valid(regs); |
4bca770e | 1918 | event->hw.last_period = event->hw.sample_period; |
4574910e | 1919 | } |
98fb1807 PM |
1920 | if (left < 0x80000000LL) |
1921 | val = 0x80000000LL - left; | |
4574910e | 1922 | } |
4574910e | 1923 | |
a4eaf7f1 PZ |
1924 | write_pmc(event->hw.idx, val); |
1925 | local64_set(&event->hw.prev_count, val); | |
1926 | local64_set(&event->hw.period_left, left); | |
1927 | perf_event_update_userpage(event); | |
1928 | ||
4574910e PM |
1929 | /* |
1930 | * Finally record data if requested. | |
1931 | */ | |
0bbd0d4b | 1932 | if (record) { |
dc1d628a PZ |
1933 | struct perf_sample_data data; |
1934 | ||
fd0d000b | 1935 | perf_sample_data_init(&data, ~0ULL, event->hw.last_period); |
df1a132b | 1936 | |
cdd6c482 | 1937 | if (event->attr.sample_type & PERF_SAMPLE_ADDR) |
98fb1807 PM |
1938 | perf_get_data_addr(regs, &data.addr); |
1939 | ||
3925f46b AK |
1940 | if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { |
1941 | struct cpu_hw_events *cpuhw; | |
1942 | cpuhw = &__get_cpu_var(cpu_hw_events); | |
1943 | power_pmu_bhrb_read(cpuhw); | |
1944 | data.br_stack = &cpuhw->bhrb_stack; | |
1945 | } | |
1946 | ||
a8b0ca17 | 1947 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1948 | power_pmu_stop(event, 0); |
0bbd0d4b PM |
1949 | } |
1950 | } | |
1951 | ||
1952 | /* | |
1953 | * Called from generic code to get the misc flags (i.e. processor mode) | |
cdd6c482 | 1954 | * for an event_id. |
0bbd0d4b PM |
1955 | */ |
1956 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1957 | { | |
98fb1807 | 1958 | u32 flags = perf_get_misc_flags(regs); |
0bbd0d4b | 1959 | |
98fb1807 PM |
1960 | if (flags) |
1961 | return flags; | |
cdd6c482 IM |
1962 | return user_mode(regs) ? PERF_RECORD_MISC_USER : |
1963 | PERF_RECORD_MISC_KERNEL; | |
0bbd0d4b PM |
1964 | } |
1965 | ||
1966 | /* | |
1967 | * Called from generic code to get the instruction pointer | |
cdd6c482 | 1968 | * for an event_id. |
0bbd0d4b PM |
1969 | */ |
1970 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
1971 | { | |
33904054 | 1972 | bool use_siar = regs_use_siar(regs); |
0bbd0d4b | 1973 | |
e6878835 | 1974 | if (use_siar && siar_valid(regs)) |
75382aa7 | 1975 | return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); |
e6878835 | 1976 | else if (use_siar) |
1977 | return 0; // no valid instruction pointer | |
75382aa7 | 1978 | else |
1ce447b9 | 1979 | return regs->nip; |
4574910e PM |
1980 | } |
1981 | ||
bc09c219 | 1982 | static bool pmc_overflow_power7(unsigned long val) |
0837e324 | 1983 | { |
0837e324 AB |
1984 | /* |
1985 | * Events on POWER7 can roll back if a speculative event doesn't | |
1986 | * eventually complete. Unfortunately in some rare cases they will | |
1987 | * raise a performance monitor exception. We need to catch this to | |
1988 | * ensure we reset the PMC. In all cases the PMC will be 256 or less | |
1989 | * cycles from overflow. | |
1990 | * | |
1991 | * We only do this if the first pass fails to find any overflowing | |
1992 | * PMCs because a user might set a period of less than 256 and we | |
1993 | * don't want to mistakenly reset them. | |
1994 | */ | |
bc09c219 MN |
1995 | if ((0x80000000 - val) <= 256) |
1996 | return true; | |
1997 | ||
1998 | return false; | |
1999 | } | |
2000 | ||
2001 | static bool pmc_overflow(unsigned long val) | |
2002 | { | |
2003 | if ((int)val < 0) | |
0837e324 AB |
2004 | return true; |
2005 | ||
2006 | return false; | |
2007 | } | |
2008 | ||
4574910e PM |
2009 | /* |
2010 | * Performance monitor interrupt stuff | |
2011 | */ | |
cdd6c482 | 2012 | static void perf_event_interrupt(struct pt_regs *regs) |
4574910e | 2013 | { |
bc09c219 | 2014 | int i, j; |
cdd6c482 IM |
2015 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); |
2016 | struct perf_event *event; | |
bc09c219 MN |
2017 | unsigned long val[8]; |
2018 | int found, active; | |
ca8f2d7f PM |
2019 | int nmi; |
2020 | ||
ab7ef2e5 | 2021 | if (cpuhw->n_limited) |
a8f90e90 | 2022 | freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), |
ab7ef2e5 PM |
2023 | mfspr(SPRN_PMC6)); |
2024 | ||
98fb1807 | 2025 | perf_read_regs(regs); |
0bbd0d4b | 2026 | |
98fb1807 | 2027 | nmi = perf_intr_is_nmi(regs); |
ca8f2d7f PM |
2028 | if (nmi) |
2029 | nmi_enter(); | |
2030 | else | |
2031 | irq_enter(); | |
4574910e | 2032 | |
bc09c219 MN |
2033 | /* Read all the PMCs since we'll need them a bunch of times */ |
2034 | for (i = 0; i < ppmu->n_counter; ++i) | |
2035 | val[i] = read_pmc(i + 1); | |
2036 | ||
2037 | /* Try to find what caused the IRQ */ | |
2038 | found = 0; | |
2039 | for (i = 0; i < ppmu->n_counter; ++i) { | |
2040 | if (!pmc_overflow(val[i])) | |
ab7ef2e5 | 2041 | continue; |
bc09c219 MN |
2042 | if (is_limited_pmc(i + 1)) |
2043 | continue; /* these won't generate IRQs */ | |
2044 | /* | |
2045 | * We've found one that's overflowed. For active | |
2046 | * counters we need to log this. For inactive | |
2047 | * counters, we need to reset it anyway | |
2048 | */ | |
2049 | found = 1; | |
2050 | active = 0; | |
2051 | for (j = 0; j < cpuhw->n_events; ++j) { | |
2052 | event = cpuhw->event[j]; | |
2053 | if (event->hw.idx == (i + 1)) { | |
2054 | active = 1; | |
2055 | record_and_restart(event, val[i], regs); | |
2056 | break; | |
2057 | } | |
4574910e | 2058 | } |
bc09c219 MN |
2059 | if (!active) |
2060 | /* reset non active counters that have overflowed */ | |
2061 | write_pmc(i + 1, 0); | |
4574910e | 2062 | } |
bc09c219 MN |
2063 | if (!found && pvr_version_is(PVR_POWER7)) { |
2064 | /* check active counters for special buggy p7 overflow */ | |
2065 | for (i = 0; i < cpuhw->n_events; ++i) { | |
2066 | event = cpuhw->event[i]; | |
2067 | if (!event->hw.idx || is_limited_pmc(event->hw.idx)) | |
ab7ef2e5 | 2068 | continue; |
bc09c219 MN |
2069 | if (pmc_overflow_power7(val[event->hw.idx - 1])) { |
2070 | /* event has overflowed in a buggy way*/ | |
2071 | found = 1; | |
2072 | record_and_restart(event, | |
2073 | val[event->hw.idx - 1], | |
2074 | regs); | |
2075 | } | |
4574910e PM |
2076 | } |
2077 | } | |
6772faa1 | 2078 | if (!found && !nmi && printk_ratelimit()) |
bc09c219 | 2079 | printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); |
4574910e PM |
2080 | |
2081 | /* | |
2082 | * Reset MMCR0 to its normal value. This will set PMXE and | |
57c0c15b | 2083 | * clear FC (freeze counters) and PMAO (perf mon alert occurred) |
4574910e | 2084 | * and thus allow interrupts to occur again. |
cdd6c482 | 2085 | * XXX might want to use MSR.PM to keep the events frozen until |
4574910e PM |
2086 | * we get back out of this interrupt. |
2087 | */ | |
ab7ef2e5 | 2088 | write_mmcr0(cpuhw, cpuhw->mmcr[0]); |
4574910e | 2089 | |
ca8f2d7f PM |
2090 | if (nmi) |
2091 | nmi_exit(); | |
2092 | else | |
db4fb5ac | 2093 | irq_exit(); |
4574910e PM |
2094 | } |
2095 | ||
3f6da390 | 2096 | static void power_pmu_setup(int cpu) |
01d0287f | 2097 | { |
cdd6c482 | 2098 | struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); |
01d0287f | 2099 | |
f36a1a13 PM |
2100 | if (!ppmu) |
2101 | return; | |
01d0287f PM |
2102 | memset(cpuhw, 0, sizeof(*cpuhw)); |
2103 | cpuhw->mmcr[0] = MMCR0_FC; | |
2104 | } | |
2105 | ||
061d19f2 | 2106 | static int |
85cfabbc | 2107 | power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) |
3f6da390 PZ |
2108 | { |
2109 | unsigned int cpu = (long)hcpu; | |
2110 | ||
2111 | switch (action & ~CPU_TASKS_FROZEN) { | |
2112 | case CPU_UP_PREPARE: | |
2113 | power_pmu_setup(cpu); | |
2114 | break; | |
2115 | ||
2116 | default: | |
2117 | break; | |
2118 | } | |
2119 | ||
2120 | return NOTIFY_OK; | |
2121 | } | |
2122 | ||
061d19f2 | 2123 | int register_power_pmu(struct power_pmu *pmu) |
4574910e | 2124 | { |
079b3c56 PM |
2125 | if (ppmu) |
2126 | return -EBUSY; /* something's already registered */ | |
2127 | ||
2128 | ppmu = pmu; | |
2129 | pr_info("%s performance monitor hardware support registered\n", | |
2130 | pmu->name); | |
d095cd46 | 2131 | |
1c53a270 SB |
2132 | power_pmu.attr_groups = ppmu->attr_groups; |
2133 | ||
98fb1807 | 2134 | #ifdef MSR_HV |
d095cd46 PM |
2135 | /* |
2136 | * Use FCHV to ignore kernel events if MSR.HV is set. | |
2137 | */ | |
2138 | if (mfmsr() & MSR_HV) | |
cdd6c482 | 2139 | freeze_events_kernel = MMCR0_FCHV; |
98fb1807 | 2140 | #endif /* CONFIG_PPC64 */ |
d095cd46 | 2141 | |
2e80a82a | 2142 | perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 PZ |
2143 | perf_cpu_notifier(power_pmu_notifier); |
2144 | ||
4574910e PM |
2145 | return 0; |
2146 | } |